From b216da5a6aabd626243daea72f6c0746bf8c070c Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Tue, 11 Jun 2019 21:13:30 -0700 Subject: [PATCH] ram stdint + Quartus Files --- .DS_Store | Bin 8196 -> 8196 bytes kernel/vortex_test.dump | 3339 +- kernel/vortex_test.elf | Bin 15640 -> 15632 bytes kernel/vortex_test.hex | 804 +- kernel/vx_include/vx_front.c | 2 +- kernel/vx_os/vx_back/vx_back.c | 21 +- rtl/.DS_Store | Bin 0 -> 8196 bytes rtl/VX_csr_handler.v | 8 +- rtl/VX_define.v | 2 + rtl/VX_fetch.v | 46 +- rtl/VX_shared_memory.v | 2 +- rtl/Vortex.qpf | 30 + rtl/Vortex.qsf | 47 + rtl/clk_const.sdc | 1 + rtl/obj_dir/VVortex | Bin 0 -> 566140 bytes rtl/obj_dir/VVortex.cpp | 14783 ++ rtl/obj_dir/VVortex.h | 489 + rtl/obj_dir/VVortex.mk | 66 + rtl/obj_dir/VVortex_VX_context_slave.cpp | 8879 + rtl/obj_dir/VVortex_VX_context_slave.h | 257 + rtl/obj_dir/VVortex__ALL.a | Bin 0 -> 234568 bytes rtl/obj_dir/VVortex__ALLcls.cpp | 4 + rtl/obj_dir/VVortex__ALLcls.d | 5 + rtl/obj_dir/VVortex__ALLcls.o | Bin 0 -> 226860 bytes rtl/obj_dir/VVortex__ALLsup.cpp | 3 + rtl/obj_dir/VVortex__ALLsup.d | 4 + rtl/obj_dir/VVortex__ALLsup.o | Bin 0 -> 3876 bytes rtl/obj_dir/VVortex__Syms.cpp | 41 + rtl/obj_dir/VVortex__Syms.h | 42 + rtl/obj_dir/VVortex__ver.d | 1 + rtl/obj_dir/VVortex__verFiles.dat | 33 + rtl/obj_dir/VVortex_classes.mk | 39 + rtl/obj_dir/test_bench.d | 4 + rtl/obj_dir/test_bench.o | Bin 0 -> 66356 bytes rtl/obj_dir/verilated.d | 9 + rtl/obj_dir/verilated.o | Bin 0 -> 390432 bytes rtl/ram.h | 3 +- rtl/results.txt | 7 + rtl/test_bench.h | 22 +- rtl/worst_case_paths.rpt | 215904 ++++++++++++++++++++ 40 files changed, 242763 insertions(+), 2134 deletions(-) create mode 100644 rtl/.DS_Store create mode 100644 rtl/Vortex.qpf create mode 100644 rtl/Vortex.qsf create mode 100644 rtl/clk_const.sdc create mode 100755 rtl/obj_dir/VVortex create mode 100644 rtl/obj_dir/VVortex.cpp create mode 100644 rtl/obj_dir/VVortex.h create mode 100644 rtl/obj_dir/VVortex.mk create mode 100644 rtl/obj_dir/VVortex_VX_context_slave.cpp create mode 100644 rtl/obj_dir/VVortex_VX_context_slave.h create mode 100644 rtl/obj_dir/VVortex__ALL.a create mode 100644 rtl/obj_dir/VVortex__ALLcls.cpp create mode 100644 rtl/obj_dir/VVortex__ALLcls.d create mode 100644 rtl/obj_dir/VVortex__ALLcls.o create mode 100644 rtl/obj_dir/VVortex__ALLsup.cpp create mode 100644 rtl/obj_dir/VVortex__ALLsup.d create mode 100644 rtl/obj_dir/VVortex__ALLsup.o create mode 100644 rtl/obj_dir/VVortex__Syms.cpp create mode 100644 rtl/obj_dir/VVortex__Syms.h create mode 100644 rtl/obj_dir/VVortex__ver.d create mode 100644 rtl/obj_dir/VVortex__verFiles.dat create mode 100644 rtl/obj_dir/VVortex_classes.mk create mode 100644 rtl/obj_dir/test_bench.d create mode 100644 rtl/obj_dir/test_bench.o create mode 100644 rtl/obj_dir/verilated.d create mode 100644 rtl/obj_dir/verilated.o create mode 100644 rtl/worst_case_paths.rpt diff --git a/.DS_Store b/.DS_Store index e5107c3945c2079c5c57cd26bc93a3772942fbe5..55d4da2c40ab601e1cadd188dfd38d85f3953f58 100644 GIT binary patch delta 122 zcmZp1XmOa}&&akhU^hP_+h!gCM>ck5h9ZU%hMdU?0{tQ;rlvXyCML$UIttb1<_18v XvDxIq0;X_9c4AjHvrD* -80000020: 0bd010ef jal ra,800018dc
+80000020: 091010ef jal ra,800018b0
80000024: 00000073 ecall 80000028 : @@ -75,7 +75,7 @@ Disassembly of section .text: 800000d4 : 800000d4: 01000217 auipc tp,0x1000 -800000d8: 26020213 addi tp,tp,608 # 81000334 +800000d8: 25820213 addi tp,tp,600 # 8100032c 800000dc: 00022023 sw zero,0(tp) # 0 800000e0: 00122223 sw ra,4(tp) # 4 800000e4: 00222423 sw sp,8(tp) # 8 @@ -113,7 +113,7 @@ Disassembly of section .text: 80000164 : 80000164: 01000217 auipc tp,0x1000 -80000168: 1d020213 addi tp,tp,464 # 81000334 +80000168: 1c820213 addi tp,tp,456 # 8100032c 8000016c: 00022003 lw zero,0(tp) # 0 80000170: 00422083 lw ra,4(tp) # 4 80000174: 00822103 lw sp,8(tp) # 8 @@ -169,10 +169,10 @@ Disassembly of section .text: 80000224: 97478793 addi a5,a5,-1676 # 974 80000228: 02f70733 mul a4,a4,a5 8000022c: 810007b7 lui a5,0x81000 -80000230: 43478793 addi a5,a5,1076 # 81000434 +80000230: 42c78793 addi a5,a5,1068 # 8100042c 80000234: 00f707b3 add a5,a4,a5 80000238: 00078513 mv a0,a5 -8000023c: 45c000ef jal ra,80000698 +8000023c: 440000ef jal ra,8000067c 80000240: fec42783 lw a5,-20(s0) 80000244: 00178793 addi a5,a5,1 80000248: fef42623 sw a5,-20(s0) @@ -191,1532 +191,1521 @@ Disassembly of section .text: 80000274: 02812423 sw s0,40(sp) 80000278: 03a12223 sw s10,36(sp) 8000027c: 03010413 addi s0,sp,48 -80000280: 000d0793 mv a5,s10 -80000284: 00078593 mv a1,a5 -80000288: 810007b7 lui a5,0x81000 -8000028c: 04078513 addi a0,a5,64 # 81000040 -80000290: 664000ef jal ra,800008f4 -80000294: 00000013 nop -80000298: 00000013 nop -8000029c: 00000013 nop -800002a0: 00000013 nop -800002a4: 00000013 nop -800002a8: 00000013 nop -800002ac: 00000013 nop -800002b0: 00000013 nop -800002b4: 00000013 nop -800002b8: 00000013 nop -800002bc: 00000013 nop -800002c0: 00000013 nop -800002c4: 000d0713 mv a4,s10 -800002c8: 000017b7 lui a5,0x1 -800002cc: 97478793 addi a5,a5,-1676 # 974 -800002d0: 02f70733 mul a4,a4,a5 -800002d4: 810007b7 lui a5,0x81000 -800002d8: 43478793 addi a5,a5,1076 # 81000434 -800002dc: 00f707b3 add a5,a4,a5 -800002e0: 00078513 mv a0,a5 -800002e4: 4e0000ef jal ra,800007c4 -800002e8: 00050793 mv a5,a0 -800002ec: 02078a63 beqz a5,80000320 -800002f0: 000d0713 mv a4,s10 -800002f4: 810007b7 lui a5,0x81000 -800002f8: 00271713 slli a4,a4,0x2 -800002fc: 28c78793 addi a5,a5,652 # 8100028c -80000300: 00f707b3 add a5,a4,a5 -80000304: 00100713 li a4,1 -80000308: 00e7a023 sw a4,0(a5) -8000030c: 000d0793 mv a5,s10 -80000310: 00079663 bnez a5,8000031c -80000314: e51ff0ef jal ra,80000164 -80000318: 05c0006f j 80000374 -8000031c: 00000073 ecall -80000320: 000d0713 mv a4,s10 -80000324: 000017b7 lui a5,0x1 -80000328: 97478793 addi a5,a5,-1676 # 974 -8000032c: 02f70733 mul a4,a4,a5 -80000330: 810007b7 lui a5,0x81000 -80000334: 43478793 addi a5,a5,1076 # 81000434 -80000338: 00f707b3 add a5,a4,a5 -8000033c: fd840713 addi a4,s0,-40 -80000340: 00070593 mv a1,a4 -80000344: 00078513 mv a0,a5 -80000348: 3dc000ef jal ra,80000724 -8000034c: fe042783 lw a5,-32(s0) -80000350: 00078113 mv sp,a5 -80000354: fdc42783 lw a5,-36(s0) -80000358: fd842583 lw a1,-40(s0) -8000035c: fe442603 lw a2,-28(s0) -80000360: fe842683 lw a3,-24(s0) -80000364: fec42703 lw a4,-20(s0) -80000368: 00078513 mv a0,a5 -8000036c: cbdff0ef jal ra,80000028 -80000370: 00000073 ecall -80000374: 02c12083 lw ra,44(sp) -80000378: 02812403 lw s0,40(sp) -8000037c: 02412d03 lw s10,36(sp) -80000380: 03010113 addi sp,sp,48 -80000384: 00008067 ret +80000280: 00000013 nop +80000284: 000d0713 mv a4,s10 +80000288: 000017b7 lui a5,0x1 +8000028c: 97478793 addi a5,a5,-1676 # 974 +80000290: 02f70733 mul a4,a4,a5 +80000294: 810007b7 lui a5,0x81000 +80000298: 42c78793 addi a5,a5,1068 # 8100042c +8000029c: 00f707b3 add a5,a4,a5 +800002a0: 00078513 mv a0,a5 +800002a4: 504000ef jal ra,800007a8 +800002a8: 00050793 mv a5,a0 +800002ac: 02078a63 beqz a5,800002e0 +800002b0: 000d0713 mv a4,s10 +800002b4: 810007b7 lui a5,0x81000 +800002b8: 00271713 slli a4,a4,0x2 +800002bc: 28478793 addi a5,a5,644 # 81000284 +800002c0: 00f707b3 add a5,a4,a5 +800002c4: 00100713 li a4,1 +800002c8: 00e7a023 sw a4,0(a5) +800002cc: 000d0793 mv a5,s10 +800002d0: 00079663 bnez a5,800002dc +800002d4: e91ff0ef jal ra,80000164 +800002d8: 05c0006f j 80000334 +800002dc: 00000073 ecall +800002e0: 000d0713 mv a4,s10 +800002e4: 000017b7 lui a5,0x1 +800002e8: 97478793 addi a5,a5,-1676 # 974 +800002ec: 02f70733 mul a4,a4,a5 +800002f0: 810007b7 lui a5,0x81000 +800002f4: 42c78793 addi a5,a5,1068 # 8100042c +800002f8: 00f707b3 add a5,a4,a5 +800002fc: fd840713 addi a4,s0,-40 +80000300: 00070593 mv a1,a4 +80000304: 00078513 mv a0,a5 +80000308: 400000ef jal ra,80000708 +8000030c: fe042783 lw a5,-32(s0) +80000310: 00078113 mv sp,a5 +80000314: fdc42783 lw a5,-36(s0) +80000318: fd842583 lw a1,-40(s0) +8000031c: fe442603 lw a2,-28(s0) +80000320: fe842683 lw a3,-24(s0) +80000324: fec42703 lw a4,-20(s0) +80000328: 00078513 mv a0,a5 +8000032c: cfdff0ef jal ra,80000028 +80000330: 00000073 ecall +80000334: 02c12083 lw ra,44(sp) +80000338: 02812403 lw s0,40(sp) +8000033c: 02412d03 lw s10,36(sp) +80000340: 03010113 addi sp,sp,48 +80000344: 00008067 ret -80000388 : -80000388: fb010113 addi sp,sp,-80 -8000038c: 04112623 sw ra,76(sp) -80000390: 04812423 sw s0,72(sp) -80000394: 05010413 addi s0,sp,80 -80000398: e5dff0ef jal ra,800001f4 -8000039c: fea42423 sw a0,-24(s0) -800003a0: 00010993 mv s3,sp -800003a4: 00100793 li a5,1 -800003a8: fef42623 sw a5,-20(s0) -800003ac: 08c0006f j 80000438 -800003b0: fec42703 lw a4,-20(s0) -800003b4: 000017b7 lui a5,0x1 -800003b8: 97478793 addi a5,a5,-1676 # 974 -800003bc: 02f70733 mul a4,a4,a5 -800003c0: 810007b7 lui a5,0x81000 -800003c4: 43478793 addi a5,a5,1076 # 81000434 -800003c8: 00f707b3 add a5,a4,a5 -800003cc: 00078513 mv a0,a5 -800003d0: 3f4000ef jal ra,800007c4 -800003d4: 00050793 mv a5,a0 -800003d8: 04079a63 bnez a5,8000042c -800003dc: fec42703 lw a4,-20(s0) -800003e0: 000017b7 lui a5,0x1 -800003e4: 97478793 addi a5,a5,-1676 # 974 -800003e8: 02f70733 mul a4,a4,a5 -800003ec: 810007b7 lui a5,0x81000 -800003f0: 43478793 addi a5,a5,1076 # 81000434 -800003f4: 00f707b3 add a5,a4,a5 -800003f8: fd040713 addi a4,s0,-48 -800003fc: 00070593 mv a1,a4 -80000400: 00078513 mv a0,a5 -80000404: 320000ef jal ra,80000724 -80000408: fd842783 lw a5,-40(s0) -8000040c: 00078113 mv sp,a5 -80000410: fd442783 lw a5,-44(s0) -80000414: fd042583 lw a1,-48(s0) -80000418: fdc42603 lw a2,-36(s0) -8000041c: fe042683 lw a3,-32(s0) -80000420: fe442703 lw a4,-28(s0) -80000424: 00078513 mv a0,a5 -80000428: c9dff0ef jal ra,800000c4 -8000042c: fec42783 lw a5,-20(s0) -80000430: 00178793 addi a5,a5,1 -80000434: fef42623 sw a5,-20(s0) -80000438: fec42783 lw a5,-20(s0) -8000043c: fe842703 lw a4,-24(s0) -80000440: f6e7e8e3 bltu a5,a4,800003b0 -80000444: 00098113 mv sp,s3 -80000448: c8dff0ef jal ra,800000d4 -8000044c: 00020793 mv a5,tp -80000450: 04078863 beqz a5,800004a0 -80000454: 810007b7 lui a5,0x81000 -80000458: 43478513 addi a0,a5,1076 # 81000434 -8000045c: 368000ef jal ra,800007c4 -80000460: 00050793 mv a5,a0 -80000464: 02079e63 bnez a5,800004a0 -80000468: fb840793 addi a5,s0,-72 -8000046c: 00078593 mv a1,a5 -80000470: 810007b7 lui a5,0x81000 -80000474: 43478513 addi a0,a5,1076 # 81000434 -80000478: 2ac000ef jal ra,80000724 -8000047c: fc042783 lw a5,-64(s0) -80000480: 00078113 mv sp,a5 -80000484: fbc42783 lw a5,-68(s0) -80000488: fb842583 lw a1,-72(s0) -8000048c: fc442603 lw a2,-60(s0) -80000490: fc842683 lw a3,-56(s0) -80000494: fcc42703 lw a4,-52(s0) -80000498: 00078513 mv a0,a5 -8000049c: b8dff0ef jal ra,80000028 -800004a0: 00000013 nop -800004a4: 04c12083 lw ra,76(sp) -800004a8: 04812403 lw s0,72(sp) -800004ac: 05010113 addi sp,sp,80 -800004b0: 00008067 ret +80000348 : +80000348: fb010113 addi sp,sp,-80 +8000034c: 04112623 sw ra,76(sp) +80000350: 04812423 sw s0,72(sp) +80000354: 05010413 addi s0,sp,80 +80000358: e9dff0ef jal ra,800001f4 +8000035c: fea42423 sw a0,-24(s0) +80000360: 00010993 mv s3,sp +80000364: 00100793 li a5,1 +80000368: fef42623 sw a5,-20(s0) +8000036c: 08c0006f j 800003f8 +80000370: fec42703 lw a4,-20(s0) +80000374: 000017b7 lui a5,0x1 +80000378: 97478793 addi a5,a5,-1676 # 974 +8000037c: 02f70733 mul a4,a4,a5 +80000380: 810007b7 lui a5,0x81000 +80000384: 42c78793 addi a5,a5,1068 # 8100042c +80000388: 00f707b3 add a5,a4,a5 +8000038c: 00078513 mv a0,a5 +80000390: 418000ef jal ra,800007a8 +80000394: 00050793 mv a5,a0 +80000398: 04079a63 bnez a5,800003ec +8000039c: fec42703 lw a4,-20(s0) +800003a0: 000017b7 lui a5,0x1 +800003a4: 97478793 addi a5,a5,-1676 # 974 +800003a8: 02f70733 mul a4,a4,a5 +800003ac: 810007b7 lui a5,0x81000 +800003b0: 42c78793 addi a5,a5,1068 # 8100042c +800003b4: 00f707b3 add a5,a4,a5 +800003b8: fd040713 addi a4,s0,-48 +800003bc: 00070593 mv a1,a4 +800003c0: 00078513 mv a0,a5 +800003c4: 344000ef jal ra,80000708 +800003c8: fd842783 lw a5,-40(s0) +800003cc: 00078113 mv sp,a5 +800003d0: fd442783 lw a5,-44(s0) +800003d4: fd042583 lw a1,-48(s0) +800003d8: fdc42603 lw a2,-36(s0) +800003dc: fe042683 lw a3,-32(s0) +800003e0: fe442703 lw a4,-28(s0) +800003e4: 00078513 mv a0,a5 +800003e8: cddff0ef jal ra,800000c4 +800003ec: fec42783 lw a5,-20(s0) +800003f0: 00178793 addi a5,a5,1 +800003f4: fef42623 sw a5,-20(s0) +800003f8: fec42783 lw a5,-20(s0) +800003fc: fe842703 lw a4,-24(s0) +80000400: f6e7e8e3 bltu a5,a4,80000370 +80000404: 00098113 mv sp,s3 +80000408: ccdff0ef jal ra,800000d4 +8000040c: 00020793 mv a5,tp +80000410: 04078863 beqz a5,80000460 +80000414: 810007b7 lui a5,0x81000 +80000418: 42c78513 addi a0,a5,1068 # 8100042c +8000041c: 38c000ef jal ra,800007a8 +80000420: 00050793 mv a5,a0 +80000424: 02079e63 bnez a5,80000460 +80000428: fb840793 addi a5,s0,-72 +8000042c: 00078593 mv a1,a5 +80000430: 810007b7 lui a5,0x81000 +80000434: 42c78513 addi a0,a5,1068 # 8100042c +80000438: 2d0000ef jal ra,80000708 +8000043c: fc042783 lw a5,-64(s0) +80000440: 00078113 mv sp,a5 +80000444: fbc42783 lw a5,-68(s0) +80000448: fb842583 lw a1,-72(s0) +8000044c: fc442603 lw a2,-60(s0) +80000450: fc842683 lw a3,-56(s0) +80000454: fcc42703 lw a4,-52(s0) +80000458: 00078513 mv a0,a5 +8000045c: bcdff0ef jal ra,80000028 +80000460: 00000013 nop +80000464: 04c12083 lw ra,76(sp) +80000468: 04812403 lw s0,72(sp) +8000046c: 05010113 addi sp,sp,80 +80000470: 00008067 ret -800004b4 : -800004b4: fb010113 addi sp,sp,-80 -800004b8: 04112623 sw ra,76(sp) -800004bc: 04812423 sw s0,72(sp) -800004c0: 05010413 addi s0,sp,80 -800004c4: faa42e23 sw a0,-68(s0) -800004c8: fab42c23 sw a1,-72(s0) -800004cc: fac42a23 sw a2,-76(s0) -800004d0: fad42823 sw a3,-80(s0) -800004d4: d31ff0ef jal ra,80000204 -800004d8: d1dff0ef jal ra,800001f4 -800004dc: fea42223 sw a0,-28(s0) -800004e0: 00010913 mv s2,sp -800004e4: fe042623 sw zero,-20(s0) -800004e8: fe042423 sw zero,-24(s0) -800004ec: 0900006f j 8000057c -800004f0: ffff09b7 lui s3,0xffff0 -800004f4: 01310133 add sp,sp,s3 -800004f8: fe842783 lw a5,-24(s0) -800004fc: fcf42623 sw a5,-52(s0) -80000500: fb842783 lw a5,-72(s0) -80000504: fcf42823 sw a5,-48(s0) -80000508: 00010793 mv a5,sp -8000050c: fcf42a23 sw a5,-44(s0) -80000510: fb442783 lw a5,-76(s0) -80000514: fcf42c23 sw a5,-40(s0) -80000518: fb042783 lw a5,-80(s0) -8000051c: fcf42e23 sw a5,-36(s0) +80000474 : +80000474: fb010113 addi sp,sp,-80 +80000478: 04112623 sw ra,76(sp) +8000047c: 04812423 sw s0,72(sp) +80000480: 05010413 addi s0,sp,80 +80000484: faa42e23 sw a0,-68(s0) +80000488: fab42c23 sw a1,-72(s0) +8000048c: fac42a23 sw a2,-76(s0) +80000490: fad42823 sw a3,-80(s0) +80000494: d71ff0ef jal ra,80000204 +80000498: d5dff0ef jal ra,800001f4 +8000049c: fea42223 sw a0,-28(s0) +800004a0: 00010913 mv s2,sp +800004a4: fe042623 sw zero,-20(s0) +800004a8: fe042423 sw zero,-24(s0) +800004ac: 0900006f j 8000053c +800004b0: ffff09b7 lui s3,0xffff0 +800004b4: 01310133 add sp,sp,s3 +800004b8: fe842783 lw a5,-24(s0) +800004bc: fcf42623 sw a5,-52(s0) +800004c0: fb842783 lw a5,-72(s0) +800004c4: fcf42823 sw a5,-48(s0) +800004c8: 00010793 mv a5,sp +800004cc: fcf42a23 sw a5,-44(s0) +800004d0: fb442783 lw a5,-76(s0) +800004d4: fcf42c23 sw a5,-40(s0) +800004d8: fb042783 lw a5,-80(s0) +800004dc: fcf42e23 sw a5,-36(s0) +800004e0: fec42783 lw a5,-20(s0) +800004e4: fef42023 sw a5,-32(s0) +800004e8: fec42703 lw a4,-20(s0) +800004ec: 000017b7 lui a5,0x1 +800004f0: 97478793 addi a5,a5,-1676 # 974 +800004f4: 02f70733 mul a4,a4,a5 +800004f8: 810007b7 lui a5,0x81000 +800004fc: 42c78793 addi a5,a5,1068 # 8100042c +80000500: 00f707b3 add a5,a4,a5 +80000504: fcc40713 addi a4,s0,-52 +80000508: 00070593 mv a1,a4 +8000050c: 00078513 mv a0,a5 +80000510: 190000ef jal ra,800006a0 +80000514: fec42783 lw a5,-20(s0) +80000518: 00178793 addi a5,a5,1 +8000051c: fef42623 sw a5,-20(s0) 80000520: fec42783 lw a5,-20(s0) -80000524: fef42023 sw a5,-32(s0) -80000528: fec42703 lw a4,-20(s0) -8000052c: 000017b7 lui a5,0x1 -80000530: 97478793 addi a5,a5,-1676 # 974 -80000534: 02f70733 mul a4,a4,a5 -80000538: 810007b7 lui a5,0x81000 -8000053c: 43478793 addi a5,a5,1076 # 81000434 -80000540: 00f707b3 add a5,a4,a5 -80000544: fcc40713 addi a4,s0,-52 -80000548: 00070593 mv a1,a4 -8000054c: 00078513 mv a0,a5 -80000550: 16c000ef jal ra,800006bc -80000554: fec42783 lw a5,-20(s0) -80000558: 00178793 addi a5,a5,1 -8000055c: fef42623 sw a5,-20(s0) -80000560: fec42783 lw a5,-20(s0) -80000564: fe442703 lw a4,-28(s0) -80000568: 00e7e463 bltu a5,a4,80000570 -8000056c: fe042623 sw zero,-20(s0) -80000570: fe842783 lw a5,-24(s0) -80000574: 00178793 addi a5,a5,1 -80000578: fef42423 sw a5,-24(s0) -8000057c: fe842703 lw a4,-24(s0) -80000580: fbc42783 lw a5,-68(s0) -80000584: f6f766e3 bltu a4,a5,800004f0 -80000588: 00090113 mv sp,s2 -8000058c: dfdff0ef jal ra,80000388 -80000590: 00000013 nop -80000594: 04c12083 lw ra,76(sp) -80000598: 04812403 lw s0,72(sp) -8000059c: 05010113 addi sp,sp,80 -800005a0: 00008067 ret +80000524: fe442703 lw a4,-28(s0) +80000528: 00e7e463 bltu a5,a4,80000530 +8000052c: fe042623 sw zero,-20(s0) +80000530: fe842783 lw a5,-24(s0) +80000534: 00178793 addi a5,a5,1 +80000538: fef42423 sw a5,-24(s0) +8000053c: fe842703 lw a4,-24(s0) +80000540: fbc42783 lw a5,-68(s0) +80000544: f6f766e3 bltu a4,a5,800004b0 +80000548: 00090113 mv sp,s2 +8000054c: dfdff0ef jal ra,80000348 +80000550: 00000013 nop +80000554: 04c12083 lw ra,76(sp) +80000558: 04812403 lw s0,72(sp) +8000055c: 05010113 addi sp,sp,80 +80000560: 00008067 ret -800005a4 : -800005a4: fd010113 addi sp,sp,-48 -800005a8: 02112623 sw ra,44(sp) -800005ac: 02812423 sw s0,40(sp) -800005b0: 03010413 addi s0,sp,48 -800005b4: fca42e23 sw a0,-36(s0) -800005b8: c3dff0ef jal ra,800001f4 -800005bc: fea42023 sw a0,-32(s0) -800005c0: fe042623 sw zero,-20(s0) -800005c4: 0540006f j 80000618 -800005c8: fe042623 sw zero,-20(s0) -800005cc: fe042423 sw zero,-24(s0) -800005d0: 03c0006f j 8000060c -800005d4: 810007b7 lui a5,0x81000 -800005d8: fe842703 lw a4,-24(s0) -800005dc: 00271713 slli a4,a4,0x2 -800005e0: 28c78793 addi a5,a5,652 # 8100028c -800005e4: 00f707b3 add a5,a4,a5 -800005e8: 0007a703 lw a4,0(a5) -800005ec: 00100793 li a5,1 -800005f0: 00f71863 bne a4,a5,80000600 -800005f4: fec42783 lw a5,-20(s0) -800005f8: 00178793 addi a5,a5,1 -800005fc: fef42623 sw a5,-20(s0) -80000600: fe842783 lw a5,-24(s0) -80000604: 00178793 addi a5,a5,1 -80000608: fef42423 sw a5,-24(s0) -8000060c: fe842783 lw a5,-24(s0) -80000610: fe042703 lw a4,-32(s0) -80000614: fce7e0e3 bltu a5,a4,800005d4 -80000618: fec42703 lw a4,-20(s0) -8000061c: fdc42783 lw a5,-36(s0) -80000620: faf714e3 bne a4,a5,800005c8 -80000624: fe042223 sw zero,-28(s0) -80000628: 0280006f j 80000650 -8000062c: 810007b7 lui a5,0x81000 -80000630: fe442703 lw a4,-28(s0) -80000634: 00271713 slli a4,a4,0x2 -80000638: 28c78793 addi a5,a5,652 # 8100028c -8000063c: 00f707b3 add a5,a4,a5 -80000640: 0007a023 sw zero,0(a5) -80000644: fe442783 lw a5,-28(s0) -80000648: 00178793 addi a5,a5,1 -8000064c: fef42223 sw a5,-28(s0) -80000650: fe442783 lw a5,-28(s0) -80000654: fe042703 lw a4,-32(s0) -80000658: fce7eae3 bltu a5,a4,8000062c -8000065c: 00000013 nop -80000660: 02c12083 lw ra,44(sp) -80000664: 02812403 lw s0,40(sp) -80000668: 03010113 addi sp,sp,48 -8000066c: 00008067 ret +80000564 : +80000564: fd010113 addi sp,sp,-48 +80000568: 02112623 sw ra,44(sp) +8000056c: 02812423 sw s0,40(sp) +80000570: 03010413 addi s0,sp,48 +80000574: fca42e23 sw a0,-36(s0) +80000578: fdc42583 lw a1,-36(s0) +8000057c: 810007b7 lui a5,0x81000 +80000580: 04078513 addi a0,a5,64 # 81000040 +80000584: 354000ef jal ra,800008d8 +80000588: c6dff0ef jal ra,800001f4 +8000058c: fea42023 sw a0,-32(s0) +80000590: fe042623 sw zero,-20(s0) +80000594: 0680006f j 800005fc +80000598: 00100793 li a5,1 +8000059c: fef42623 sw a5,-20(s0) +800005a0: fe042423 sw zero,-24(s0) +800005a4: 03c0006f j 800005e0 +800005a8: 810007b7 lui a5,0x81000 +800005ac: fe842703 lw a4,-24(s0) +800005b0: 00271713 slli a4,a4,0x2 +800005b4: 28478793 addi a5,a5,644 # 81000284 +800005b8: 00f707b3 add a5,a4,a5 +800005bc: 0007a703 lw a4,0(a5) +800005c0: 00100793 li a5,1 +800005c4: 00f71863 bne a4,a5,800005d4 +800005c8: fec42783 lw a5,-20(s0) +800005cc: 00178793 addi a5,a5,1 +800005d0: fef42623 sw a5,-20(s0) +800005d4: fe842783 lw a5,-24(s0) +800005d8: 00178793 addi a5,a5,1 +800005dc: fef42423 sw a5,-24(s0) +800005e0: fe842703 lw a4,-24(s0) +800005e4: 01f00793 li a5,31 +800005e8: fce7d0e3 bge a5,a4,800005a8 +800005ec: fec42583 lw a1,-20(s0) +800005f0: 810007b7 lui a5,0x81000 +800005f4: 04c78513 addi a0,a5,76 # 8100004c +800005f8: 2e0000ef jal ra,800008d8 +800005fc: fec42703 lw a4,-20(s0) +80000600: fdc42783 lw a5,-36(s0) +80000604: f8f71ae3 bne a4,a5,80000598 +80000608: fe042223 sw zero,-28(s0) +8000060c: 0280006f j 80000634 +80000610: 810007b7 lui a5,0x81000 +80000614: fe442703 lw a4,-28(s0) +80000618: 00271713 slli a4,a4,0x2 +8000061c: 28478793 addi a5,a5,644 # 81000284 +80000620: 00f707b3 add a5,a4,a5 +80000624: 0007a023 sw zero,0(a5) +80000628: fe442783 lw a5,-28(s0) +8000062c: 00178793 addi a5,a5,1 +80000630: fef42223 sw a5,-28(s0) +80000634: fe442783 lw a5,-28(s0) +80000638: fe042703 lw a4,-32(s0) +8000063c: fce7eae3 bltu a5,a4,80000610 +80000640: 00000013 nop +80000644: 02c12083 lw ra,44(sp) +80000648: 02812403 lw s0,40(sp) +8000064c: 03010113 addi sp,sp,48 +80000650: 00008067 ret -80000670 : -80000670: ff010113 addi sp,sp,-16 -80000674: 00812623 sw s0,12(sp) -80000678: 01712423 sw s7,8(sp) -8000067c: 01010413 addi s0,sp,16 -80000680: 000b8793 mv a5,s7 -80000684: 00078513 mv a0,a5 -80000688: 00c12403 lw s0,12(sp) -8000068c: 00812b83 lw s7,8(sp) -80000690: 01010113 addi sp,sp,16 -80000694: 00008067 ret +80000654 : +80000654: ff010113 addi sp,sp,-16 +80000658: 00812623 sw s0,12(sp) +8000065c: 01712423 sw s7,8(sp) +80000660: 01010413 addi s0,sp,16 +80000664: 000b8793 mv a5,s7 +80000668: 00078513 mv a0,a5 +8000066c: 00c12403 lw s0,12(sp) +80000670: 00812b83 lw s7,8(sp) +80000674: 01010113 addi sp,sp,16 +80000678: 00008067 ret -80000698 : -80000698: 00050293 mv t0,a0 -8000069c: 00000313 li t1,0 -800006a0: 00700393 li t2,7 -800006a4: 0062a023 sw t1,0(t0) -800006a8: 0062a223 sw t1,4(t0) +8000067c : +8000067c: 00050293 mv t0,a0 +80000680: 00000313 li t1,0 +80000684: 00700393 li t2,7 +80000688: 0062a023 sw t1,0(t0) +8000068c: 0062a223 sw t1,4(t0) +80000690: 0062a423 sw t1,8(t0) +80000694: 0072a623 sw t2,12(t0) +80000698: 0062a823 sw t1,16(t0) +8000069c: 00008067 ret + +800006a0 : +800006a0: 00050293 mv t0,a0 +800006a4: 0082a303 lw t1,8(t0) +800006a8: 00130313 addi t1,t1,1 800006ac: 0062a423 sw t1,8(t0) -800006b0: 0072a623 sw t2,12(t0) -800006b4: 0062a823 sw t1,16(t0) -800006b8: 00008067 ret +800006b0: 01428313 addi t1,t0,20 +800006b4: 0042ae83 lw t4,4(t0) +800006b8: 005e9393 slli t2,t4,0x5 +800006bc: 00730333 add t1,t1,t2 +800006c0: 0005ae03 lw t3,0(a1) +800006c4: 01c32023 sw t3,0(t1) +800006c8: 0045ae03 lw t3,4(a1) +800006cc: 01c32223 sw t3,4(t1) +800006d0: 0085ae03 lw t3,8(a1) +800006d4: 01c32423 sw t3,8(t1) +800006d8: 00c5ae03 lw t3,12(a1) +800006dc: 01c32623 sw t3,12(t1) +800006e0: 0105ae03 lw t3,16(a1) +800006e4: 01c32823 sw t3,16(t1) +800006e8: 0145ae03 lw t3,20(a1) +800006ec: 01c32a23 sw t3,20(t1) +800006f0: 001e8e93 addi t4,t4,1 +800006f4: 03200f13 li t5,50 +800006f8: 01ee9463 bne t4,t5,80000700 +800006fc: 00000e93 li t4,0 -800006bc : -800006bc: 00050293 mv t0,a0 -800006c0: 0082a303 lw t1,8(t0) -800006c4: 00130313 addi t1,t1,1 -800006c8: 0062a423 sw t1,8(t0) -800006cc: 01428313 addi t1,t0,20 -800006d0: 0042ae83 lw t4,4(t0) -800006d4: 005e9393 slli t2,t4,0x5 -800006d8: 00730333 add t1,t1,t2 -800006dc: 0005ae03 lw t3,0(a1) -800006e0: 01c32023 sw t3,0(t1) -800006e4: 0045ae03 lw t3,4(a1) -800006e8: 01c32223 sw t3,4(t1) -800006ec: 0085ae03 lw t3,8(a1) -800006f0: 01c32423 sw t3,8(t1) -800006f4: 00c5ae03 lw t3,12(a1) -800006f8: 01c32623 sw t3,12(t1) -800006fc: 0105ae03 lw t3,16(a1) -80000700: 01c32823 sw t3,16(t1) -80000704: 0145ae03 lw t3,20(a1) -80000708: 01c32a23 sw t3,20(t1) -8000070c: 001e8e93 addi t4,t4,1 -80000710: 03200f13 li t5,50 -80000714: 01ee9463 bne t4,t5,8000071c -80000718: 00000e93 li t4,0 +80000700 : +80000700: 01d2a223 sw t4,4(t0) +80000704: 00008067 ret -8000071c : -8000071c: 01d2a223 sw t4,4(t0) -80000720: 00008067 ret +80000708 : +80000708: 00050293 mv t0,a0 +8000070c: 0082a303 lw t1,8(t0) +80000710: 00000013 nop +80000714: 00000013 nop +80000718: 00000013 nop +8000071c: 00000013 nop +80000720: 00000013 nop +80000724: 00000013 nop +80000728: fff30313 addi t1,t1,-1 +8000072c: 0062a423 sw t1,8(t0) +80000730: 01428313 addi t1,t0,20 +80000734: 0002ae83 lw t4,0(t0) +80000738: 03200f93 li t6,50 +8000073c: 000e8f13 mv t5,t4 +80000740: 001f0f13 addi t5,t5,1 +80000744: 01ff1463 bne t5,t6,8000074c +80000748: 00000f13 li t5,0 -80000724 : -80000724: 00050293 mv t0,a0 -80000728: 0082a303 lw t1,8(t0) -8000072c: 00000013 nop -80000730: 00000013 nop -80000734: 00000013 nop -80000738: 00000013 nop -8000073c: 00000013 nop -80000740: 00000013 nop -80000744: fff30313 addi t1,t1,-1 -80000748: 0062a423 sw t1,8(t0) -8000074c: 01428313 addi t1,t0,20 -80000750: 0002ae83 lw t4,0(t0) -80000754: 03200f93 li t6,50 -80000758: 000e8f13 mv t5,t4 -8000075c: 001f0f13 addi t5,t5,1 -80000760: 01ff1463 bne t5,t6,80000768 -80000764: 00000f13 li t5,0 +8000074c : +8000074c: 01e2a023 sw t5,0(t0) +80000750: 005e9393 slli t2,t4,0x5 +80000754: 00730333 add t1,t1,t2 +80000758: 00032e03 lw t3,0(t1) +8000075c: 01c5a023 sw t3,0(a1) +80000760: 00432e03 lw t3,4(t1) +80000764: 01c5a223 sw t3,4(a1) +80000768: 00832e03 lw t3,8(t1) +8000076c: 01c5a423 sw t3,8(a1) +80000770: 00c32e03 lw t3,12(t1) +80000774: 01c5a623 sw t3,12(a1) +80000778: 01032e03 lw t3,16(t1) +8000077c: 01c5a823 sw t3,16(a1) +80000780: 01432e03 lw t3,20(t1) +80000784: 01c5aa23 sw t3,20(a1) +80000788: 00008067 ret -80000768 : -80000768: 01e2a023 sw t5,0(t0) -8000076c: 005e9393 slli t2,t4,0x5 -80000770: 00730333 add t1,t1,t2 -80000774: 00032e03 lw t3,0(t1) -80000778: 01c5a023 sw t3,0(a1) -8000077c: 00432e03 lw t3,4(t1) -80000780: 01c5a223 sw t3,4(a1) -80000784: 00832e03 lw t3,8(t1) -80000788: 01c5a423 sw t3,8(a1) -8000078c: 00c32e03 lw t3,12(t1) -80000790: 01c5a623 sw t3,12(a1) -80000794: 01032e03 lw t3,16(t1) -80000798: 01c5a823 sw t3,16(a1) -8000079c: 01432e03 lw t3,20(t1) -800007a0: 01c5aa23 sw t3,20(a1) +8000078c : +8000078c: 00050293 mv t0,a0 +80000790: 0082a303 lw t1,8(t0) +80000794: 00000513 li a0,0 +80000798: 03200e13 li t3,50 +8000079c: 006e1463 bne t3,t1,800007a4 +800007a0: 00150513 addi a0,a0,1 + +800007a4 : 800007a4: 00008067 ret -800007a8 : +800007a8 : 800007a8: 00050293 mv t0,a0 800007ac: 0082a303 lw t1,8(t0) 800007b0: 00000513 li a0,0 -800007b4: 03200e13 li t3,50 -800007b8: 006e1463 bne t3,t1,800007c0 +800007b4: 00000e13 li t3,0 +800007b8: 006e1463 bne t3,t1,800007c0 800007bc: 00150513 addi a0,a0,1 -800007c0 : +800007c0 : 800007c0: 00008067 ret -800007c4 : +800007c4 : 800007c4: 00050293 mv t0,a0 -800007c8: 0082a303 lw t1,8(t0) -800007cc: 00000513 li a0,0 -800007d0: 00000e13 li t3,0 -800007d4: 006e1463 bne t3,t1,800007dc -800007d8: 00150513 addi a0,a0,1 +800007c8: 00c2a303 lw t1,12(t0) +800007cc: 0102a383 lw t2,16(t0) +800007d0: 0063b533 sltu a0,t2,t1 +800007d4: 00008067 ret -800007dc : -800007dc: 00008067 ret +800007d8 : +800007d8: ff410113 addi sp,sp,-12 +800007dc: 00112023 sw ra,0(sp) +800007e0: 00b12223 sw a1,4(sp) -800007e0 : -800007e0: 00050293 mv t0,a0 -800007e4: 00c2a303 lw t1,12(t0) -800007e8: 0102a383 lw t2,16(t0) -800007ec: 0063b533 sltu a0,t2,t1 -800007f0: 00008067 ret +800007e4 : +800007e4: 00054583 lbu a1,0(a0) +800007e8: 00058863 beqz a1,800007f8 +800007ec: 01c000ef jal ra,80000808 +800007f0: 00150513 addi a0,a0,1 +800007f4: ff1ff06f j 800007e4 -800007f4 : -800007f4: ff410113 addi sp,sp,-12 -800007f8: 00112023 sw ra,0(sp) -800007fc: 00b12223 sw a1,4(sp) +800007f8 : +800007f8: 00012083 lw ra,0(sp) +800007fc: 00412583 lw a1,4(sp) +80000800: 00c10113 addi sp,sp,12 +80000804: 00008067 ret -80000800 : -80000800: 00054583 lbu a1,0(a0) -80000804: 00058863 beqz a1,80000814 -80000808: 01c000ef jal ra,80000824 -8000080c: 00150513 addi a0,a0,1 -80000810: ff1ff06f j 80000800 +80000808 : +80000808: 000108b7 lui a7,0x10 +8000080c: 00b8a023 sw a1,0(a7) # 10000 +80000810: 00008067 ret -80000814 : -80000814: 00012083 lw ra,0(sp) -80000818: 00412583 lw a1,4(sp) -8000081c: 00c10113 addi sp,sp,12 -80000820: 00008067 ret +80000814 : +80000814: fd010113 addi sp,sp,-48 +80000818: 02112623 sw ra,44(sp) +8000081c: 02812423 sw s0,40(sp) +80000820: 03010413 addi s0,sp,48 +80000824: fca42e23 sw a0,-36(s0) +80000828: fdc42703 lw a4,-36(s0) +8000082c: 00f00793 li a5,15 +80000830: 02e7e463 bltu a5,a4,80000858 +80000834: 810007b7 lui a5,0x81000 +80000838: fdc42703 lw a4,-36(s0) +8000083c: 00271713 slli a4,a4,0x2 +80000840: 1c478793 addi a5,a5,452 # 810001c4 +80000844: 00f707b3 add a5,a4,a5 +80000848: 0007a783 lw a5,0(a5) +8000084c: 00078513 mv a0,a5 +80000850: f89ff0ef jal ra,800007d8 +80000854: 0740006f j 800008c8 +80000858: 02000793 li a5,32 +8000085c: fef42623 sw a5,-20(s0) +80000860: fe0405a3 sb zero,-21(s0) +80000864: fec42783 lw a5,-20(s0) +80000868: ffc78793 addi a5,a5,-4 +8000086c: fdc42703 lw a4,-36(s0) +80000870: 00f757b3 srl a5,a4,a5 +80000874: 00f7f793 andi a5,a5,15 +80000878: fef42223 sw a5,-28(s0) +8000087c: fe442783 lw a5,-28(s0) +80000880: 00078663 beqz a5,8000088c +80000884: 00100793 li a5,1 +80000888: fef405a3 sb a5,-21(s0) +8000088c: feb44783 lbu a5,-21(s0) +80000890: 02078263 beqz a5,800008b4 +80000894: 810007b7 lui a5,0x81000 +80000898: fe442703 lw a4,-28(s0) +8000089c: 00271713 slli a4,a4,0x2 +800008a0: 1c478793 addi a5,a5,452 # 810001c4 +800008a4: 00f707b3 add a5,a4,a5 +800008a8: 0007a783 lw a5,0(a5) +800008ac: 00078513 mv a0,a5 +800008b0: f29ff0ef jal ra,800007d8 +800008b4: fec42783 lw a5,-20(s0) +800008b8: ffc78793 addi a5,a5,-4 +800008bc: fef42623 sw a5,-20(s0) +800008c0: fec42783 lw a5,-20(s0) +800008c4: faf040e3 bgtz a5,80000864 +800008c8: 02c12083 lw ra,44(sp) +800008cc: 02812403 lw s0,40(sp) +800008d0: 03010113 addi sp,sp,48 +800008d4: 00008067 ret -80000824 : -80000824: 000108b7 lui a7,0x10 -80000828: 00b8a023 sw a1,0(a7) # 10000 -8000082c: 00008067 ret +800008d8 : +800008d8: fe010113 addi sp,sp,-32 +800008dc: 00112e23 sw ra,28(sp) +800008e0: 00812c23 sw s0,24(sp) +800008e4: 02010413 addi s0,sp,32 +800008e8: fea42623 sw a0,-20(s0) +800008ec: feb42423 sw a1,-24(s0) +800008f0: fec42503 lw a0,-20(s0) +800008f4: ee5ff0ef jal ra,800007d8 +800008f8: fe842503 lw a0,-24(s0) +800008fc: f19ff0ef jal ra,80000814 +80000900: 810007b7 lui a5,0x81000 +80000904: 09478513 addi a0,a5,148 # 81000094 +80000908: ed1ff0ef jal ra,800007d8 +8000090c: 00000013 nop +80000910: 01c12083 lw ra,28(sp) +80000914: 01812403 lw s0,24(sp) +80000918: 02010113 addi sp,sp,32 +8000091c: 00008067 ret -80000830 : -80000830: fd010113 addi sp,sp,-48 -80000834: 02112623 sw ra,44(sp) -80000838: 02812423 sw s0,40(sp) -8000083c: 03010413 addi s0,sp,48 -80000840: fca42e23 sw a0,-36(s0) -80000844: fdc42703 lw a4,-36(s0) -80000848: 00f00793 li a5,15 -8000084c: 02e7e463 bltu a5,a4,80000874 -80000850: 810007b7 lui a5,0x81000 -80000854: fdc42703 lw a4,-36(s0) -80000858: 00271713 slli a4,a4,0x2 -8000085c: 1cc78793 addi a5,a5,460 # 810001cc -80000860: 00f707b3 add a5,a4,a5 -80000864: 0007a783 lw a5,0(a5) -80000868: 00078513 mv a0,a5 -8000086c: f89ff0ef jal ra,800007f4 -80000870: 0740006f j 800008e4 -80000874: 02000793 li a5,32 -80000878: fef42623 sw a5,-20(s0) -8000087c: fe0405a3 sb zero,-21(s0) -80000880: fec42783 lw a5,-20(s0) -80000884: ffc78793 addi a5,a5,-4 -80000888: fdc42703 lw a4,-36(s0) -8000088c: 00f757b3 srl a5,a4,a5 -80000890: 00f7f793 andi a5,a5,15 -80000894: fef42223 sw a5,-28(s0) -80000898: fe442783 lw a5,-28(s0) -8000089c: 00078663 beqz a5,800008a8 -800008a0: 00100793 li a5,1 -800008a4: fef405a3 sb a5,-21(s0) -800008a8: feb44783 lbu a5,-21(s0) -800008ac: 02078263 beqz a5,800008d0 -800008b0: 810007b7 lui a5,0x81000 -800008b4: fe442703 lw a4,-28(s0) -800008b8: 00271713 slli a4,a4,0x2 -800008bc: 1cc78793 addi a5,a5,460 # 810001cc -800008c0: 00f707b3 add a5,a4,a5 -800008c4: 0007a783 lw a5,0(a5) -800008c8: 00078513 mv a0,a5 -800008cc: f29ff0ef jal ra,800007f4 -800008d0: fec42783 lw a5,-20(s0) -800008d4: ffc78793 addi a5,a5,-4 -800008d8: fef42623 sw a5,-20(s0) -800008dc: fec42783 lw a5,-20(s0) -800008e0: faf040e3 bgtz a5,80000880 -800008e4: 02c12083 lw ra,44(sp) -800008e8: 02812403 lw s0,40(sp) -800008ec: 03010113 addi sp,sp,48 -800008f0: 00008067 ret - -800008f4 : -800008f4: fe010113 addi sp,sp,-32 -800008f8: 00112e23 sw ra,28(sp) -800008fc: 00812c23 sw s0,24(sp) -80000900: 02010413 addi s0,sp,32 -80000904: fea42623 sw a0,-20(s0) -80000908: feb42423 sw a1,-24(s0) -8000090c: fec42503 lw a0,-20(s0) -80000910: ee5ff0ef jal ra,800007f4 -80000914: fe842503 lw a0,-24(s0) -80000918: f19ff0ef jal ra,80000830 -8000091c: 810007b7 lui a5,0x81000 -80000920: 09078513 addi a0,a5,144 # 81000090 -80000924: ed1ff0ef jal ra,800007f4 -80000928: 00000013 nop -8000092c: 01c12083 lw ra,28(sp) -80000930: 01812403 lw s0,24(sp) -80000934: 02010113 addi sp,sp,32 -80000938: 00008067 ret - -8000093c : -8000093c: fd010113 addi sp,sp,-48 -80000940: 02112623 sw ra,44(sp) -80000944: 02812423 sw s0,40(sp) -80000948: 03010413 addi s0,sp,48 -8000094c: fca42e23 sw a0,-36(s0) -80000950: fcb42c23 sw a1,-40(s0) -80000954: fcc42a23 sw a2,-44(s0) -80000958: fcd42823 sw a3,-48(s0) +80000920 : +80000920: fd010113 addi sp,sp,-48 +80000924: 02112623 sw ra,44(sp) +80000928: 02812423 sw s0,40(sp) +8000092c: 03010413 addi s0,sp,48 +80000930: fca42e23 sw a0,-36(s0) +80000934: fcb42c23 sw a1,-40(s0) +80000938: fcc42a23 sw a2,-44(s0) +8000093c: fcd42823 sw a3,-48(s0) +80000940: 810267b7 lui a5,0x81026 +80000944: fdc42703 lw a4,-36(s0) +80000948: 1ce7aa23 sw a4,468(a5) # 810261d4 +8000094c: 810267b7 lui a5,0x81026 +80000950: 1d478793 addi a5,a5,468 # 810261d4 +80000954: fd842703 lw a4,-40(s0) +80000958: 00e7a223 sw a4,4(a5) 8000095c: 810267b7 lui a5,0x81026 -80000960: fdc42703 lw a4,-36(s0) -80000964: 1ce7ae23 sw a4,476(a5) # 810261dc -80000968: 810267b7 lui a5,0x81026 -8000096c: 1dc78793 addi a5,a5,476 # 810261dc -80000970: fd842703 lw a4,-40(s0) -80000974: 00e7a223 sw a4,4(a5) -80000978: 810267b7 lui a5,0x81026 -8000097c: 1dc78793 addi a5,a5,476 # 810261dc -80000980: fd442703 lw a4,-44(s0) -80000984: 00e7a423 sw a4,8(a5) -80000988: 810267b7 lui a5,0x81026 -8000098c: 1dc78793 addi a5,a5,476 # 810261dc -80000990: fd042703 lw a4,-48(s0) -80000994: 00e7a623 sw a4,12(a5) -80000998: 865ff0ef jal ra,800001fc -8000099c: fea42423 sw a0,-24(s0) -800009a0: fd042703 lw a4,-48(s0) -800009a4: fe842783 lw a5,-24(s0) -800009a8: 02f757b3 divu a5,a4,a5 +80000960: 1d478793 addi a5,a5,468 # 810261d4 +80000964: fd442703 lw a4,-44(s0) +80000968: 00e7a423 sw a4,8(a5) +8000096c: 810267b7 lui a5,0x81026 +80000970: 1d478793 addi a5,a5,468 # 810261d4 +80000974: fd042703 lw a4,-48(s0) +80000978: 00e7a623 sw a4,12(a5) +8000097c: 881ff0ef jal ra,800001fc +80000980: fea42423 sw a0,-24(s0) +80000984: fd042703 lw a4,-48(s0) +80000988: fe842783 lw a5,-24(s0) +8000098c: 02f757b3 divu a5,a4,a5 +80000990: fef42623 sw a5,-20(s0) +80000994: fd042703 lw a4,-48(s0) +80000998: fe842783 lw a5,-24(s0) +8000099c: 02f777b3 remu a5,a4,a5 +800009a0: 00078863 beqz a5,800009b0 +800009a4: fec42783 lw a5,-20(s0) +800009a8: 00178793 addi a5,a5,1 800009ac: fef42623 sw a5,-20(s0) -800009b0: fd042703 lw a4,-48(s0) -800009b4: fe842783 lw a5,-24(s0) -800009b8: 02f777b3 remu a5,a4,a5 -800009bc: 00078863 beqz a5,800009cc -800009c0: fec42783 lw a5,-20(s0) -800009c4: 00178793 addi a5,a5,1 -800009c8: fef42623 sw a5,-20(s0) -800009cc: fec42583 lw a1,-20(s0) -800009d0: 810007b7 lui a5,0x81000 -800009d4: 0d478513 addi a0,a5,212 # 810000d4 -800009d8: f1dff0ef jal ra,800008f4 -800009dc: 810267b7 lui a5,0x81026 -800009e0: 1dc78793 addi a5,a5,476 # 810261dc -800009e4: fec42703 lw a4,-20(s0) -800009e8: 00e7a823 sw a4,16(a5) -800009ec: fd042703 lw a4,-48(s0) -800009f0: fe842783 lw a5,-24(s0) -800009f4: 02f76263 bltu a4,a5,80000a18 -800009f8: 810267b7 lui a5,0x81026 -800009fc: 1dc78693 addi a3,a5,476 # 810261dc -80000a00: 800017b7 lui a5,0x80001 -80000a04: a7078613 addi a2,a5,-1424 # 80000a70 -80000a08: fe842583 lw a1,-24(s0) -80000a0c: fd042503 lw a0,-48(s0) -80000a10: aa5ff0ef jal ra,800004b4 -80000a14: 0200006f j 80000a34 -80000a18: 810267b7 lui a5,0x81026 -80000a1c: 1dc78693 addi a3,a5,476 # 810261dc -80000a20: 800017b7 lui a5,0x80001 -80000a24: a7078613 addi a2,a5,-1424 # 80000a70 -80000a28: fd042583 lw a1,-48(s0) -80000a2c: fd042503 lw a0,-48(s0) -80000a30: a85ff0ef jal ra,800004b4 -80000a34: fc0ff0ef jal ra,800001f4 -80000a38: fea42223 sw a0,-28(s0) -80000a3c: fd042703 lw a4,-48(s0) -80000a40: fe442783 lw a5,-28(s0) -80000a44: 00e7f863 bgeu a5,a4,80000a54 -80000a48: fe442503 lw a0,-28(s0) -80000a4c: b59ff0ef jal ra,800005a4 -80000a50: 00c0006f j 80000a5c -80000a54: fd042503 lw a0,-48(s0) -80000a58: b4dff0ef jal ra,800005a4 -80000a5c: 00000013 nop -80000a60: 02c12083 lw ra,44(sp) -80000a64: 02812403 lw s0,40(sp) -80000a68: 03010113 addi sp,sp,48 -80000a6c: 00008067 ret +800009b0: 810267b7 lui a5,0x81026 +800009b4: 1d478793 addi a5,a5,468 # 810261d4 +800009b8: fec42703 lw a4,-20(s0) +800009bc: 00e7a823 sw a4,16(a5) +800009c0: fd042703 lw a4,-48(s0) +800009c4: fe842783 lw a5,-24(s0) +800009c8: 02f76263 bltu a4,a5,800009ec +800009cc: 810267b7 lui a5,0x81026 +800009d0: 1d478693 addi a3,a5,468 # 810261d4 +800009d4: 800017b7 lui a5,0x80001 +800009d8: a4478613 addi a2,a5,-1468 # 80000a44 +800009dc: fe842583 lw a1,-24(s0) +800009e0: fd042503 lw a0,-48(s0) +800009e4: a91ff0ef jal ra,80000474 +800009e8: 0200006f j 80000a08 +800009ec: 810267b7 lui a5,0x81026 +800009f0: 1d478693 addi a3,a5,468 # 810261d4 +800009f4: 800017b7 lui a5,0x80001 +800009f8: a4478613 addi a2,a5,-1468 # 80000a44 +800009fc: fd042583 lw a1,-48(s0) +80000a00: fd042503 lw a0,-48(s0) +80000a04: a71ff0ef jal ra,80000474 +80000a08: fecff0ef jal ra,800001f4 +80000a0c: fea42223 sw a0,-28(s0) +80000a10: fd042703 lw a4,-48(s0) +80000a14: fe442783 lw a5,-28(s0) +80000a18: 00e7f863 bgeu a5,a4,80000a28 +80000a1c: fe442503 lw a0,-28(s0) +80000a20: b45ff0ef jal ra,80000564 +80000a24: 00c0006f j 80000a30 +80000a28: fd042503 lw a0,-48(s0) +80000a2c: b39ff0ef jal ra,80000564 +80000a30: 00000013 nop +80000a34: 02c12083 lw ra,44(sp) +80000a38: 02812403 lw s0,40(sp) +80000a3c: 03010113 addi sp,sp,48 +80000a40: 00008067 ret -80000a70 <_vx_mat_mult>: -80000a70: fa010113 addi sp,sp,-96 -80000a74: 04112e23 sw ra,92(sp) -80000a78: 04812c23 sw s0,88(sp) -80000a7c: 06010413 addi s0,sp,96 -80000a80: faa42623 sw a0,-84(s0) -80000a84: fab42423 sw a1,-88(s0) -80000a88: be9ff0ef jal ra,80000670 -80000a8c: fca42c23 sw a0,-40(s0) -80000a90: fd842783 lw a5,-40(s0) -80000a94: 0007a783 lw a5,0(a5) -80000a98: fcf42a23 sw a5,-44(s0) -80000a9c: fd842783 lw a5,-40(s0) -80000aa0: 0047a783 lw a5,4(a5) -80000aa4: fcf42823 sw a5,-48(s0) -80000aa8: fd842783 lw a5,-40(s0) -80000aac: 0087a783 lw a5,8(a5) -80000ab0: fcf42623 sw a5,-52(s0) -80000ab4: fd842783 lw a5,-40(s0) -80000ab8: 0107a783 lw a5,16(a5) -80000abc: fef42623 sw a5,-20(s0) -80000ac0: fec42703 lw a4,-20(s0) -80000ac4: fac42783 lw a5,-84(s0) -80000ac8: 02f707b3 mul a5,a4,a5 -80000acc: fef42423 sw a5,-24(s0) -80000ad0: fec42783 lw a5,-20(s0) -80000ad4: 00079a63 bnez a5,80000ae8 <_vx_mat_mult+0x78> -80000ad8: 00100793 li a5,1 -80000adc: fef42623 sw a5,-20(s0) -80000ae0: fac42783 lw a5,-84(s0) -80000ae4: fef42423 sw a5,-24(s0) -80000ae8: fd842783 lw a5,-40(s0) -80000aec: 00c7a783 lw a5,12(a5) -80000af0: fcf42423 sw a5,-56(s0) -80000af4: fe042223 sw zero,-28(s0) -80000af8: 0d80006f j 80000bd0 <_vx_mat_mult+0x160> -80000afc: fe042023 sw zero,-32(s0) -80000b00: fc042e23 sw zero,-36(s0) -80000b04: 0780006f j 80000b7c <_vx_mat_mult+0x10c> -80000b08: fa842703 lw a4,-88(s0) -80000b0c: fc842783 lw a5,-56(s0) -80000b10: 02f707b3 mul a5,a4,a5 -80000b14: fdc42703 lw a4,-36(s0) +80000a44 <_vx_mat_mult>: +80000a44: fa010113 addi sp,sp,-96 +80000a48: 04112e23 sw ra,92(sp) +80000a4c: 04812c23 sw s0,88(sp) +80000a50: 06010413 addi s0,sp,96 +80000a54: faa42623 sw a0,-84(s0) +80000a58: fab42423 sw a1,-88(s0) +80000a5c: bf9ff0ef jal ra,80000654 +80000a60: fca42c23 sw a0,-40(s0) +80000a64: fd842783 lw a5,-40(s0) +80000a68: 0007a783 lw a5,0(a5) +80000a6c: fcf42a23 sw a5,-44(s0) +80000a70: fd842783 lw a5,-40(s0) +80000a74: 0047a783 lw a5,4(a5) +80000a78: fcf42823 sw a5,-48(s0) +80000a7c: fd842783 lw a5,-40(s0) +80000a80: 0087a783 lw a5,8(a5) +80000a84: fcf42623 sw a5,-52(s0) +80000a88: fd842783 lw a5,-40(s0) +80000a8c: 0107a783 lw a5,16(a5) +80000a90: fef42623 sw a5,-20(s0) +80000a94: fec42703 lw a4,-20(s0) +80000a98: fac42783 lw a5,-84(s0) +80000a9c: 02f707b3 mul a5,a4,a5 +80000aa0: fef42423 sw a5,-24(s0) +80000aa4: fec42783 lw a5,-20(s0) +80000aa8: 00079a63 bnez a5,80000abc <_vx_mat_mult+0x78> +80000aac: 00100793 li a5,1 +80000ab0: fef42623 sw a5,-20(s0) +80000ab4: fac42783 lw a5,-84(s0) +80000ab8: fef42423 sw a5,-24(s0) +80000abc: fd842783 lw a5,-40(s0) +80000ac0: 00c7a783 lw a5,12(a5) +80000ac4: fcf42423 sw a5,-56(s0) +80000ac8: fe042223 sw zero,-28(s0) +80000acc: 0d80006f j 80000ba4 <_vx_mat_mult+0x160> +80000ad0: fe042023 sw zero,-32(s0) +80000ad4: fc042e23 sw zero,-36(s0) +80000ad8: 0780006f j 80000b50 <_vx_mat_mult+0x10c> +80000adc: fa842703 lw a4,-88(s0) +80000ae0: fc842783 lw a5,-56(s0) +80000ae4: 02f707b3 mul a5,a4,a5 +80000ae8: fdc42703 lw a4,-36(s0) +80000aec: 00f707b3 add a5,a4,a5 +80000af0: fcf42223 sw a5,-60(s0) +80000af4: fc842703 lw a4,-56(s0) +80000af8: fdc42783 lw a5,-36(s0) +80000afc: 02f707b3 mul a5,a4,a5 +80000b00: fe842703 lw a4,-24(s0) +80000b04: 00f707b3 add a5,a4,a5 +80000b08: fcf42023 sw a5,-64(s0) +80000b0c: fc442783 lw a5,-60(s0) +80000b10: 00279793 slli a5,a5,0x2 +80000b14: fd442703 lw a4,-44(s0) 80000b18: 00f707b3 add a5,a4,a5 -80000b1c: fcf42223 sw a5,-60(s0) -80000b20: fc842703 lw a4,-56(s0) -80000b24: fdc42783 lw a5,-36(s0) -80000b28: 02f707b3 mul a5,a4,a5 -80000b2c: fe842703 lw a4,-24(s0) -80000b30: 00f707b3 add a5,a4,a5 -80000b34: fcf42023 sw a5,-64(s0) -80000b38: fc442783 lw a5,-60(s0) -80000b3c: 00279793 slli a5,a5,0x2 -80000b40: fd442703 lw a4,-44(s0) -80000b44: 00f707b3 add a5,a4,a5 -80000b48: 0007a703 lw a4,0(a5) -80000b4c: fc042783 lw a5,-64(s0) -80000b50: 00279793 slli a5,a5,0x2 -80000b54: fd042683 lw a3,-48(s0) -80000b58: 00f687b3 add a5,a3,a5 -80000b5c: 0007a783 lw a5,0(a5) -80000b60: 02f707b3 mul a5,a4,a5 -80000b64: fe042703 lw a4,-32(s0) -80000b68: 00f707b3 add a5,a4,a5 -80000b6c: fef42023 sw a5,-32(s0) -80000b70: fdc42783 lw a5,-36(s0) -80000b74: 00178793 addi a5,a5,1 -80000b78: fcf42e23 sw a5,-36(s0) -80000b7c: fdc42703 lw a4,-36(s0) -80000b80: fc842783 lw a5,-56(s0) -80000b84: f8f762e3 bltu a4,a5,80000b08 <_vx_mat_mult+0x98> -80000b88: fa842703 lw a4,-88(s0) -80000b8c: fc842783 lw a5,-56(s0) -80000b90: 02f70733 mul a4,a4,a5 -80000b94: fe842783 lw a5,-24(s0) -80000b98: 00f707b3 add a5,a4,a5 -80000b9c: faf42e23 sw a5,-68(s0) -80000ba0: fbc42783 lw a5,-68(s0) -80000ba4: 00279793 slli a5,a5,0x2 -80000ba8: fcc42703 lw a4,-52(s0) -80000bac: 00f707b3 add a5,a4,a5 -80000bb0: fe042703 lw a4,-32(s0) -80000bb4: 00e7a023 sw a4,0(a5) -80000bb8: fe842783 lw a5,-24(s0) -80000bbc: 00178793 addi a5,a5,1 -80000bc0: fef42423 sw a5,-24(s0) -80000bc4: fe442783 lw a5,-28(s0) -80000bc8: 00178793 addi a5,a5,1 -80000bcc: fef42223 sw a5,-28(s0) -80000bd0: fe442783 lw a5,-28(s0) -80000bd4: fec42703 lw a4,-20(s0) -80000bd8: f2e7e2e3 bltu a5,a4,80000afc <_vx_mat_mult+0x8c> -80000bdc: 00000013 nop -80000be0: 05c12083 lw ra,92(sp) -80000be4: 05812403 lw s0,88(sp) -80000be8: 06010113 addi sp,sp,96 -80000bec: 00008067 ret +80000b1c: 0007a703 lw a4,0(a5) +80000b20: fc042783 lw a5,-64(s0) +80000b24: 00279793 slli a5,a5,0x2 +80000b28: fd042683 lw a3,-48(s0) +80000b2c: 00f687b3 add a5,a3,a5 +80000b30: 0007a783 lw a5,0(a5) +80000b34: 02f707b3 mul a5,a4,a5 +80000b38: fe042703 lw a4,-32(s0) +80000b3c: 00f707b3 add a5,a4,a5 +80000b40: fef42023 sw a5,-32(s0) +80000b44: fdc42783 lw a5,-36(s0) +80000b48: 00178793 addi a5,a5,1 +80000b4c: fcf42e23 sw a5,-36(s0) +80000b50: fdc42703 lw a4,-36(s0) +80000b54: fc842783 lw a5,-56(s0) +80000b58: f8f762e3 bltu a4,a5,80000adc <_vx_mat_mult+0x98> +80000b5c: fa842703 lw a4,-88(s0) +80000b60: fc842783 lw a5,-56(s0) +80000b64: 02f70733 mul a4,a4,a5 +80000b68: fe842783 lw a5,-24(s0) +80000b6c: 00f707b3 add a5,a4,a5 +80000b70: faf42e23 sw a5,-68(s0) +80000b74: fbc42783 lw a5,-68(s0) +80000b78: 00279793 slli a5,a5,0x2 +80000b7c: fcc42703 lw a4,-52(s0) +80000b80: 00f707b3 add a5,a4,a5 +80000b84: fe042703 lw a4,-32(s0) +80000b88: 00e7a023 sw a4,0(a5) +80000b8c: fe842783 lw a5,-24(s0) +80000b90: 00178793 addi a5,a5,1 +80000b94: fef42423 sw a5,-24(s0) +80000b98: fe442783 lw a5,-28(s0) +80000b9c: 00178793 addi a5,a5,1 +80000ba0: fef42223 sw a5,-28(s0) +80000ba4: fe442783 lw a5,-28(s0) +80000ba8: fec42703 lw a4,-20(s0) +80000bac: f2e7e2e3 bltu a5,a4,80000ad0 <_vx_mat_mult+0x8c> +80000bb0: 00000013 nop +80000bb4: 05c12083 lw ra,92(sp) +80000bb8: 05812403 lw s0,88(sp) +80000bbc: 06010113 addi sp,sp,96 +80000bc0: 00008067 ret -80000bf0 : -80000bf0: fc010113 addi sp,sp,-64 -80000bf4: 02112e23 sw ra,60(sp) -80000bf8: 02812c23 sw s0,56(sp) -80000bfc: 04010413 addi s0,sp,64 -80000c00: fca42e23 sw a0,-36(s0) -80000c04: fcb42c23 sw a1,-40(s0) -80000c08: fcc42a23 sw a2,-44(s0) -80000c0c: fcd42823 sw a3,-48(s0) -80000c10: fce42623 sw a4,-52(s0) +80000bc4 : +80000bc4: fc010113 addi sp,sp,-64 +80000bc8: 02112e23 sw ra,60(sp) +80000bcc: 02812c23 sw s0,56(sp) +80000bd0: 04010413 addi s0,sp,64 +80000bd4: fca42e23 sw a0,-36(s0) +80000bd8: fcb42c23 sw a1,-40(s0) +80000bdc: fcc42a23 sw a2,-44(s0) +80000be0: fcd42823 sw a3,-48(s0) +80000be4: fce42623 sw a4,-52(s0) +80000be8: 810267b7 lui a5,0x81026 +80000bec: fdc42703 lw a4,-36(s0) +80000bf0: 1ee7a423 sw a4,488(a5) # 810261e8 +80000bf4: 810267b7 lui a5,0x81026 +80000bf8: 1e878793 addi a5,a5,488 # 810261e8 +80000bfc: fd842703 lw a4,-40(s0) +80000c00: 00e7a223 sw a4,4(a5) +80000c04: 810267b7 lui a5,0x81026 +80000c08: 1e878793 addi a5,a5,488 # 810261e8 +80000c0c: fd442703 lw a4,-44(s0) +80000c10: 00e7a423 sw a4,8(a5) 80000c14: 810267b7 lui a5,0x81026 -80000c18: fdc42703 lw a4,-36(s0) -80000c1c: 1ee7a823 sw a4,496(a5) # 810261f0 -80000c20: 810267b7 lui a5,0x81026 -80000c24: 1f078793 addi a5,a5,496 # 810261f0 -80000c28: fd842703 lw a4,-40(s0) -80000c2c: 00e7a223 sw a4,4(a5) -80000c30: 810267b7 lui a5,0x81026 -80000c34: 1f078793 addi a5,a5,496 # 810261f0 -80000c38: fd442703 lw a4,-44(s0) -80000c3c: 00e7a423 sw a4,8(a5) -80000c40: 810267b7 lui a5,0x81026 -80000c44: 1f078793 addi a5,a5,496 # 810261f0 -80000c48: fcc42703 lw a4,-52(s0) -80000c4c: 00e7a623 sw a4,12(a5) -80000c50: 810267b7 lui a5,0x81026 -80000c54: 1f078793 addi a5,a5,496 # 810261f0 -80000c58: fd042703 lw a4,-48(s0) -80000c5c: 00e7a823 sw a4,16(a5) -80000c60: d9cff0ef jal ra,800001fc -80000c64: fea42423 sw a0,-24(s0) -80000c68: fcc42703 lw a4,-52(s0) -80000c6c: fe842783 lw a5,-24(s0) -80000c70: 02f757b3 divu a5,a4,a5 -80000c74: fef42623 sw a5,-20(s0) +80000c18: 1e878793 addi a5,a5,488 # 810261e8 +80000c1c: fcc42703 lw a4,-52(s0) +80000c20: 00e7a623 sw a4,12(a5) +80000c24: 810267b7 lui a5,0x81026 +80000c28: 1e878793 addi a5,a5,488 # 810261e8 +80000c2c: fd042703 lw a4,-48(s0) +80000c30: 00e7a823 sw a4,16(a5) +80000c34: dc8ff0ef jal ra,800001fc +80000c38: fea42423 sw a0,-24(s0) +80000c3c: fcc42703 lw a4,-52(s0) +80000c40: fe842783 lw a5,-24(s0) +80000c44: 02f757b3 divu a5,a4,a5 +80000c48: fef42623 sw a5,-20(s0) +80000c4c: fcc42703 lw a4,-52(s0) +80000c50: fe842783 lw a5,-24(s0) +80000c54: 02f777b3 remu a5,a4,a5 +80000c58: 00078863 beqz a5,80000c68 +80000c5c: fec42783 lw a5,-20(s0) +80000c60: 00178793 addi a5,a5,1 +80000c64: fef42623 sw a5,-20(s0) +80000c68: 810267b7 lui a5,0x81026 +80000c6c: 1e878793 addi a5,a5,488 # 810261e8 +80000c70: fec42703 lw a4,-20(s0) +80000c74: 00e7aa23 sw a4,20(a5) 80000c78: fcc42703 lw a4,-52(s0) 80000c7c: fe842783 lw a5,-24(s0) -80000c80: 02f777b3 remu a5,a4,a5 -80000c84: 00078863 beqz a5,80000c94 -80000c88: fec42783 lw a5,-20(s0) -80000c8c: 00178793 addi a5,a5,1 -80000c90: fef42623 sw a5,-20(s0) -80000c94: 810267b7 lui a5,0x81026 -80000c98: 1f078793 addi a5,a5,496 # 810261f0 -80000c9c: fec42703 lw a4,-20(s0) -80000ca0: 00e7aa23 sw a4,20(a5) -80000ca4: fcc42703 lw a4,-52(s0) -80000ca8: fe842783 lw a5,-24(s0) -80000cac: 02f76263 bltu a4,a5,80000cd0 -80000cb0: 810267b7 lui a5,0x81026 -80000cb4: 1f078693 addi a3,a5,496 # 810261f0 -80000cb8: 800017b7 lui a5,0x80001 -80000cbc: d2878613 addi a2,a5,-728 # 80000d28 -80000cc0: fe842583 lw a1,-24(s0) -80000cc4: fd042503 lw a0,-48(s0) -80000cc8: fecff0ef jal ra,800004b4 -80000ccc: 0200006f j 80000cec -80000cd0: 810267b7 lui a5,0x81026 -80000cd4: 1f078693 addi a3,a5,496 # 810261f0 -80000cd8: 800017b7 lui a5,0x80001 -80000cdc: d2878613 addi a2,a5,-728 # 80000d28 -80000ce0: fcc42583 lw a1,-52(s0) -80000ce4: fd042503 lw a0,-48(s0) -80000ce8: fccff0ef jal ra,800004b4 -80000cec: d08ff0ef jal ra,800001f4 -80000cf0: fea42223 sw a0,-28(s0) -80000cf4: fd042703 lw a4,-48(s0) -80000cf8: fe442783 lw a5,-28(s0) -80000cfc: 00e7f863 bgeu a5,a4,80000d0c -80000d00: fe442503 lw a0,-28(s0) -80000d04: 8a1ff0ef jal ra,800005a4 -80000d08: 00c0006f j 80000d14 -80000d0c: fd042503 lw a0,-48(s0) -80000d10: 895ff0ef jal ra,800005a4 -80000d14: 00000013 nop -80000d18: 03c12083 lw ra,60(sp) -80000d1c: 03812403 lw s0,56(sp) -80000d20: 04010113 addi sp,sp,64 -80000d24: 00008067 ret +80000c80: 02f76263 bltu a4,a5,80000ca4 +80000c84: 810267b7 lui a5,0x81026 +80000c88: 1e878693 addi a3,a5,488 # 810261e8 +80000c8c: 800017b7 lui a5,0x80001 +80000c90: cfc78613 addi a2,a5,-772 # 80000cfc +80000c94: fe842583 lw a1,-24(s0) +80000c98: fd042503 lw a0,-48(s0) +80000c9c: fd8ff0ef jal ra,80000474 +80000ca0: 0200006f j 80000cc0 +80000ca4: 810267b7 lui a5,0x81026 +80000ca8: 1e878693 addi a3,a5,488 # 810261e8 +80000cac: 800017b7 lui a5,0x80001 +80000cb0: cfc78613 addi a2,a5,-772 # 80000cfc +80000cb4: fcc42583 lw a1,-52(s0) +80000cb8: fd042503 lw a0,-48(s0) +80000cbc: fb8ff0ef jal ra,80000474 +80000cc0: d34ff0ef jal ra,800001f4 +80000cc4: fea42223 sw a0,-28(s0) +80000cc8: fd042703 lw a4,-48(s0) +80000ccc: fe442783 lw a5,-28(s0) +80000cd0: 00e7f863 bgeu a5,a4,80000ce0 +80000cd4: fe442503 lw a0,-28(s0) +80000cd8: 88dff0ef jal ra,80000564 +80000cdc: 00c0006f j 80000ce8 +80000ce0: fd042503 lw a0,-48(s0) +80000ce4: 881ff0ef jal ra,80000564 +80000ce8: 00000013 nop +80000cec: 03c12083 lw ra,60(sp) +80000cf0: 03812403 lw s0,56(sp) +80000cf4: 04010113 addi sp,sp,64 +80000cf8: 00008067 ret -80000d28 <_vx_mat_add>: -80000d28: fb010113 addi sp,sp,-80 -80000d2c: 04112623 sw ra,76(sp) -80000d30: 04812423 sw s0,72(sp) -80000d34: 05010413 addi s0,sp,80 -80000d38: faa42e23 sw a0,-68(s0) -80000d3c: fab42c23 sw a1,-72(s0) -80000d40: 931ff0ef jal ra,80000670 -80000d44: fea42023 sw a0,-32(s0) -80000d48: fe042783 lw a5,-32(s0) -80000d4c: 0007a783 lw a5,0(a5) -80000d50: fcf42e23 sw a5,-36(s0) -80000d54: fe042783 lw a5,-32(s0) -80000d58: 0047a783 lw a5,4(a5) -80000d5c: fcf42c23 sw a5,-40(s0) -80000d60: fe042783 lw a5,-32(s0) -80000d64: 0087a783 lw a5,8(a5) -80000d68: fcf42a23 sw a5,-44(s0) -80000d6c: fe042783 lw a5,-32(s0) -80000d70: 0147a783 lw a5,20(a5) -80000d74: fef42623 sw a5,-20(s0) -80000d78: fec42703 lw a4,-20(s0) -80000d7c: fbc42783 lw a5,-68(s0) -80000d80: 02f707b3 mul a5,a4,a5 -80000d84: fef42423 sw a5,-24(s0) -80000d88: fec42783 lw a5,-20(s0) -80000d8c: 00079a63 bnez a5,80000da0 <_vx_mat_add+0x78> -80000d90: 00100793 li a5,1 -80000d94: fef42623 sw a5,-20(s0) -80000d98: fbc42783 lw a5,-68(s0) -80000d9c: fef42423 sw a5,-24(s0) -80000da0: fe042783 lw a5,-32(s0) -80000da4: 00c7a783 lw a5,12(a5) -80000da8: fcf42823 sw a5,-48(s0) -80000dac: fe042223 sw zero,-28(s0) -80000db0: 0c00006f j 80000e70 <_vx_mat_add+0x148> -80000db4: fb842703 lw a4,-72(s0) -80000db8: fd042783 lw a5,-48(s0) -80000dbc: 02f70733 mul a4,a4,a5 -80000dc0: fe842783 lw a5,-24(s0) -80000dc4: 00f707b3 add a5,a4,a5 -80000dc8: fcf42623 sw a5,-52(s0) -80000dcc: fe842703 lw a4,-24(s0) -80000dd0: fd042783 lw a5,-48(s0) -80000dd4: 00f737b3 sltu a5,a4,a5 -80000dd8: 0ff7f793 andi a5,a5,255 -80000ddc: fcf42423 sw a5,-56(s0) -80000de0: fc842783 lw a5,-56(s0) -80000de4: 0017b793 seqz a5,a5 -80000de8: fcf403a3 sb a5,-57(s0) -80000dec: fc744783 lbu a5,-57(s0) -80000df0: 00078f13 mv t5,a5 -80000df4: 800017b7 lui a5,0x80001 -80000df8: e5c78f93 addi t6,a5,-420 # 80000e5c -80000dfc: 000f206b 0xf206b -80000e00: 01ff707b 0x1ff707b -80000e04: fcc42783 lw a5,-52(s0) -80000e08: 00279793 slli a5,a5,0x2 -80000e0c: fdc42703 lw a4,-36(s0) -80000e10: 00f707b3 add a5,a4,a5 -80000e14: 0007a683 lw a3,0(a5) -80000e18: fcc42783 lw a5,-52(s0) -80000e1c: 00279793 slli a5,a5,0x2 -80000e20: fd842703 lw a4,-40(s0) -80000e24: 00f707b3 add a5,a4,a5 -80000e28: 0007a703 lw a4,0(a5) -80000e2c: fcc42783 lw a5,-52(s0) -80000e30: 00279793 slli a5,a5,0x2 -80000e34: fd442603 lw a2,-44(s0) -80000e38: 00f607b3 add a5,a2,a5 -80000e3c: 00e68733 add a4,a3,a4 -80000e40: 00e7a023 sw a4,0(a5) -80000e44: fe842783 lw a5,-24(s0) -80000e48: 00178793 addi a5,a5,1 -80000e4c: fef42423 sw a5,-24(s0) -80000e50: 800017b7 lui a5,0x80001 -80000e54: e6078e13 addi t3,a5,-416 # 80000e60 -80000e58: 000e0067 jr t3 -80000e5c: 00000013 nop -80000e60: 0000306b 0x306b -80000e64: fe442783 lw a5,-28(s0) -80000e68: 00178793 addi a5,a5,1 -80000e6c: fef42223 sw a5,-28(s0) -80000e70: fe442783 lw a5,-28(s0) -80000e74: fec42703 lw a4,-20(s0) -80000e78: f2e7eee3 bltu a5,a4,80000db4 <_vx_mat_add+0x8c> -80000e7c: 00000013 nop -80000e80: 04c12083 lw ra,76(sp) -80000e84: 04812403 lw s0,72(sp) -80000e88: 05010113 addi sp,sp,80 -80000e8c: 00008067 ret +80000cfc <_vx_mat_add>: +80000cfc: fb010113 addi sp,sp,-80 +80000d00: 04112623 sw ra,76(sp) +80000d04: 04812423 sw s0,72(sp) +80000d08: 05010413 addi s0,sp,80 +80000d0c: faa42e23 sw a0,-68(s0) +80000d10: fab42c23 sw a1,-72(s0) +80000d14: 941ff0ef jal ra,80000654 +80000d18: fea42023 sw a0,-32(s0) +80000d1c: fe042783 lw a5,-32(s0) +80000d20: 0007a783 lw a5,0(a5) +80000d24: fcf42e23 sw a5,-36(s0) +80000d28: fe042783 lw a5,-32(s0) +80000d2c: 0047a783 lw a5,4(a5) +80000d30: fcf42c23 sw a5,-40(s0) +80000d34: fe042783 lw a5,-32(s0) +80000d38: 0087a783 lw a5,8(a5) +80000d3c: fcf42a23 sw a5,-44(s0) +80000d40: fe042783 lw a5,-32(s0) +80000d44: 0147a783 lw a5,20(a5) +80000d48: fef42623 sw a5,-20(s0) +80000d4c: fec42703 lw a4,-20(s0) +80000d50: fbc42783 lw a5,-68(s0) +80000d54: 02f707b3 mul a5,a4,a5 +80000d58: fef42423 sw a5,-24(s0) +80000d5c: fec42783 lw a5,-20(s0) +80000d60: 00079a63 bnez a5,80000d74 <_vx_mat_add+0x78> +80000d64: 00100793 li a5,1 +80000d68: fef42623 sw a5,-20(s0) +80000d6c: fbc42783 lw a5,-68(s0) +80000d70: fef42423 sw a5,-24(s0) +80000d74: fe042783 lw a5,-32(s0) +80000d78: 00c7a783 lw a5,12(a5) +80000d7c: fcf42823 sw a5,-48(s0) +80000d80: fe042223 sw zero,-28(s0) +80000d84: 0c00006f j 80000e44 <_vx_mat_add+0x148> +80000d88: fb842703 lw a4,-72(s0) +80000d8c: fd042783 lw a5,-48(s0) +80000d90: 02f70733 mul a4,a4,a5 +80000d94: fe842783 lw a5,-24(s0) +80000d98: 00f707b3 add a5,a4,a5 +80000d9c: fcf42623 sw a5,-52(s0) +80000da0: fe842703 lw a4,-24(s0) +80000da4: fd042783 lw a5,-48(s0) +80000da8: 00f737b3 sltu a5,a4,a5 +80000dac: 0ff7f793 andi a5,a5,255 +80000db0: fcf42423 sw a5,-56(s0) +80000db4: fc842783 lw a5,-56(s0) +80000db8: 0017b793 seqz a5,a5 +80000dbc: fcf403a3 sb a5,-57(s0) +80000dc0: fc744783 lbu a5,-57(s0) +80000dc4: 00078f13 mv t5,a5 +80000dc8: 800017b7 lui a5,0x80001 +80000dcc: e3078f93 addi t6,a5,-464 # 80000e30 +80000dd0: 000f206b 0xf206b +80000dd4: 01ff707b 0x1ff707b +80000dd8: fcc42783 lw a5,-52(s0) +80000ddc: 00279793 slli a5,a5,0x2 +80000de0: fdc42703 lw a4,-36(s0) +80000de4: 00f707b3 add a5,a4,a5 +80000de8: 0007a683 lw a3,0(a5) +80000dec: fcc42783 lw a5,-52(s0) +80000df0: 00279793 slli a5,a5,0x2 +80000df4: fd842703 lw a4,-40(s0) +80000df8: 00f707b3 add a5,a4,a5 +80000dfc: 0007a703 lw a4,0(a5) +80000e00: fcc42783 lw a5,-52(s0) +80000e04: 00279793 slli a5,a5,0x2 +80000e08: fd442603 lw a2,-44(s0) +80000e0c: 00f607b3 add a5,a2,a5 +80000e10: 00e68733 add a4,a3,a4 +80000e14: 00e7a023 sw a4,0(a5) +80000e18: fe842783 lw a5,-24(s0) +80000e1c: 00178793 addi a5,a5,1 +80000e20: fef42423 sw a5,-24(s0) +80000e24: 800017b7 lui a5,0x80001 +80000e28: e3478e13 addi t3,a5,-460 # 80000e34 +80000e2c: 000e0067 jr t3 +80000e30: 00000013 nop +80000e34: 0000306b 0x306b +80000e38: fe442783 lw a5,-28(s0) +80000e3c: 00178793 addi a5,a5,1 +80000e40: fef42223 sw a5,-28(s0) +80000e44: fe442783 lw a5,-28(s0) +80000e48: fec42703 lw a4,-20(s0) +80000e4c: f2e7eee3 bltu a5,a4,80000d88 <_vx_mat_add+0x8c> +80000e50: 00000013 nop +80000e54: 04c12083 lw ra,76(sp) +80000e58: 04812403 lw s0,72(sp) +80000e5c: 05010113 addi sp,sp,80 +80000e60: 00008067 ret -80000e90 : -80000e90: fc010113 addi sp,sp,-64 -80000e94: 02112e23 sw ra,60(sp) -80000e98: 02812c23 sw s0,56(sp) -80000e9c: 04010413 addi s0,sp,64 -80000ea0: fca42e23 sw a0,-36(s0) -80000ea4: fcb42c23 sw a1,-40(s0) -80000ea8: fcc42a23 sw a2,-44(s0) -80000eac: fcd42823 sw a3,-48(s0) -80000eb0: fce42623 sw a4,-52(s0) +80000e64 : +80000e64: fc010113 addi sp,sp,-64 +80000e68: 02112e23 sw ra,60(sp) +80000e6c: 02812c23 sw s0,56(sp) +80000e70: 04010413 addi s0,sp,64 +80000e74: fca42e23 sw a0,-36(s0) +80000e78: fcb42c23 sw a1,-40(s0) +80000e7c: fcc42a23 sw a2,-44(s0) +80000e80: fcd42823 sw a3,-48(s0) +80000e84: fce42623 sw a4,-52(s0) +80000e88: 810267b7 lui a5,0x81026 +80000e8c: fdc42703 lw a4,-36(s0) +80000e90: 1ee7a423 sw a4,488(a5) # 810261e8 +80000e94: 810267b7 lui a5,0x81026 +80000e98: 1e878793 addi a5,a5,488 # 810261e8 +80000e9c: fd842703 lw a4,-40(s0) +80000ea0: 00e7a223 sw a4,4(a5) +80000ea4: 810267b7 lui a5,0x81026 +80000ea8: 1e878793 addi a5,a5,488 # 810261e8 +80000eac: fd442703 lw a4,-44(s0) +80000eb0: 00e7a423 sw a4,8(a5) 80000eb4: 810267b7 lui a5,0x81026 -80000eb8: fdc42703 lw a4,-36(s0) -80000ebc: 1ee7a823 sw a4,496(a5) # 810261f0 -80000ec0: 810267b7 lui a5,0x81026 -80000ec4: 1f078793 addi a5,a5,496 # 810261f0 -80000ec8: fd842703 lw a4,-40(s0) -80000ecc: 00e7a223 sw a4,4(a5) -80000ed0: 810267b7 lui a5,0x81026 -80000ed4: 1f078793 addi a5,a5,496 # 810261f0 -80000ed8: fd442703 lw a4,-44(s0) -80000edc: 00e7a423 sw a4,8(a5) -80000ee0: 810267b7 lui a5,0x81026 -80000ee4: 1f078793 addi a5,a5,496 # 810261f0 -80000ee8: fcc42703 lw a4,-52(s0) -80000eec: 00e7a623 sw a4,12(a5) -80000ef0: 810267b7 lui a5,0x81026 -80000ef4: 1f078793 addi a5,a5,496 # 810261f0 -80000ef8: fd042703 lw a4,-48(s0) -80000efc: 00e7a823 sw a4,16(a5) -80000f00: afcff0ef jal ra,800001fc -80000f04: fea42423 sw a0,-24(s0) -80000f08: fcc42703 lw a4,-52(s0) -80000f0c: fe842783 lw a5,-24(s0) -80000f10: 02f757b3 divu a5,a4,a5 -80000f14: fef42623 sw a5,-20(s0) +80000eb8: 1e878793 addi a5,a5,488 # 810261e8 +80000ebc: fcc42703 lw a4,-52(s0) +80000ec0: 00e7a623 sw a4,12(a5) +80000ec4: 810267b7 lui a5,0x81026 +80000ec8: 1e878793 addi a5,a5,488 # 810261e8 +80000ecc: fd042703 lw a4,-48(s0) +80000ed0: 00e7a823 sw a4,16(a5) +80000ed4: b28ff0ef jal ra,800001fc +80000ed8: fea42423 sw a0,-24(s0) +80000edc: fcc42703 lw a4,-52(s0) +80000ee0: fe842783 lw a5,-24(s0) +80000ee4: 02f757b3 divu a5,a4,a5 +80000ee8: fef42623 sw a5,-20(s0) +80000eec: fcc42703 lw a4,-52(s0) +80000ef0: fe842783 lw a5,-24(s0) +80000ef4: 02f777b3 remu a5,a4,a5 +80000ef8: 00078863 beqz a5,80000f08 +80000efc: fec42783 lw a5,-20(s0) +80000f00: 00178793 addi a5,a5,1 +80000f04: fef42623 sw a5,-20(s0) +80000f08: 810267b7 lui a5,0x81026 +80000f0c: 1e878793 addi a5,a5,488 # 810261e8 +80000f10: fec42703 lw a4,-20(s0) +80000f14: 00e7aa23 sw a4,20(a5) 80000f18: fcc42703 lw a4,-52(s0) 80000f1c: fe842783 lw a5,-24(s0) -80000f20: 02f777b3 remu a5,a4,a5 -80000f24: 00078863 beqz a5,80000f34 -80000f28: fec42783 lw a5,-20(s0) -80000f2c: 00178793 addi a5,a5,1 -80000f30: fef42623 sw a5,-20(s0) -80000f34: 810267b7 lui a5,0x81026 -80000f38: 1f078793 addi a5,a5,496 # 810261f0 -80000f3c: fec42703 lw a4,-20(s0) -80000f40: 00e7aa23 sw a4,20(a5) -80000f44: fcc42703 lw a4,-52(s0) -80000f48: fe842783 lw a5,-24(s0) -80000f4c: 02f76263 bltu a4,a5,80000f70 -80000f50: 810267b7 lui a5,0x81026 -80000f54: 1f078693 addi a3,a5,496 # 810261f0 -80000f58: 800017b7 lui a5,0x80001 -80000f5c: fc878613 addi a2,a5,-56 # 80000fc8 -80000f60: fe842583 lw a1,-24(s0) -80000f64: fd042503 lw a0,-48(s0) -80000f68: d4cff0ef jal ra,800004b4 -80000f6c: 0200006f j 80000f8c -80000f70: 810267b7 lui a5,0x81026 -80000f74: 1f078693 addi a3,a5,496 # 810261f0 -80000f78: 800017b7 lui a5,0x80001 -80000f7c: fc878613 addi a2,a5,-56 # 80000fc8 -80000f80: fcc42583 lw a1,-52(s0) -80000f84: fd042503 lw a0,-48(s0) -80000f88: d2cff0ef jal ra,800004b4 -80000f8c: a68ff0ef jal ra,800001f4 -80000f90: fea42223 sw a0,-28(s0) -80000f94: fd042703 lw a4,-48(s0) -80000f98: fe442783 lw a5,-28(s0) -80000f9c: 00e7f863 bgeu a5,a4,80000fac -80000fa0: fe442503 lw a0,-28(s0) -80000fa4: e00ff0ef jal ra,800005a4 -80000fa8: 00c0006f j 80000fb4 -80000fac: fd042503 lw a0,-48(s0) -80000fb0: df4ff0ef jal ra,800005a4 -80000fb4: 00000013 nop -80000fb8: 03c12083 lw ra,60(sp) -80000fbc: 03812403 lw s0,56(sp) -80000fc0: 04010113 addi sp,sp,64 -80000fc4: 00008067 ret +80000f20: 02f76263 bltu a4,a5,80000f44 +80000f24: 810267b7 lui a5,0x81026 +80000f28: 1e878693 addi a3,a5,488 # 810261e8 +80000f2c: 800017b7 lui a5,0x80001 +80000f30: f9c78613 addi a2,a5,-100 # 80000f9c +80000f34: fe842583 lw a1,-24(s0) +80000f38: fd042503 lw a0,-48(s0) +80000f3c: d38ff0ef jal ra,80000474 +80000f40: 0200006f j 80000f60 +80000f44: 810267b7 lui a5,0x81026 +80000f48: 1e878693 addi a3,a5,488 # 810261e8 +80000f4c: 800017b7 lui a5,0x80001 +80000f50: f9c78613 addi a2,a5,-100 # 80000f9c +80000f54: fcc42583 lw a1,-52(s0) +80000f58: fd042503 lw a0,-48(s0) +80000f5c: d18ff0ef jal ra,80000474 +80000f60: a94ff0ef jal ra,800001f4 +80000f64: fea42223 sw a0,-28(s0) +80000f68: fd042703 lw a4,-48(s0) +80000f6c: fe442783 lw a5,-28(s0) +80000f70: 00e7f863 bgeu a5,a4,80000f80 +80000f74: fe442503 lw a0,-28(s0) +80000f78: decff0ef jal ra,80000564 +80000f7c: 00c0006f j 80000f88 +80000f80: fd042503 lw a0,-48(s0) +80000f84: de0ff0ef jal ra,80000564 +80000f88: 00000013 nop +80000f8c: 03c12083 lw ra,60(sp) +80000f90: 03812403 lw s0,56(sp) +80000f94: 04010113 addi sp,sp,64 +80000f98: 00008067 ret -80000fc8 <_vx_mat_sub>: -80000fc8: fb010113 addi sp,sp,-80 -80000fcc: 04112623 sw ra,76(sp) -80000fd0: 04812423 sw s0,72(sp) -80000fd4: 05010413 addi s0,sp,80 -80000fd8: faa42e23 sw a0,-68(s0) -80000fdc: fab42c23 sw a1,-72(s0) -80000fe0: e90ff0ef jal ra,80000670 -80000fe4: fea42023 sw a0,-32(s0) -80000fe8: fe042783 lw a5,-32(s0) -80000fec: 0007a783 lw a5,0(a5) -80000ff0: fcf42e23 sw a5,-36(s0) -80000ff4: fe042783 lw a5,-32(s0) -80000ff8: 0047a783 lw a5,4(a5) -80000ffc: fcf42c23 sw a5,-40(s0) -80001000: fe042783 lw a5,-32(s0) -80001004: 0087a783 lw a5,8(a5) -80001008: fcf42a23 sw a5,-44(s0) -8000100c: fe042783 lw a5,-32(s0) -80001010: 0147a783 lw a5,20(a5) -80001014: fef42623 sw a5,-20(s0) -80001018: fec42703 lw a4,-20(s0) -8000101c: fbc42783 lw a5,-68(s0) -80001020: 02f707b3 mul a5,a4,a5 -80001024: fef42423 sw a5,-24(s0) -80001028: fec42783 lw a5,-20(s0) -8000102c: 00079a63 bnez a5,80001040 <_vx_mat_sub+0x78> -80001030: 00100793 li a5,1 -80001034: fef42623 sw a5,-20(s0) -80001038: fbc42783 lw a5,-68(s0) -8000103c: fef42423 sw a5,-24(s0) -80001040: fe042783 lw a5,-32(s0) -80001044: 00c7a783 lw a5,12(a5) -80001048: fcf42823 sw a5,-48(s0) -8000104c: fe042223 sw zero,-28(s0) -80001050: 0c00006f j 80001110 <_vx_mat_sub+0x148> -80001054: fb842703 lw a4,-72(s0) -80001058: fd042783 lw a5,-48(s0) -8000105c: 02f70733 mul a4,a4,a5 -80001060: fe842783 lw a5,-24(s0) -80001064: 00f707b3 add a5,a4,a5 -80001068: fcf42623 sw a5,-52(s0) -8000106c: fe842703 lw a4,-24(s0) -80001070: fd042783 lw a5,-48(s0) -80001074: 00f737b3 sltu a5,a4,a5 -80001078: 0ff7f793 andi a5,a5,255 -8000107c: fcf42423 sw a5,-56(s0) -80001080: fc842783 lw a5,-56(s0) -80001084: 0017b793 seqz a5,a5 -80001088: fcf403a3 sb a5,-57(s0) -8000108c: fc744783 lbu a5,-57(s0) -80001090: 00078f13 mv t5,a5 -80001094: 800017b7 lui a5,0x80001 -80001098: 0fc78f93 addi t6,a5,252 # 800010fc -8000109c: 000f206b 0xf206b -800010a0: 01ff707b 0x1ff707b -800010a4: fcc42783 lw a5,-52(s0) -800010a8: 00279793 slli a5,a5,0x2 -800010ac: fdc42703 lw a4,-36(s0) -800010b0: 00f707b3 add a5,a4,a5 -800010b4: 0007a683 lw a3,0(a5) -800010b8: fcc42783 lw a5,-52(s0) -800010bc: 00279793 slli a5,a5,0x2 -800010c0: fd842703 lw a4,-40(s0) -800010c4: 00f707b3 add a5,a4,a5 -800010c8: 0007a703 lw a4,0(a5) -800010cc: fcc42783 lw a5,-52(s0) -800010d0: 00279793 slli a5,a5,0x2 -800010d4: fd442603 lw a2,-44(s0) -800010d8: 00f607b3 add a5,a2,a5 -800010dc: 40e68733 sub a4,a3,a4 -800010e0: 00e7a023 sw a4,0(a5) -800010e4: fe842783 lw a5,-24(s0) -800010e8: 00178793 addi a5,a5,1 -800010ec: fef42423 sw a5,-24(s0) -800010f0: 800017b7 lui a5,0x80001 -800010f4: 10078e13 addi t3,a5,256 # 80001100 -800010f8: 000e0067 jr t3 -800010fc: 00000013 nop -80001100: 0000306b 0x306b -80001104: fe442783 lw a5,-28(s0) -80001108: 00178793 addi a5,a5,1 -8000110c: fef42223 sw a5,-28(s0) -80001110: fe442783 lw a5,-28(s0) -80001114: fec42703 lw a4,-20(s0) -80001118: f2e7eee3 bltu a5,a4,80001054 <_vx_mat_sub+0x8c> -8000111c: 00000013 nop -80001120: 04c12083 lw ra,76(sp) -80001124: 04812403 lw s0,72(sp) -80001128: 05010113 addi sp,sp,80 -8000112c: 00008067 ret +80000f9c <_vx_mat_sub>: +80000f9c: fb010113 addi sp,sp,-80 +80000fa0: 04112623 sw ra,76(sp) +80000fa4: 04812423 sw s0,72(sp) +80000fa8: 05010413 addi s0,sp,80 +80000fac: faa42e23 sw a0,-68(s0) +80000fb0: fab42c23 sw a1,-72(s0) +80000fb4: ea0ff0ef jal ra,80000654 +80000fb8: fea42023 sw a0,-32(s0) +80000fbc: fe042783 lw a5,-32(s0) +80000fc0: 0007a783 lw a5,0(a5) +80000fc4: fcf42e23 sw a5,-36(s0) +80000fc8: fe042783 lw a5,-32(s0) +80000fcc: 0047a783 lw a5,4(a5) +80000fd0: fcf42c23 sw a5,-40(s0) +80000fd4: fe042783 lw a5,-32(s0) +80000fd8: 0087a783 lw a5,8(a5) +80000fdc: fcf42a23 sw a5,-44(s0) +80000fe0: fe042783 lw a5,-32(s0) +80000fe4: 0147a783 lw a5,20(a5) +80000fe8: fef42623 sw a5,-20(s0) +80000fec: fec42703 lw a4,-20(s0) +80000ff0: fbc42783 lw a5,-68(s0) +80000ff4: 02f707b3 mul a5,a4,a5 +80000ff8: fef42423 sw a5,-24(s0) +80000ffc: fec42783 lw a5,-20(s0) +80001000: 00079a63 bnez a5,80001014 <_vx_mat_sub+0x78> +80001004: 00100793 li a5,1 +80001008: fef42623 sw a5,-20(s0) +8000100c: fbc42783 lw a5,-68(s0) +80001010: fef42423 sw a5,-24(s0) +80001014: fe042783 lw a5,-32(s0) +80001018: 00c7a783 lw a5,12(a5) +8000101c: fcf42823 sw a5,-48(s0) +80001020: fe042223 sw zero,-28(s0) +80001024: 0c00006f j 800010e4 <_vx_mat_sub+0x148> +80001028: fb842703 lw a4,-72(s0) +8000102c: fd042783 lw a5,-48(s0) +80001030: 02f70733 mul a4,a4,a5 +80001034: fe842783 lw a5,-24(s0) +80001038: 00f707b3 add a5,a4,a5 +8000103c: fcf42623 sw a5,-52(s0) +80001040: fe842703 lw a4,-24(s0) +80001044: fd042783 lw a5,-48(s0) +80001048: 00f737b3 sltu a5,a4,a5 +8000104c: 0ff7f793 andi a5,a5,255 +80001050: fcf42423 sw a5,-56(s0) +80001054: fc842783 lw a5,-56(s0) +80001058: 0017b793 seqz a5,a5 +8000105c: fcf403a3 sb a5,-57(s0) +80001060: fc744783 lbu a5,-57(s0) +80001064: 00078f13 mv t5,a5 +80001068: 800017b7 lui a5,0x80001 +8000106c: 0d078f93 addi t6,a5,208 # 800010d0 +80001070: 000f206b 0xf206b +80001074: 01ff707b 0x1ff707b +80001078: fcc42783 lw a5,-52(s0) +8000107c: 00279793 slli a5,a5,0x2 +80001080: fdc42703 lw a4,-36(s0) +80001084: 00f707b3 add a5,a4,a5 +80001088: 0007a683 lw a3,0(a5) +8000108c: fcc42783 lw a5,-52(s0) +80001090: 00279793 slli a5,a5,0x2 +80001094: fd842703 lw a4,-40(s0) +80001098: 00f707b3 add a5,a4,a5 +8000109c: 0007a703 lw a4,0(a5) +800010a0: fcc42783 lw a5,-52(s0) +800010a4: 00279793 slli a5,a5,0x2 +800010a8: fd442603 lw a2,-44(s0) +800010ac: 00f607b3 add a5,a2,a5 +800010b0: 40e68733 sub a4,a3,a4 +800010b4: 00e7a023 sw a4,0(a5) +800010b8: fe842783 lw a5,-24(s0) +800010bc: 00178793 addi a5,a5,1 +800010c0: fef42423 sw a5,-24(s0) +800010c4: 800017b7 lui a5,0x80001 +800010c8: 0d478e13 addi t3,a5,212 # 800010d4 +800010cc: 000e0067 jr t3 +800010d0: 00000013 nop +800010d4: 0000306b 0x306b +800010d8: fe442783 lw a5,-28(s0) +800010dc: 00178793 addi a5,a5,1 +800010e0: fef42223 sw a5,-28(s0) +800010e4: fe442783 lw a5,-28(s0) +800010e8: fec42703 lw a4,-20(s0) +800010ec: f2e7eee3 bltu a5,a4,80001028 <_vx_mat_sub+0x8c> +800010f0: 00000013 nop +800010f4: 04c12083 lw ra,76(sp) +800010f8: 04812403 lw s0,72(sp) +800010fc: 05010113 addi sp,sp,80 +80001100: 00008067 ret -80001130 : -80001130: fc010113 addi sp,sp,-64 -80001134: 02112e23 sw ra,60(sp) -80001138: 02812c23 sw s0,56(sp) -8000113c: 04010413 addi s0,sp,64 -80001140: fca42e23 sw a0,-36(s0) -80001144: fcb42c23 sw a1,-40(s0) -80001148: fcc42a23 sw a2,-44(s0) -8000114c: fcd42823 sw a3,-48(s0) -80001150: fce42623 sw a4,-52(s0) +80001104 : +80001104: fc010113 addi sp,sp,-64 +80001108: 02112e23 sw ra,60(sp) +8000110c: 02812c23 sw s0,56(sp) +80001110: 04010413 addi s0,sp,64 +80001114: fca42e23 sw a0,-36(s0) +80001118: fcb42c23 sw a1,-40(s0) +8000111c: fcc42a23 sw a2,-44(s0) +80001120: fcd42823 sw a3,-48(s0) +80001124: fce42623 sw a4,-52(s0) +80001128: 810267b7 lui a5,0x81026 +8000112c: fdc42703 lw a4,-36(s0) +80001130: 20e7a023 sw a4,512(a5) # 81026200 +80001134: 810267b7 lui a5,0x81026 +80001138: 20078793 addi a5,a5,512 # 81026200 +8000113c: fd842703 lw a4,-40(s0) +80001140: 00e7a223 sw a4,4(a5) +80001144: 810267b7 lui a5,0x81026 +80001148: 20078793 addi a5,a5,512 # 81026200 +8000114c: fd442703 lw a4,-44(s0) +80001150: 00e7a423 sw a4,8(a5) 80001154: 810267b7 lui a5,0x81026 -80001158: fdc42703 lw a4,-36(s0) -8000115c: 20e7a423 sw a4,520(a5) # 81026208 -80001160: 810267b7 lui a5,0x81026 -80001164: 20878793 addi a5,a5,520 # 81026208 -80001168: fd842703 lw a4,-40(s0) -8000116c: 00e7a223 sw a4,4(a5) -80001170: 810267b7 lui a5,0x81026 -80001174: 20878793 addi a5,a5,520 # 81026208 -80001178: fd442703 lw a4,-44(s0) -8000117c: 00e7a423 sw a4,8(a5) -80001180: 810267b7 lui a5,0x81026 -80001184: 20878793 addi a5,a5,520 # 81026208 -80001188: fcc42703 lw a4,-52(s0) -8000118c: 00e7a623 sw a4,12(a5) -80001190: 810267b7 lui a5,0x81026 -80001194: 20878793 addi a5,a5,520 # 81026208 -80001198: fd042703 lw a4,-48(s0) -8000119c: 00e7a823 sw a4,16(a5) -800011a0: 85cff0ef jal ra,800001fc -800011a4: fea42423 sw a0,-24(s0) -800011a8: fcc42703 lw a4,-52(s0) -800011ac: fe842783 lw a5,-24(s0) -800011b0: 02f757b3 divu a5,a4,a5 -800011b4: fef42623 sw a5,-20(s0) +80001158: 20078793 addi a5,a5,512 # 81026200 +8000115c: fcc42703 lw a4,-52(s0) +80001160: 00e7a623 sw a4,12(a5) +80001164: 810267b7 lui a5,0x81026 +80001168: 20078793 addi a5,a5,512 # 81026200 +8000116c: fd042703 lw a4,-48(s0) +80001170: 00e7a823 sw a4,16(a5) +80001174: 888ff0ef jal ra,800001fc +80001178: fea42423 sw a0,-24(s0) +8000117c: fcc42703 lw a4,-52(s0) +80001180: fe842783 lw a5,-24(s0) +80001184: 02f757b3 divu a5,a4,a5 +80001188: fef42623 sw a5,-20(s0) +8000118c: fcc42703 lw a4,-52(s0) +80001190: fe842783 lw a5,-24(s0) +80001194: 02f777b3 remu a5,a4,a5 +80001198: 00078863 beqz a5,800011a8 +8000119c: fec42783 lw a5,-20(s0) +800011a0: 00178793 addi a5,a5,1 +800011a4: fef42623 sw a5,-20(s0) +800011a8: 810267b7 lui a5,0x81026 +800011ac: 20078793 addi a5,a5,512 # 81026200 +800011b0: fec42703 lw a4,-20(s0) +800011b4: 00e7aa23 sw a4,20(a5) 800011b8: fcc42703 lw a4,-52(s0) 800011bc: fe842783 lw a5,-24(s0) -800011c0: 02f777b3 remu a5,a4,a5 -800011c4: 00078863 beqz a5,800011d4 -800011c8: fec42783 lw a5,-20(s0) -800011cc: 00178793 addi a5,a5,1 -800011d0: fef42623 sw a5,-20(s0) -800011d4: 810267b7 lui a5,0x81026 -800011d8: 20878793 addi a5,a5,520 # 81026208 -800011dc: fec42703 lw a4,-20(s0) -800011e0: 00e7aa23 sw a4,20(a5) -800011e4: fcc42703 lw a4,-52(s0) -800011e8: fe842783 lw a5,-24(s0) -800011ec: 02f76263 bltu a4,a5,80001210 -800011f0: 810267b7 lui a5,0x81026 -800011f4: 20878693 addi a3,a5,520 # 81026208 -800011f8: 800017b7 lui a5,0x80001 -800011fc: 26878613 addi a2,a5,616 # 80001268 -80001200: fe842583 lw a1,-24(s0) -80001204: fd042503 lw a0,-48(s0) -80001208: aacff0ef jal ra,800004b4 -8000120c: 0200006f j 8000122c -80001210: 810267b7 lui a5,0x81026 -80001214: 20878693 addi a3,a5,520 # 81026208 -80001218: 800017b7 lui a5,0x80001 -8000121c: 26878613 addi a2,a5,616 # 80001268 -80001220: fcc42583 lw a1,-52(s0) -80001224: fd042503 lw a0,-48(s0) -80001228: a8cff0ef jal ra,800004b4 -8000122c: fc9fe0ef jal ra,800001f4 -80001230: fea42223 sw a0,-28(s0) -80001234: fd042703 lw a4,-48(s0) -80001238: fe442783 lw a5,-28(s0) -8000123c: 00e7f863 bgeu a5,a4,8000124c -80001240: fe442503 lw a0,-28(s0) -80001244: b60ff0ef jal ra,800005a4 -80001248: 00c0006f j 80001254 -8000124c: fd042503 lw a0,-48(s0) -80001250: b54ff0ef jal ra,800005a4 -80001254: 00000013 nop -80001258: 03c12083 lw ra,60(sp) -8000125c: 03812403 lw s0,56(sp) -80001260: 04010113 addi sp,sp,64 -80001264: 00008067 ret +800011c0: 02f76263 bltu a4,a5,800011e4 +800011c4: 810267b7 lui a5,0x81026 +800011c8: 20078693 addi a3,a5,512 # 81026200 +800011cc: 800017b7 lui a5,0x80001 +800011d0: 23c78613 addi a2,a5,572 # 8000123c +800011d4: fe842583 lw a1,-24(s0) +800011d8: fd042503 lw a0,-48(s0) +800011dc: a98ff0ef jal ra,80000474 +800011e0: 0200006f j 80001200 +800011e4: 810267b7 lui a5,0x81026 +800011e8: 20078693 addi a3,a5,512 # 81026200 +800011ec: 800017b7 lui a5,0x80001 +800011f0: 23c78613 addi a2,a5,572 # 8000123c +800011f4: fcc42583 lw a1,-52(s0) +800011f8: fd042503 lw a0,-48(s0) +800011fc: a78ff0ef jal ra,80000474 +80001200: ff5fe0ef jal ra,800001f4 +80001204: fea42223 sw a0,-28(s0) +80001208: fd042703 lw a4,-48(s0) +8000120c: fe442783 lw a5,-28(s0) +80001210: 00e7f863 bgeu a5,a4,80001220 +80001214: fe442503 lw a0,-28(s0) +80001218: b4cff0ef jal ra,80000564 +8000121c: 00c0006f j 80001228 +80001220: fd042503 lw a0,-48(s0) +80001224: b40ff0ef jal ra,80000564 +80001228: 00000013 nop +8000122c: 03c12083 lw ra,60(sp) +80001230: 03812403 lw s0,56(sp) +80001234: 04010113 addi sp,sp,64 +80001238: 00008067 ret -80001268 <_vx_e_mat_add>: -80001268: fb010113 addi sp,sp,-80 -8000126c: 04112623 sw ra,76(sp) -80001270: 04812423 sw s0,72(sp) -80001274: 05010413 addi s0,sp,80 -80001278: faa42e23 sw a0,-68(s0) -8000127c: fab42c23 sw a1,-72(s0) -80001280: bf0ff0ef jal ra,80000670 -80001284: fea42023 sw a0,-32(s0) -80001288: fe042783 lw a5,-32(s0) -8000128c: 0007a783 lw a5,0(a5) -80001290: fcf42e23 sw a5,-36(s0) -80001294: fe042783 lw a5,-32(s0) -80001298: 0047a783 lw a5,4(a5) -8000129c: 0007a783 lw a5,0(a5) -800012a0: fcf42c23 sw a5,-40(s0) -800012a4: fe042783 lw a5,-32(s0) -800012a8: 0087a783 lw a5,8(a5) -800012ac: fcf42a23 sw a5,-44(s0) -800012b0: fe042783 lw a5,-32(s0) -800012b4: 0147a783 lw a5,20(a5) -800012b8: fef42623 sw a5,-20(s0) -800012bc: fec42703 lw a4,-20(s0) -800012c0: fbc42783 lw a5,-68(s0) -800012c4: 02f707b3 mul a5,a4,a5 -800012c8: fef42423 sw a5,-24(s0) -800012cc: fec42783 lw a5,-20(s0) -800012d0: 00079a63 bnez a5,800012e4 <_vx_e_mat_add+0x7c> -800012d4: 00100793 li a5,1 -800012d8: fef42623 sw a5,-20(s0) -800012dc: fbc42783 lw a5,-68(s0) -800012e0: fef42423 sw a5,-24(s0) -800012e4: fe042783 lw a5,-32(s0) -800012e8: 00c7a783 lw a5,12(a5) -800012ec: fcf42823 sw a5,-48(s0) -800012f0: fe042223 sw zero,-28(s0) -800012f4: 0b00006f j 800013a4 <_vx_e_mat_add+0x13c> -800012f8: fb842703 lw a4,-72(s0) -800012fc: fd042783 lw a5,-48(s0) -80001300: 02f70733 mul a4,a4,a5 -80001304: fe842783 lw a5,-24(s0) -80001308: 00f707b3 add a5,a4,a5 -8000130c: fcf42623 sw a5,-52(s0) -80001310: fe842703 lw a4,-24(s0) -80001314: fd042783 lw a5,-48(s0) -80001318: 00f737b3 sltu a5,a4,a5 -8000131c: 0ff7f793 andi a5,a5,255 -80001320: fcf42423 sw a5,-56(s0) -80001324: fc842783 lw a5,-56(s0) -80001328: 0017b793 seqz a5,a5 -8000132c: fcf403a3 sb a5,-57(s0) -80001330: fc744783 lbu a5,-57(s0) -80001334: 00078f13 mv t5,a5 -80001338: 800017b7 lui a5,0x80001 -8000133c: 39078f93 addi t6,a5,912 # 80001390 -80001340: 000f206b 0xf206b -80001344: 01ff707b 0x1ff707b -80001348: fcc42783 lw a5,-52(s0) -8000134c: 00279793 slli a5,a5,0x2 -80001350: fdc42703 lw a4,-36(s0) -80001354: 00f707b3 add a5,a4,a5 -80001358: 0007a683 lw a3,0(a5) -8000135c: fcc42783 lw a5,-52(s0) -80001360: 00279793 slli a5,a5,0x2 -80001364: fd442703 lw a4,-44(s0) -80001368: 00f707b3 add a5,a4,a5 -8000136c: fd842703 lw a4,-40(s0) -80001370: 00e68733 add a4,a3,a4 -80001374: 00e7a023 sw a4,0(a5) -80001378: fe842783 lw a5,-24(s0) -8000137c: 00178793 addi a5,a5,1 -80001380: fef42423 sw a5,-24(s0) -80001384: 800017b7 lui a5,0x80001 -80001388: 39478e13 addi t3,a5,916 # 80001394 -8000138c: 000e0067 jr t3 -80001390: 00000013 nop -80001394: 0000306b 0x306b -80001398: fe442783 lw a5,-28(s0) -8000139c: 00178793 addi a5,a5,1 -800013a0: fef42223 sw a5,-28(s0) -800013a4: fe442783 lw a5,-28(s0) -800013a8: fec42703 lw a4,-20(s0) -800013ac: f4e7e6e3 bltu a5,a4,800012f8 <_vx_e_mat_add+0x90> -800013b0: 00000013 nop -800013b4: 04c12083 lw ra,76(sp) -800013b8: 04812403 lw s0,72(sp) -800013bc: 05010113 addi sp,sp,80 -800013c0: 00008067 ret +8000123c <_vx_e_mat_add>: +8000123c: fb010113 addi sp,sp,-80 +80001240: 04112623 sw ra,76(sp) +80001244: 04812423 sw s0,72(sp) +80001248: 05010413 addi s0,sp,80 +8000124c: faa42e23 sw a0,-68(s0) +80001250: fab42c23 sw a1,-72(s0) +80001254: c00ff0ef jal ra,80000654 +80001258: fea42023 sw a0,-32(s0) +8000125c: fe042783 lw a5,-32(s0) +80001260: 0007a783 lw a5,0(a5) +80001264: fcf42e23 sw a5,-36(s0) +80001268: fe042783 lw a5,-32(s0) +8000126c: 0047a783 lw a5,4(a5) +80001270: 0007a783 lw a5,0(a5) +80001274: fcf42c23 sw a5,-40(s0) +80001278: fe042783 lw a5,-32(s0) +8000127c: 0087a783 lw a5,8(a5) +80001280: fcf42a23 sw a5,-44(s0) +80001284: fe042783 lw a5,-32(s0) +80001288: 0147a783 lw a5,20(a5) +8000128c: fef42623 sw a5,-20(s0) +80001290: fec42703 lw a4,-20(s0) +80001294: fbc42783 lw a5,-68(s0) +80001298: 02f707b3 mul a5,a4,a5 +8000129c: fef42423 sw a5,-24(s0) +800012a0: fec42783 lw a5,-20(s0) +800012a4: 00079a63 bnez a5,800012b8 <_vx_e_mat_add+0x7c> +800012a8: 00100793 li a5,1 +800012ac: fef42623 sw a5,-20(s0) +800012b0: fbc42783 lw a5,-68(s0) +800012b4: fef42423 sw a5,-24(s0) +800012b8: fe042783 lw a5,-32(s0) +800012bc: 00c7a783 lw a5,12(a5) +800012c0: fcf42823 sw a5,-48(s0) +800012c4: fe042223 sw zero,-28(s0) +800012c8: 0b00006f j 80001378 <_vx_e_mat_add+0x13c> +800012cc: fb842703 lw a4,-72(s0) +800012d0: fd042783 lw a5,-48(s0) +800012d4: 02f70733 mul a4,a4,a5 +800012d8: fe842783 lw a5,-24(s0) +800012dc: 00f707b3 add a5,a4,a5 +800012e0: fcf42623 sw a5,-52(s0) +800012e4: fe842703 lw a4,-24(s0) +800012e8: fd042783 lw a5,-48(s0) +800012ec: 00f737b3 sltu a5,a4,a5 +800012f0: 0ff7f793 andi a5,a5,255 +800012f4: fcf42423 sw a5,-56(s0) +800012f8: fc842783 lw a5,-56(s0) +800012fc: 0017b793 seqz a5,a5 +80001300: fcf403a3 sb a5,-57(s0) +80001304: fc744783 lbu a5,-57(s0) +80001308: 00078f13 mv t5,a5 +8000130c: 800017b7 lui a5,0x80001 +80001310: 36478f93 addi t6,a5,868 # 80001364 +80001314: 000f206b 0xf206b +80001318: 01ff707b 0x1ff707b +8000131c: fcc42783 lw a5,-52(s0) +80001320: 00279793 slli a5,a5,0x2 +80001324: fdc42703 lw a4,-36(s0) +80001328: 00f707b3 add a5,a4,a5 +8000132c: 0007a683 lw a3,0(a5) +80001330: fcc42783 lw a5,-52(s0) +80001334: 00279793 slli a5,a5,0x2 +80001338: fd442703 lw a4,-44(s0) +8000133c: 00f707b3 add a5,a4,a5 +80001340: fd842703 lw a4,-40(s0) +80001344: 00e68733 add a4,a3,a4 +80001348: 00e7a023 sw a4,0(a5) +8000134c: fe842783 lw a5,-24(s0) +80001350: 00178793 addi a5,a5,1 +80001354: fef42423 sw a5,-24(s0) +80001358: 800017b7 lui a5,0x80001 +8000135c: 36878e13 addi t3,a5,872 # 80001368 +80001360: 000e0067 jr t3 +80001364: 00000013 nop +80001368: 0000306b 0x306b +8000136c: fe442783 lw a5,-28(s0) +80001370: 00178793 addi a5,a5,1 +80001374: fef42223 sw a5,-28(s0) +80001378: fe442783 lw a5,-28(s0) +8000137c: fec42703 lw a4,-20(s0) +80001380: f4e7e6e3 bltu a5,a4,800012cc <_vx_e_mat_add+0x90> +80001384: 00000013 nop +80001388: 04c12083 lw ra,76(sp) +8000138c: 04812403 lw s0,72(sp) +80001390: 05010113 addi sp,sp,80 +80001394: 00008067 ret -800013c4 : -800013c4: fc010113 addi sp,sp,-64 -800013c8: 02112e23 sw ra,60(sp) -800013cc: 02812c23 sw s0,56(sp) -800013d0: 04010413 addi s0,sp,64 -800013d4: fca42e23 sw a0,-36(s0) -800013d8: fcb42c23 sw a1,-40(s0) -800013dc: fcc42a23 sw a2,-44(s0) -800013e0: fcd42823 sw a3,-48(s0) -800013e4: fce42623 sw a4,-52(s0) +80001398 : +80001398: fc010113 addi sp,sp,-64 +8000139c: 02112e23 sw ra,60(sp) +800013a0: 02812c23 sw s0,56(sp) +800013a4: 04010413 addi s0,sp,64 +800013a8: fca42e23 sw a0,-36(s0) +800013ac: fcb42c23 sw a1,-40(s0) +800013b0: fcc42a23 sw a2,-44(s0) +800013b4: fcd42823 sw a3,-48(s0) +800013b8: fce42623 sw a4,-52(s0) +800013bc: 810267b7 lui a5,0x81026 +800013c0: fdc42703 lw a4,-36(s0) +800013c4: 20e7a023 sw a4,512(a5) # 81026200 +800013c8: 810267b7 lui a5,0x81026 +800013cc: 20078793 addi a5,a5,512 # 81026200 +800013d0: fd842703 lw a4,-40(s0) +800013d4: 00e7a223 sw a4,4(a5) +800013d8: 810267b7 lui a5,0x81026 +800013dc: 20078793 addi a5,a5,512 # 81026200 +800013e0: fd442703 lw a4,-44(s0) +800013e4: 00e7a423 sw a4,8(a5) 800013e8: 810267b7 lui a5,0x81026 -800013ec: fdc42703 lw a4,-36(s0) -800013f0: 20e7a423 sw a4,520(a5) # 81026208 -800013f4: 810267b7 lui a5,0x81026 -800013f8: 20878793 addi a5,a5,520 # 81026208 -800013fc: fd842703 lw a4,-40(s0) -80001400: 00e7a223 sw a4,4(a5) -80001404: 810267b7 lui a5,0x81026 -80001408: 20878793 addi a5,a5,520 # 81026208 -8000140c: fd442703 lw a4,-44(s0) -80001410: 00e7a423 sw a4,8(a5) -80001414: 810267b7 lui a5,0x81026 -80001418: 20878793 addi a5,a5,520 # 81026208 -8000141c: fcc42703 lw a4,-52(s0) -80001420: 00e7a623 sw a4,12(a5) -80001424: 810267b7 lui a5,0x81026 -80001428: 20878793 addi a5,a5,520 # 81026208 -8000142c: fd042703 lw a4,-48(s0) -80001430: 00e7a823 sw a4,16(a5) -80001434: dc9fe0ef jal ra,800001fc -80001438: fea42423 sw a0,-24(s0) -8000143c: fcc42703 lw a4,-52(s0) -80001440: fe842783 lw a5,-24(s0) -80001444: 02f757b3 divu a5,a4,a5 -80001448: fef42623 sw a5,-20(s0) +800013ec: 20078793 addi a5,a5,512 # 81026200 +800013f0: fcc42703 lw a4,-52(s0) +800013f4: 00e7a623 sw a4,12(a5) +800013f8: 810267b7 lui a5,0x81026 +800013fc: 20078793 addi a5,a5,512 # 81026200 +80001400: fd042703 lw a4,-48(s0) +80001404: 00e7a823 sw a4,16(a5) +80001408: df5fe0ef jal ra,800001fc +8000140c: fea42423 sw a0,-24(s0) +80001410: fcc42703 lw a4,-52(s0) +80001414: fe842783 lw a5,-24(s0) +80001418: 02f757b3 divu a5,a4,a5 +8000141c: fef42623 sw a5,-20(s0) +80001420: fcc42703 lw a4,-52(s0) +80001424: fe842783 lw a5,-24(s0) +80001428: 02f777b3 remu a5,a4,a5 +8000142c: 00078863 beqz a5,8000143c +80001430: fec42783 lw a5,-20(s0) +80001434: 00178793 addi a5,a5,1 +80001438: fef42623 sw a5,-20(s0) +8000143c: 810267b7 lui a5,0x81026 +80001440: 20078793 addi a5,a5,512 # 81026200 +80001444: fec42703 lw a4,-20(s0) +80001448: 00e7aa23 sw a4,20(a5) 8000144c: fcc42703 lw a4,-52(s0) 80001450: fe842783 lw a5,-24(s0) -80001454: 02f777b3 remu a5,a4,a5 -80001458: 00078863 beqz a5,80001468 -8000145c: fec42783 lw a5,-20(s0) -80001460: 00178793 addi a5,a5,1 -80001464: fef42623 sw a5,-20(s0) -80001468: 810267b7 lui a5,0x81026 -8000146c: 20878793 addi a5,a5,520 # 81026208 -80001470: fec42703 lw a4,-20(s0) -80001474: 00e7aa23 sw a4,20(a5) -80001478: fcc42703 lw a4,-52(s0) -8000147c: fe842783 lw a5,-24(s0) -80001480: 02f76263 bltu a4,a5,800014a4 -80001484: 810267b7 lui a5,0x81026 -80001488: 20878693 addi a3,a5,520 # 81026208 -8000148c: 800017b7 lui a5,0x80001 -80001490: 4fc78613 addi a2,a5,1276 # 800014fc -80001494: fe842583 lw a1,-24(s0) -80001498: fd042503 lw a0,-48(s0) -8000149c: 818ff0ef jal ra,800004b4 -800014a0: 0200006f j 800014c0 -800014a4: 810267b7 lui a5,0x81026 -800014a8: 20878693 addi a3,a5,520 # 81026208 -800014ac: 800017b7 lui a5,0x80001 -800014b0: 4fc78613 addi a2,a5,1276 # 800014fc -800014b4: fcc42583 lw a1,-52(s0) -800014b8: fd042503 lw a0,-48(s0) -800014bc: ff9fe0ef jal ra,800004b4 -800014c0: d35fe0ef jal ra,800001f4 -800014c4: fea42223 sw a0,-28(s0) -800014c8: fd042703 lw a4,-48(s0) -800014cc: fe442783 lw a5,-28(s0) -800014d0: 00e7f863 bgeu a5,a4,800014e0 -800014d4: fe442503 lw a0,-28(s0) -800014d8: 8ccff0ef jal ra,800005a4 -800014dc: 00c0006f j 800014e8 -800014e0: fd042503 lw a0,-48(s0) -800014e4: 8c0ff0ef jal ra,800005a4 -800014e8: 00000013 nop -800014ec: 03c12083 lw ra,60(sp) -800014f0: 03812403 lw s0,56(sp) -800014f4: 04010113 addi sp,sp,64 -800014f8: 00008067 ret +80001454: 02f76263 bltu a4,a5,80001478 +80001458: 810267b7 lui a5,0x81026 +8000145c: 20078693 addi a3,a5,512 # 81026200 +80001460: 800017b7 lui a5,0x80001 +80001464: 4d078613 addi a2,a5,1232 # 800014d0 +80001468: fe842583 lw a1,-24(s0) +8000146c: fd042503 lw a0,-48(s0) +80001470: 804ff0ef jal ra,80000474 +80001474: 0200006f j 80001494 +80001478: 810267b7 lui a5,0x81026 +8000147c: 20078693 addi a3,a5,512 # 81026200 +80001480: 800017b7 lui a5,0x80001 +80001484: 4d078613 addi a2,a5,1232 # 800014d0 +80001488: fcc42583 lw a1,-52(s0) +8000148c: fd042503 lw a0,-48(s0) +80001490: fe5fe0ef jal ra,80000474 +80001494: d61fe0ef jal ra,800001f4 +80001498: fea42223 sw a0,-28(s0) +8000149c: fd042703 lw a4,-48(s0) +800014a0: fe442783 lw a5,-28(s0) +800014a4: 00e7f863 bgeu a5,a4,800014b4 +800014a8: fe442503 lw a0,-28(s0) +800014ac: 8b8ff0ef jal ra,80000564 +800014b0: 00c0006f j 800014bc +800014b4: fd042503 lw a0,-48(s0) +800014b8: 8acff0ef jal ra,80000564 +800014bc: 00000013 nop +800014c0: 03c12083 lw ra,60(sp) +800014c4: 03812403 lw s0,56(sp) +800014c8: 04010113 addi sp,sp,64 +800014cc: 00008067 ret -800014fc <_vx_e_mat_mult>: -800014fc: fb010113 addi sp,sp,-80 -80001500: 04112623 sw ra,76(sp) -80001504: 04812423 sw s0,72(sp) -80001508: 05010413 addi s0,sp,80 -8000150c: faa42e23 sw a0,-68(s0) -80001510: fab42c23 sw a1,-72(s0) -80001514: 95cff0ef jal ra,80000670 -80001518: fea42023 sw a0,-32(s0) -8000151c: fe042783 lw a5,-32(s0) -80001520: 0007a783 lw a5,0(a5) -80001524: fcf42e23 sw a5,-36(s0) -80001528: fe042783 lw a5,-32(s0) -8000152c: 0047a783 lw a5,4(a5) -80001530: 0007a783 lw a5,0(a5) -80001534: fcf42c23 sw a5,-40(s0) -80001538: fe042783 lw a5,-32(s0) -8000153c: 0087a783 lw a5,8(a5) -80001540: fcf42a23 sw a5,-44(s0) -80001544: fe042783 lw a5,-32(s0) -80001548: 0147a783 lw a5,20(a5) -8000154c: fef42623 sw a5,-20(s0) -80001550: fec42703 lw a4,-20(s0) -80001554: fbc42783 lw a5,-68(s0) -80001558: 02f707b3 mul a5,a4,a5 -8000155c: fef42423 sw a5,-24(s0) -80001560: fec42783 lw a5,-20(s0) -80001564: 00079a63 bnez a5,80001578 <_vx_e_mat_mult+0x7c> -80001568: 00100793 li a5,1 -8000156c: fef42623 sw a5,-20(s0) -80001570: fbc42783 lw a5,-68(s0) -80001574: fef42423 sw a5,-24(s0) -80001578: fe042783 lw a5,-32(s0) -8000157c: 00c7a783 lw a5,12(a5) -80001580: fcf42823 sw a5,-48(s0) -80001584: fe042223 sw zero,-28(s0) -80001588: 0b00006f j 80001638 <_vx_e_mat_mult+0x13c> -8000158c: fb842703 lw a4,-72(s0) -80001590: fd042783 lw a5,-48(s0) -80001594: 02f70733 mul a4,a4,a5 -80001598: fe842783 lw a5,-24(s0) -8000159c: 00f707b3 add a5,a4,a5 -800015a0: fcf42623 sw a5,-52(s0) -800015a4: fe842703 lw a4,-24(s0) -800015a8: fd042783 lw a5,-48(s0) -800015ac: 00f737b3 sltu a5,a4,a5 -800015b0: 0ff7f793 andi a5,a5,255 -800015b4: fcf42423 sw a5,-56(s0) -800015b8: fc842783 lw a5,-56(s0) -800015bc: 0017b793 seqz a5,a5 -800015c0: fcf403a3 sb a5,-57(s0) -800015c4: fc744783 lbu a5,-57(s0) -800015c8: 00078f13 mv t5,a5 -800015cc: 800017b7 lui a5,0x80001 -800015d0: 62478f93 addi t6,a5,1572 # 80001624 -800015d4: 000f206b 0xf206b -800015d8: 01ff707b 0x1ff707b -800015dc: fcc42783 lw a5,-52(s0) -800015e0: 00279793 slli a5,a5,0x2 -800015e4: fdc42703 lw a4,-36(s0) -800015e8: 00f707b3 add a5,a4,a5 -800015ec: 0007a683 lw a3,0(a5) -800015f0: fcc42783 lw a5,-52(s0) -800015f4: 00279793 slli a5,a5,0x2 -800015f8: fd442703 lw a4,-44(s0) -800015fc: 00f707b3 add a5,a4,a5 -80001600: fd842703 lw a4,-40(s0) -80001604: 02e68733 mul a4,a3,a4 -80001608: 00e7a023 sw a4,0(a5) -8000160c: fe842783 lw a5,-24(s0) -80001610: 00178793 addi a5,a5,1 -80001614: fef42423 sw a5,-24(s0) -80001618: 800017b7 lui a5,0x80001 -8000161c: 62878e13 addi t3,a5,1576 # 80001628 -80001620: 000e0067 jr t3 -80001624: 00000013 nop -80001628: 0000306b 0x306b -8000162c: fe442783 lw a5,-28(s0) -80001630: 00178793 addi a5,a5,1 -80001634: fef42223 sw a5,-28(s0) -80001638: fe442783 lw a5,-28(s0) -8000163c: fec42703 lw a4,-20(s0) -80001640: f4e7e6e3 bltu a5,a4,8000158c <_vx_e_mat_mult+0x90> -80001644: 00000013 nop -80001648: 04c12083 lw ra,76(sp) -8000164c: 04812403 lw s0,72(sp) -80001650: 05010113 addi sp,sp,80 -80001654: 00008067 ret +800014d0 <_vx_e_mat_mult>: +800014d0: fb010113 addi sp,sp,-80 +800014d4: 04112623 sw ra,76(sp) +800014d8: 04812423 sw s0,72(sp) +800014dc: 05010413 addi s0,sp,80 +800014e0: faa42e23 sw a0,-68(s0) +800014e4: fab42c23 sw a1,-72(s0) +800014e8: 96cff0ef jal ra,80000654 +800014ec: fea42023 sw a0,-32(s0) +800014f0: fe042783 lw a5,-32(s0) +800014f4: 0007a783 lw a5,0(a5) +800014f8: fcf42e23 sw a5,-36(s0) +800014fc: fe042783 lw a5,-32(s0) +80001500: 0047a783 lw a5,4(a5) +80001504: 0007a783 lw a5,0(a5) +80001508: fcf42c23 sw a5,-40(s0) +8000150c: fe042783 lw a5,-32(s0) +80001510: 0087a783 lw a5,8(a5) +80001514: fcf42a23 sw a5,-44(s0) +80001518: fe042783 lw a5,-32(s0) +8000151c: 0147a783 lw a5,20(a5) +80001520: fef42623 sw a5,-20(s0) +80001524: fec42703 lw a4,-20(s0) +80001528: fbc42783 lw a5,-68(s0) +8000152c: 02f707b3 mul a5,a4,a5 +80001530: fef42423 sw a5,-24(s0) +80001534: fec42783 lw a5,-20(s0) +80001538: 00079a63 bnez a5,8000154c <_vx_e_mat_mult+0x7c> +8000153c: 00100793 li a5,1 +80001540: fef42623 sw a5,-20(s0) +80001544: fbc42783 lw a5,-68(s0) +80001548: fef42423 sw a5,-24(s0) +8000154c: fe042783 lw a5,-32(s0) +80001550: 00c7a783 lw a5,12(a5) +80001554: fcf42823 sw a5,-48(s0) +80001558: fe042223 sw zero,-28(s0) +8000155c: 0b00006f j 8000160c <_vx_e_mat_mult+0x13c> +80001560: fb842703 lw a4,-72(s0) +80001564: fd042783 lw a5,-48(s0) +80001568: 02f70733 mul a4,a4,a5 +8000156c: fe842783 lw a5,-24(s0) +80001570: 00f707b3 add a5,a4,a5 +80001574: fcf42623 sw a5,-52(s0) +80001578: fe842703 lw a4,-24(s0) +8000157c: fd042783 lw a5,-48(s0) +80001580: 00f737b3 sltu a5,a4,a5 +80001584: 0ff7f793 andi a5,a5,255 +80001588: fcf42423 sw a5,-56(s0) +8000158c: fc842783 lw a5,-56(s0) +80001590: 0017b793 seqz a5,a5 +80001594: fcf403a3 sb a5,-57(s0) +80001598: fc744783 lbu a5,-57(s0) +8000159c: 00078f13 mv t5,a5 +800015a0: 800017b7 lui a5,0x80001 +800015a4: 5f878f93 addi t6,a5,1528 # 800015f8 +800015a8: 000f206b 0xf206b +800015ac: 01ff707b 0x1ff707b +800015b0: fcc42783 lw a5,-52(s0) +800015b4: 00279793 slli a5,a5,0x2 +800015b8: fdc42703 lw a4,-36(s0) +800015bc: 00f707b3 add a5,a4,a5 +800015c0: 0007a683 lw a3,0(a5) +800015c4: fcc42783 lw a5,-52(s0) +800015c8: 00279793 slli a5,a5,0x2 +800015cc: fd442703 lw a4,-44(s0) +800015d0: 00f707b3 add a5,a4,a5 +800015d4: fd842703 lw a4,-40(s0) +800015d8: 02e68733 mul a4,a3,a4 +800015dc: 00e7a023 sw a4,0(a5) +800015e0: fe842783 lw a5,-24(s0) +800015e4: 00178793 addi a5,a5,1 +800015e8: fef42423 sw a5,-24(s0) +800015ec: 800017b7 lui a5,0x80001 +800015f0: 5fc78e13 addi t3,a5,1532 # 800015fc +800015f4: 000e0067 jr t3 +800015f8: 00000013 nop +800015fc: 0000306b 0x306b +80001600: fe442783 lw a5,-28(s0) +80001604: 00178793 addi a5,a5,1 +80001608: fef42223 sw a5,-28(s0) +8000160c: fe442783 lw a5,-28(s0) +80001610: fec42703 lw a4,-20(s0) +80001614: f4e7e6e3 bltu a5,a4,80001560 <_vx_e_mat_mult+0x90> +80001618: 00000013 nop +8000161c: 04c12083 lw ra,76(sp) +80001620: 04812403 lw s0,72(sp) +80001624: 05010113 addi sp,sp,80 +80001628: 00008067 ret -80001658 : -80001658: fd010113 addi sp,sp,-48 -8000165c: 02812623 sw s0,44(sp) -80001660: 03010413 addi s0,sp,48 -80001664: fca42e23 sw a0,-36(s0) -80001668: fe042623 sw zero,-20(s0) -8000166c: 0100006f j 8000167c -80001670: fec42783 lw a5,-20(s0) -80001674: 00178793 addi a5,a5,1 -80001678: fef42623 sw a5,-20(s0) -8000167c: fec42703 lw a4,-20(s0) -80001680: fdc42783 lw a5,-36(s0) -80001684: fef746e3 blt a4,a5,80001670 -80001688: 00000013 nop -8000168c: 02c12403 lw s0,44(sp) -80001690: 03010113 addi sp,sp,48 -80001694: 00008067 ret +8000162c : +8000162c: fd010113 addi sp,sp,-48 +80001630: 02812623 sw s0,44(sp) +80001634: 03010413 addi s0,sp,48 +80001638: fca42e23 sw a0,-36(s0) +8000163c: fe042623 sw zero,-20(s0) +80001640: 0100006f j 80001650 +80001644: fec42783 lw a5,-20(s0) +80001648: 00178793 addi a5,a5,1 +8000164c: fef42623 sw a5,-20(s0) +80001650: fec42703 lw a4,-20(s0) +80001654: fdc42783 lw a5,-36(s0) +80001658: fef746e3 blt a4,a5,80001644 +8000165c: 00000013 nop +80001660: 02c12403 lw s0,44(sp) +80001664: 03010113 addi sp,sp,48 +80001668: 00008067 ret -80001698 : -80001698: fd010113 addi sp,sp,-48 -8000169c: 02112623 sw ra,44(sp) -800016a0: 02812423 sw s0,40(sp) -800016a4: 03010413 addi s0,sp,48 -800016a8: fca42e23 sw a0,-36(s0) -800016ac: fcb42c23 sw a1,-40(s0) -800016b0: 810267b7 lui a5,0x81026 -800016b4: 22078713 addi a4,a5,544 # 81026220 -800016b8: fdc42783 lw a5,-36(s0) -800016bc: 00f707b3 add a5,a4,a5 -800016c0: 00100713 li a4,1 -800016c4: 00e78023 sb a4,0(a5) -800016c8: fdc42783 lw a5,-36(s0) -800016cc: 0c079063 bnez a5,8000178c -800016d0: fe0401a3 sb zero,-29(s0) -800016d4: fe042623 sw zero,-20(s0) -800016d8: 0a80006f j 80001780 -800016dc: fe042623 sw zero,-20(s0) -800016e0: fe042423 sw zero,-24(s0) -800016e4: 0340006f j 80001718 -800016e8: 810267b7 lui a5,0x81026 -800016ec: 22078713 addi a4,a5,544 # 81026220 -800016f0: fe842783 lw a5,-24(s0) -800016f4: 00f707b3 add a5,a4,a5 -800016f8: 0007c783 lbu a5,0(a5) -800016fc: 00078863 beqz a5,8000170c -80001700: fec42783 lw a5,-20(s0) -80001704: 00178793 addi a5,a5,1 -80001708: fef42623 sw a5,-20(s0) -8000170c: fe842783 lw a5,-24(s0) -80001710: 00178793 addi a5,a5,1 -80001714: fef42423 sw a5,-24(s0) -80001718: fe842703 lw a4,-24(s0) -8000171c: fd842783 lw a5,-40(s0) -80001720: fcf744e3 blt a4,a5,800016e8 -80001724: fec42703 lw a4,-20(s0) -80001728: fd842783 lw a5,-40(s0) -8000172c: 04f71a63 bne a4,a5,80001780 -80001730: fe042223 sw zero,-28(s0) -80001734: 0400006f j 80001774 -80001738: 810267b7 lui a5,0x81026 -8000173c: 22078713 addi a4,a5,544 # 81026220 -80001740: fe442783 lw a5,-28(s0) -80001744: 00f707b3 add a5,a4,a5 -80001748: 00078023 sb zero,0(a5) -8000174c: 810297b7 lui a5,0x81029 -80001750: 00100713 li a4,1 -80001754: 2ee78423 sb a4,744(a5) # 810292e8 -80001758: 04600513 li a0,70 -8000175c: efdff0ef jal ra,80001658 -80001760: 810297b7 lui a5,0x81029 -80001764: 2e078423 sb zero,744(a5) # 810292e8 -80001768: fe442783 lw a5,-28(s0) -8000176c: 00178793 addi a5,a5,1 -80001770: fef42223 sw a5,-28(s0) -80001774: fe442703 lw a4,-28(s0) -80001778: fd842783 lw a5,-40(s0) -8000177c: faf74ee3 blt a4,a5,80001738 -80001780: fe344783 lbu a5,-29(s0) -80001784: f4079ce3 bnez a5,800016dc -80001788: 0240006f j 800017ac -8000178c: 00000013 nop -80001790: 810297b7 lui a5,0x81029 -80001794: 2e87c783 lbu a5,744(a5) # 810292e8 -80001798: 0017c793 xori a5,a5,1 -8000179c: 0ff7f793 andi a5,a5,255 -800017a0: fe0798e3 bnez a5,80001790 -800017a4: 06400513 li a0,100 -800017a8: eb1ff0ef jal ra,80001658 -800017ac: 00000013 nop -800017b0: 02c12083 lw ra,44(sp) -800017b4: 02812403 lw s0,40(sp) -800017b8: 03010113 addi sp,sp,48 -800017bc: 00008067 ret +8000166c : +8000166c: fd010113 addi sp,sp,-48 +80001670: 02112623 sw ra,44(sp) +80001674: 02812423 sw s0,40(sp) +80001678: 03010413 addi s0,sp,48 +8000167c: fca42e23 sw a0,-36(s0) +80001680: fcb42c23 sw a1,-40(s0) +80001684: 810267b7 lui a5,0x81026 +80001688: 21878713 addi a4,a5,536 # 81026218 +8000168c: fdc42783 lw a5,-36(s0) +80001690: 00f707b3 add a5,a4,a5 +80001694: 00100713 li a4,1 +80001698: 00e78023 sb a4,0(a5) +8000169c: fdc42783 lw a5,-36(s0) +800016a0: 0c079063 bnez a5,80001760 +800016a4: fe0401a3 sb zero,-29(s0) +800016a8: fe042623 sw zero,-20(s0) +800016ac: 0a80006f j 80001754 +800016b0: fe042623 sw zero,-20(s0) +800016b4: fe042423 sw zero,-24(s0) +800016b8: 0340006f j 800016ec +800016bc: 810267b7 lui a5,0x81026 +800016c0: 21878713 addi a4,a5,536 # 81026218 +800016c4: fe842783 lw a5,-24(s0) +800016c8: 00f707b3 add a5,a4,a5 +800016cc: 0007c783 lbu a5,0(a5) +800016d0: 00078863 beqz a5,800016e0 +800016d4: fec42783 lw a5,-20(s0) +800016d8: 00178793 addi a5,a5,1 +800016dc: fef42623 sw a5,-20(s0) +800016e0: fe842783 lw a5,-24(s0) +800016e4: 00178793 addi a5,a5,1 +800016e8: fef42423 sw a5,-24(s0) +800016ec: fe842703 lw a4,-24(s0) +800016f0: fd842783 lw a5,-40(s0) +800016f4: fcf744e3 blt a4,a5,800016bc +800016f8: fec42703 lw a4,-20(s0) +800016fc: fd842783 lw a5,-40(s0) +80001700: 04f71a63 bne a4,a5,80001754 +80001704: fe042223 sw zero,-28(s0) +80001708: 0400006f j 80001748 +8000170c: 810267b7 lui a5,0x81026 +80001710: 21878713 addi a4,a5,536 # 81026218 +80001714: fe442783 lw a5,-28(s0) +80001718: 00f707b3 add a5,a4,a5 +8000171c: 00078023 sb zero,0(a5) +80001720: 810297b7 lui a5,0x81029 +80001724: 00100713 li a4,1 +80001728: 2ee78023 sb a4,736(a5) # 810292e0 +8000172c: 04600513 li a0,70 +80001730: efdff0ef jal ra,8000162c +80001734: 810297b7 lui a5,0x81029 +80001738: 2e078023 sb zero,736(a5) # 810292e0 +8000173c: fe442783 lw a5,-28(s0) +80001740: 00178793 addi a5,a5,1 +80001744: fef42223 sw a5,-28(s0) +80001748: fe442703 lw a4,-28(s0) +8000174c: fd842783 lw a5,-40(s0) +80001750: faf74ee3 blt a4,a5,8000170c +80001754: fe344783 lbu a5,-29(s0) +80001758: f4079ce3 bnez a5,800016b0 +8000175c: 0240006f j 80001780 +80001760: 00000013 nop +80001764: 810297b7 lui a5,0x81029 +80001768: 2e07c783 lbu a5,736(a5) # 810292e0 +8000176c: 0017c793 xori a5,a5,1 +80001770: 0ff7f793 andi a5,a5,255 +80001774: fe0798e3 bnez a5,80001764 +80001778: 06400513 li a0,100 +8000177c: eb1ff0ef jal ra,8000162c +80001780: 00000013 nop +80001784: 02c12083 lw ra,44(sp) +80001788: 02812403 lw s0,40(sp) +8000178c: 03010113 addi sp,sp,48 +80001790: 00008067 ret -800017c0 : -800017c0: fe010113 addi sp,sp,-32 -800017c4: 00812e23 sw s0,28(sp) -800017c8: 02010413 addi s0,sp,32 -800017cc: fe042623 sw zero,-20(s0) -800017d0: 0480006f j 80001818 -800017d4: 810267b7 lui a5,0x81026 -800017d8: fec42703 lw a4,-20(s0) -800017dc: 00271713 slli a4,a4,0x2 -800017e0: 24078793 addi a5,a5,576 # 81026240 -800017e4: 00f707b3 add a5,a4,a5 -800017e8: 00300713 li a4,3 -800017ec: 00e7a023 sw a4,0(a5) -800017f0: 810277b7 lui a5,0x81027 -800017f4: fec42703 lw a4,-20(s0) -800017f8: 00271713 slli a4,a4,0x2 -800017fc: 24078793 addi a5,a5,576 # 81027240 -80001800: 00f707b3 add a5,a4,a5 -80001804: 00200713 li a4,2 -80001808: 00e7a023 sw a4,0(a5) -8000180c: fec42783 lw a5,-20(s0) -80001810: 00178793 addi a5,a5,1 -80001814: fef42623 sw a5,-20(s0) -80001818: fec42703 lw a4,-20(s0) -8000181c: 0ff00793 li a5,255 -80001820: fae7dae3 bge a5,a4,800017d4 -80001824: 00000013 nop -80001828: 01c12403 lw s0,28(sp) -8000182c: 02010113 addi sp,sp,32 -80001830: 00008067 ret +80001794 : +80001794: fe010113 addi sp,sp,-32 +80001798: 00812e23 sw s0,28(sp) +8000179c: 02010413 addi s0,sp,32 +800017a0: fe042623 sw zero,-20(s0) +800017a4: 0480006f j 800017ec +800017a8: 810267b7 lui a5,0x81026 +800017ac: fec42703 lw a4,-20(s0) +800017b0: 00271713 slli a4,a4,0x2 +800017b4: 23878793 addi a5,a5,568 # 81026238 +800017b8: 00f707b3 add a5,a4,a5 +800017bc: 00300713 li a4,3 +800017c0: 00e7a023 sw a4,0(a5) +800017c4: 810277b7 lui a5,0x81027 +800017c8: fec42703 lw a4,-20(s0) +800017cc: 00271713 slli a4,a4,0x2 +800017d0: 23878793 addi a5,a5,568 # 81027238 +800017d4: 00f707b3 add a5,a4,a5 +800017d8: 00200713 li a4,2 +800017dc: 00e7a023 sw a4,0(a5) +800017e0: fec42783 lw a5,-20(s0) +800017e4: 00178793 addi a5,a5,1 +800017e8: fef42623 sw a5,-20(s0) +800017ec: fec42703 lw a4,-20(s0) +800017f0: 0ff00793 li a5,255 +800017f4: fae7dae3 bge a5,a4,800017a8 +800017f8: 00000013 nop +800017fc: 01c12403 lw s0,28(sp) +80001800: 02010113 addi sp,sp,32 +80001804: 00008067 ret -80001834 : -80001834: fd010113 addi sp,sp,-48 -80001838: 02112623 sw ra,44(sp) -8000183c: 02812423 sw s0,40(sp) -80001840: 03010413 addi s0,sp,48 -80001844: fca42e23 sw a0,-36(s0) -80001848: 810007b7 lui a5,0x81000 -8000184c: 12078513 addi a0,a5,288 # 81000120 -80001850: fa5fe0ef jal ra,800007f4 -80001854: fe042623 sw zero,-20(s0) -80001858: 0580006f j 800018b0 -8000185c: fec42783 lw a5,-20(s0) -80001860: 00078e63 beqz a5,8000187c -80001864: fec42783 lw a5,-20(s0) -80001868: 00f7f793 andi a5,a5,15 -8000186c: 00079863 bnez a5,8000187c -80001870: 810007b7 lui a5,0x81000 -80001874: 14478513 addi a0,a5,324 # 81000144 -80001878: f7dfe0ef jal ra,800007f4 -8000187c: fec42783 lw a5,-20(s0) -80001880: 00279793 slli a5,a5,0x2 -80001884: fdc42703 lw a4,-36(s0) -80001888: 00f707b3 add a5,a4,a5 -8000188c: 0007a783 lw a5,0(a5) -80001890: 00078513 mv a0,a5 -80001894: f9dfe0ef jal ra,80000830 -80001898: 810007b7 lui a5,0x81000 -8000189c: 14878513 addi a0,a5,328 # 81000148 -800018a0: f55fe0ef jal ra,800007f4 -800018a4: fec42783 lw a5,-20(s0) -800018a8: 00178793 addi a5,a5,1 -800018ac: fef42623 sw a5,-20(s0) -800018b0: fec42703 lw a4,-20(s0) -800018b4: 0ff00793 li a5,255 -800018b8: fae7d2e3 bge a5,a4,8000185c -800018bc: 810007b7 lui a5,0x81000 -800018c0: 14c78513 addi a0,a5,332 # 8100014c -800018c4: f31fe0ef jal ra,800007f4 -800018c8: 00000013 nop -800018cc: 02c12083 lw ra,44(sp) -800018d0: 02812403 lw s0,40(sp) -800018d4: 03010113 addi sp,sp,48 -800018d8: 00008067 ret +80001808 : +80001808: fd010113 addi sp,sp,-48 +8000180c: 02112623 sw ra,44(sp) +80001810: 02812423 sw s0,40(sp) +80001814: 03010413 addi s0,sp,48 +80001818: fca42e23 sw a0,-36(s0) +8000181c: 810007b7 lui a5,0x81000 +80001820: 11878513 addi a0,a5,280 # 81000118 +80001824: fb5fe0ef jal ra,800007d8 +80001828: fe042623 sw zero,-20(s0) +8000182c: 0580006f j 80001884 +80001830: fec42783 lw a5,-20(s0) +80001834: 00078e63 beqz a5,80001850 +80001838: fec42783 lw a5,-20(s0) +8000183c: 00f7f793 andi a5,a5,15 +80001840: 00079863 bnez a5,80001850 +80001844: 810007b7 lui a5,0x81000 +80001848: 13c78513 addi a0,a5,316 # 8100013c +8000184c: f8dfe0ef jal ra,800007d8 +80001850: fec42783 lw a5,-20(s0) +80001854: 00279793 slli a5,a5,0x2 +80001858: fdc42703 lw a4,-36(s0) +8000185c: 00f707b3 add a5,a4,a5 +80001860: 0007a783 lw a5,0(a5) +80001864: 00078513 mv a0,a5 +80001868: fadfe0ef jal ra,80000814 +8000186c: 810007b7 lui a5,0x81000 +80001870: 14078513 addi a0,a5,320 # 81000140 +80001874: f65fe0ef jal ra,800007d8 +80001878: fec42783 lw a5,-20(s0) +8000187c: 00178793 addi a5,a5,1 +80001880: fef42623 sw a5,-20(s0) +80001884: fec42703 lw a4,-20(s0) +80001888: 0ff00793 li a5,255 +8000188c: fae7d2e3 bge a5,a4,80001830 +80001890: 810007b7 lui a5,0x81000 +80001894: 14478513 addi a0,a5,324 # 81000144 +80001898: f41fe0ef jal ra,800007d8 +8000189c: 00000013 nop +800018a0: 02c12083 lw ra,44(sp) +800018a4: 02812403 lw s0,40(sp) +800018a8: 03010113 addi sp,sp,48 +800018ac: 00008067 ret -800018dc
: -800018dc: ff010113 addi sp,sp,-16 -800018e0: 00112623 sw ra,12(sp) -800018e4: 00812423 sw s0,8(sp) -800018e8: 01010413 addi s0,sp,16 -800018ec: ed5ff0ef jal ra,800017c0 -800018f0: 01000693 li a3,16 -800018f4: 810287b7 lui a5,0x81028 -800018f8: 24078613 addi a2,a5,576 # 81028240 -800018fc: 810277b7 lui a5,0x81027 -80001900: 24078593 addi a1,a5,576 # 81027240 -80001904: 810267b7 lui a5,0x81026 -80001908: 24078513 addi a0,a5,576 # 81026240 -8000190c: 830ff0ef jal ra,8000093c -80001910: 810007b7 lui a5,0x81000 -80001914: 17078513 addi a0,a5,368 # 81000170 -80001918: eddfe0ef jal ra,800007f4 -8000191c: 810287b7 lui a5,0x81028 -80001920: 24078513 addi a0,a5,576 # 81028240 -80001924: f11ff0ef jal ra,80001834 -80001928: 00000793 li a5,0 -8000192c: 00078513 mv a0,a5 -80001930: 00c12083 lw ra,12(sp) -80001934: 00812403 lw s0,8(sp) -80001938: 01010113 addi sp,sp,16 -8000193c: 00008067 ret +800018b0
: +800018b0: ff010113 addi sp,sp,-16 +800018b4: 00112623 sw ra,12(sp) +800018b8: 00812423 sw s0,8(sp) +800018bc: 01010413 addi s0,sp,16 +800018c0: ed5ff0ef jal ra,80001794 +800018c4: 01000693 li a3,16 +800018c8: 810287b7 lui a5,0x81028 +800018cc: 23878613 addi a2,a5,568 # 81028238 +800018d0: 810277b7 lui a5,0x81027 +800018d4: 23878593 addi a1,a5,568 # 81027238 +800018d8: 810267b7 lui a5,0x81026 +800018dc: 23878513 addi a0,a5,568 # 81026238 +800018e0: 840ff0ef jal ra,80000920 +800018e4: 810007b7 lui a5,0x81000 +800018e8: 16878513 addi a0,a5,360 # 81000168 +800018ec: eedfe0ef jal ra,800007d8 +800018f0: 810287b7 lui a5,0x81028 +800018f4: 23878513 addi a0,a5,568 # 81028238 +800018f8: f11ff0ef jal ra,80001808 +800018fc: 00000793 li a5,0 +80001900: 00078513 mv a0,a5 +80001904: 00c12083 lw ra,12(sp) +80001908: 00812403 lw s0,8(sp) +8000190c: 01010113 addi sp,sp,16 +80001910: 00008067 ret Disassembly of section .rodata: @@ -1743,273 +1732,273 @@ Disassembly of section .rodata: 8100002a: 0000 unimp 8100002c: 0062 c.slli zero,0x18 8100002e: 0000 unimp -81000030: 00000063 beqz zero,81000030 +81000030: 00000063 beqz zero,81000030 81000034: 0064 addi s1,sp,12 81000036: 0000 unimp 81000038: 0065 c.nop 25 8100003a: 0000 unimp 8100003c: 0066 c.slli zero,0x19 8100003e: 0000 unimp -81000040: 6552 flw fa0,20(sp) -81000042: 65686373 csrrsi t1,0x656,16 -81000046: 7564 flw fs1,108(a0) -81000048: 656c flw fa1,76(a0) -8100004a: 203a fld ft0,392(sp) -8100004c: 0000 unimp -8100004e: 0000 unimp -81000050: 0030 addi a2,sp,8 -81000052: 0000 unimp -81000054: 0031 c.nop 12 +81000040: 74696177 0x74696177 +81000044: 6620 flw fs0,72(a2) +81000046: 203a726f jal tp,810a7a48 +8100004a: 0000 unimp +8100004c: 6f46 flw ft10,80(sp) +8100004e: 6e75 lui t3,0x1d +81000050: 3a64 fld fs1,240(a2) +81000052: 0020 addi s0,sp,8 +81000054: 0030 addi a2,sp,8 81000056: 0000 unimp -81000058: 0032 c.slli zero,0xc +81000058: 0031 c.nop 12 8100005a: 0000 unimp -8100005c: 00000033 add zero,zero,zero -81000060: 0034 addi a3,sp,8 -81000062: 0000 unimp -81000064: 0035 c.nop 13 +8100005c: 0032 c.slli zero,0xc +8100005e: 0000 unimp +81000060: 00000033 add zero,zero,zero +81000064: 0034 addi a3,sp,8 81000066: 0000 unimp -81000068: 0036 c.slli zero,0xd +81000068: 0035 c.nop 13 8100006a: 0000 unimp -8100006c: 00000037 lui zero,0x0 -81000070: 0038 addi a4,sp,8 -81000072: 0000 unimp -81000074: 0039 c.nop 14 +8100006c: 0036 c.slli zero,0xd +8100006e: 0000 unimp +81000070: 00000037 lui zero,0x0 +81000074: 0038 addi a4,sp,8 81000076: 0000 unimp -81000078: 0061 c.nop 24 +81000078: 0039 c.nop 14 8100007a: 0000 unimp -8100007c: 0062 c.slli zero,0x18 +8100007c: 0061 c.nop 24 8100007e: 0000 unimp -81000080: 00000063 beqz zero,81000080 -81000084: 0064 addi s1,sp,12 -81000086: 0000 unimp -81000088: 0065 c.nop 25 +81000080: 0062 c.slli zero,0x18 +81000082: 0000 unimp +81000084: 00000063 beqz zero,81000084 +81000088: 0064 addi s1,sp,12 8100008a: 0000 unimp -8100008c: 0066 c.slli zero,0x19 +8100008c: 0065 c.nop 25 8100008e: 0000 unimp -81000090: 000a c.slli zero,0x2 +81000090: 0066 c.slli zero,0x19 81000092: 0000 unimp -81000094: 0030 addi a2,sp,8 +81000094: 000a c.slli zero,0x2 81000096: 0000 unimp -81000098: 0031 c.nop 12 +81000098: 0030 addi a2,sp,8 8100009a: 0000 unimp -8100009c: 0032 c.slli zero,0xc +8100009c: 0031 c.nop 12 8100009e: 0000 unimp -810000a0: 00000033 add zero,zero,zero -810000a4: 0034 addi a3,sp,8 -810000a6: 0000 unimp -810000a8: 0035 c.nop 13 +810000a0: 0032 c.slli zero,0xc +810000a2: 0000 unimp +810000a4: 00000033 add zero,zero,zero +810000a8: 0034 addi a3,sp,8 810000aa: 0000 unimp -810000ac: 0036 c.slli zero,0xd +810000ac: 0035 c.nop 13 810000ae: 0000 unimp -810000b0: 00000037 lui zero,0x0 -810000b4: 0038 addi a4,sp,8 -810000b6: 0000 unimp -810000b8: 0039 c.nop 14 +810000b0: 0036 c.slli zero,0xd +810000b2: 0000 unimp +810000b4: 00000037 lui zero,0x0 +810000b8: 0038 addi a4,sp,8 810000ba: 0000 unimp -810000bc: 0061 c.nop 24 +810000bc: 0039 c.nop 14 810000be: 0000 unimp -810000c0: 0062 c.slli zero,0x18 +810000c0: 0061 c.nop 24 810000c2: 0000 unimp -810000c4: 00000063 beqz zero,810000c4 -810000c8: 0064 addi s1,sp,12 -810000ca: 0000 unimp -810000cc: 0065 c.nop 25 +810000c4: 0062 c.slli zero,0x18 +810000c6: 0000 unimp +810000c8: 00000063 beqz zero,810000c8 +810000cc: 0064 addi s1,sp,12 810000ce: 0000 unimp -810000d0: 0066 c.slli zero,0x19 +810000d0: 0065 c.nop 25 810000d2: 0000 unimp -810000d4: 7366664f fnmadd.d fa2,fa2,fs6,fa4,unknown -810000d8: 7465 lui s0,0xffff9 -810000da: 203a fld ft0,392(sp) -810000dc: 0000 unimp +810000d4: 0066 c.slli zero,0x19 +810000d6: 0000 unimp +810000d8: 0030 addi a2,sp,8 +810000da: 0000 unimp +810000dc: 0031 c.nop 12 810000de: 0000 unimp -810000e0: 0030 addi a2,sp,8 +810000e0: 0032 c.slli zero,0xc 810000e2: 0000 unimp -810000e4: 0031 c.nop 12 -810000e6: 0000 unimp -810000e8: 0032 c.slli zero,0xc +810000e4: 00000033 add zero,zero,zero +810000e8: 0034 addi a3,sp,8 810000ea: 0000 unimp -810000ec: 00000033 add zero,zero,zero -810000f0: 0034 addi a3,sp,8 +810000ec: 0035 c.nop 13 +810000ee: 0000 unimp +810000f0: 0036 c.slli zero,0xd 810000f2: 0000 unimp -810000f4: 0035 c.nop 13 -810000f6: 0000 unimp -810000f8: 0036 c.slli zero,0xd +810000f4: 00000037 lui zero,0x0 +810000f8: 0038 addi a4,sp,8 810000fa: 0000 unimp -810000fc: 00000037 lui zero,0x0 -81000100: 0038 addi a4,sp,8 +810000fc: 0039 c.nop 14 +810000fe: 0000 unimp +81000100: 0061 c.nop 24 81000102: 0000 unimp -81000104: 0039 c.nop 14 +81000104: 0062 c.slli zero,0x18 81000106: 0000 unimp -81000108: 0061 c.nop 24 -8100010a: 0000 unimp -8100010c: 0062 c.slli zero,0x18 +81000108: 00000063 beqz zero,81000108 +8100010c: 0064 addi s1,sp,12 8100010e: 0000 unimp -81000110: 00000063 beqz zero,81000110 -81000114: 0064 addi s1,sp,12 +81000110: 0065 c.nop 25 +81000112: 0000 unimp +81000114: 0066 c.slli zero,0x19 81000116: 0000 unimp -81000118: 0065 c.nop 25 -8100011a: 0000 unimp -8100011c: 0066 c.slli zero,0x19 -8100011e: 0000 unimp -81000120: 2d2d jal 8100075a -81000122: 2d2d jal 8100075c -81000124: 2d2d jal 8100075e -81000126: 2d2d jal 81000760 -81000128: 2d2d jal 81000762 -8100012a: 2d2d jal 81000764 -8100012c: 2d2d jal 81000766 -8100012e: 2d2d jal 81000768 -81000130: 2d2d jal 8100076a -81000132: 2d2d jal 8100076c -81000134: 2d2d jal 8100076e -81000136: 2d2d jal 81000770 -81000138: 2d2d jal 81000772 -8100013a: 2d2d jal 81000774 -8100013c: 2d2d jal 81000776 -8100013e: 0a2d addi s4,s4,11 -81000140: 0000 unimp +81000118: 2d2d jal 81000752 +8100011a: 2d2d jal 81000754 +8100011c: 2d2d jal 81000756 +8100011e: 2d2d jal 81000758 +81000120: 2d2d jal 8100075a +81000122: 2d2d jal 8100075c +81000124: 2d2d jal 8100075e +81000126: 2d2d jal 81000760 +81000128: 2d2d jal 81000762 +8100012a: 2d2d jal 81000764 +8100012c: 2d2d jal 81000766 +8100012e: 2d2d jal 81000768 +81000130: 2d2d jal 8100076a +81000132: 2d2d jal 8100076c +81000134: 2d2d jal 8100076e +81000136: 0a2d addi s4,s4,11 +81000138: 0000 unimp +8100013a: 0000 unimp +8100013c: 000a c.slli zero,0x2 +8100013e: 0000 unimp +81000140: 0020 addi s0,sp,8 81000142: 0000 unimp -81000144: 000a c.slli zero,0x2 -81000146: 0000 unimp -81000148: 0020 addi s0,sp,8 -8100014a: 0000 unimp -8100014c: 2d0a fld fs10,128(sp) -8100014e: 2d2d jal 81000788 -81000150: 2d2d jal 8100078a -81000152: 2d2d jal 8100078c -81000154: 2d2d jal 8100078e -81000156: 2d2d jal 81000790 -81000158: 2d2d jal 81000792 -8100015a: 2d2d jal 81000794 -8100015c: 2d2d jal 81000796 -8100015e: 2d2d jal 81000798 -81000160: 2d2d jal 8100079a -81000162: 2d2d jal 8100079c -81000164: 2d2d jal 8100079e -81000166: 2d2d jal 810007a0 -81000168: 2d2d jal 810007a2 -8100016a: 2d2d jal 810007a4 -8100016c: 000a c.slli zero,0x2 -8100016e: 0000 unimp -81000170: 0a0a slli s4,s4,0x2 -81000172: 614d addi sp,sp,176 -81000174: 7274 flw fa3,100(a2) -81000176: 7869 lui a6,0xffffa -81000178: 6d20 flw fs0,88(a0) -8100017a: 6c75 lui s8,0x1d -8100017c: 6974 flw fa3,84(a0) -8100017e: 6c70 flw fa2,92(s0) -81000180: 6369 lui t1,0x1a -81000182: 7461 lui s0,0xffff8 -81000184: 6f69 lui t5,0x1a -81000186: 0a6e slli s4,s4,0x1b +81000144: 2d0a fld fs10,128(sp) +81000146: 2d2d jal 81000780 +81000148: 2d2d jal 81000782 +8100014a: 2d2d jal 81000784 +8100014c: 2d2d jal 81000786 +8100014e: 2d2d jal 81000788 +81000150: 2d2d jal 8100078a +81000152: 2d2d jal 8100078c +81000154: 2d2d jal 8100078e +81000156: 2d2d jal 81000790 +81000158: 2d2d jal 81000792 +8100015a: 2d2d jal 81000794 +8100015c: 2d2d jal 81000796 +8100015e: 2d2d jal 81000798 +81000160: 2d2d jal 8100079a +81000162: 2d2d jal 8100079c +81000164: 000a c.slli zero,0x2 +81000166: 0000 unimp +81000168: 0a0a slli s4,s4,0x2 +8100016a: 614d addi sp,sp,176 +8100016c: 7274 flw fa3,100(a2) +8100016e: 7869 lui a6,0xffffa +81000170: 6d20 flw fs0,88(a0) +81000172: 6c75 lui s8,0x1d +81000174: 6974 flw fa3,84(a0) +81000176: 6c70 flw fa2,92(s0) +81000178: 6369 lui t1,0x1a +8100017a: 7461 lui s0,0xffff8 +8100017c: 6f69 lui t5,0x1a +8100017e: 0a6e slli s4,s4,0x1b ... Disassembly of section .data: -8100018c : -8100018c: 0000 unimp +81000184 : +81000184: 0000 unimp +81000186: 8100 0x8100 +81000188: 0004 0x4 +8100018a: 8100 0x8100 +8100018c: 0008 0x8 8100018e: 8100 0x8100 -81000190: 0004 0x4 +81000190: 000c 0xc 81000192: 8100 0x8100 -81000194: 0008 0x8 +81000194: 0010 0x10 81000196: 8100 0x8100 -81000198: 000c 0xc +81000198: 0014 0x14 8100019a: 8100 0x8100 -8100019c: 0010 0x10 +8100019c: 0018 0x18 8100019e: 8100 0x8100 -810001a0: 0014 0x14 +810001a0: 001c 0x1c 810001a2: 8100 0x8100 -810001a4: 0018 0x18 +810001a4: 0020 addi s0,sp,8 810001a6: 8100 0x8100 -810001a8: 001c 0x1c +810001a8: 0024 addi s1,sp,8 810001aa: 8100 0x8100 -810001ac: 0020 addi s0,sp,8 +810001ac: 0028 addi a0,sp,8 810001ae: 8100 0x8100 -810001b0: 0024 addi s1,sp,8 +810001b0: 002c addi a1,sp,8 810001b2: 8100 0x8100 -810001b4: 0028 addi a0,sp,8 +810001b4: 0030 addi a2,sp,8 810001b6: 8100 0x8100 -810001b8: 002c addi a1,sp,8 +810001b8: 0034 addi a3,sp,8 810001ba: 8100 0x8100 -810001bc: 0030 addi a2,sp,8 +810001bc: 0038 addi a4,sp,8 810001be: 8100 0x8100 -810001c0: 0034 addi a3,sp,8 +810001c0: 003c addi a5,sp,8 810001c2: 8100 0x8100 -810001c4: 0038 addi a4,sp,8 + +810001c4 : +810001c4: 0054 addi a3,sp,4 810001c6: 8100 0x8100 -810001c8: 003c addi a5,sp,8 +810001c8: 0058 addi a4,sp,4 810001ca: 8100 0x8100 - -810001cc : -810001cc: 0050 addi a2,sp,4 +810001cc: 005c addi a5,sp,4 810001ce: 8100 0x8100 -810001d0: 0054 addi a3,sp,4 +810001d0: 0060 addi s0,sp,12 810001d2: 8100 0x8100 -810001d4: 0058 addi a4,sp,4 +810001d4: 0064 addi s1,sp,12 810001d6: 8100 0x8100 -810001d8: 005c addi a5,sp,4 +810001d8: 0068 addi a0,sp,12 810001da: 8100 0x8100 -810001dc: 0060 addi s0,sp,12 +810001dc: 006c addi a1,sp,12 810001de: 8100 0x8100 -810001e0: 0064 addi s1,sp,12 +810001e0: 0070 addi a2,sp,12 810001e2: 8100 0x8100 -810001e4: 0068 addi a0,sp,12 +810001e4: 0074 addi a3,sp,12 810001e6: 8100 0x8100 -810001e8: 006c addi a1,sp,12 +810001e8: 0078 addi a4,sp,12 810001ea: 8100 0x8100 -810001ec: 0070 addi a2,sp,12 +810001ec: 007c addi a5,sp,12 810001ee: 8100 0x8100 -810001f0: 0074 addi a3,sp,12 +810001f0: 0080 addi s0,sp,64 810001f2: 8100 0x8100 -810001f4: 0078 addi a4,sp,12 +810001f4: 0084 addi s1,sp,64 810001f6: 8100 0x8100 -810001f8: 007c addi a5,sp,12 +810001f8: 0088 addi a0,sp,64 810001fa: 8100 0x8100 -810001fc: 0080 addi s0,sp,64 +810001fc: 008c addi a1,sp,64 810001fe: 8100 0x8100 -81000200: 0084 addi s1,sp,64 +81000200: 0090 addi a2,sp,64 81000202: 8100 0x8100 -81000204: 0088 addi a0,sp,64 + +81000204 : +81000204: 0098 addi a4,sp,64 81000206: 8100 0x8100 -81000208: 008c addi a1,sp,64 +81000208: 009c addi a5,sp,64 8100020a: 8100 0x8100 - -8100020c : -8100020c: 0094 addi a3,sp,64 +8100020c: 00a0 addi s0,sp,72 8100020e: 8100 0x8100 -81000210: 0098 addi a4,sp,64 +81000210: 00a4 addi s1,sp,72 81000212: 8100 0x8100 -81000214: 009c addi a5,sp,64 +81000214: 00a8 addi a0,sp,72 81000216: 8100 0x8100 -81000218: 00a0 addi s0,sp,72 +81000218: 00ac addi a1,sp,72 8100021a: 8100 0x8100 -8100021c: 00a4 addi s1,sp,72 +8100021c: 00b0 addi a2,sp,72 8100021e: 8100 0x8100 -81000220: 00a8 addi a0,sp,72 +81000220: 00b4 addi a3,sp,72 81000222: 8100 0x8100 -81000224: 00ac addi a1,sp,72 +81000224: 00b8 addi a4,sp,72 81000226: 8100 0x8100 -81000228: 00b0 addi a2,sp,72 +81000228: 00bc addi a5,sp,72 8100022a: 8100 0x8100 -8100022c: 00b4 addi a3,sp,72 +8100022c: 00c0 addi s0,sp,68 8100022e: 8100 0x8100 -81000230: 00b8 addi a4,sp,72 +81000230: 00c4 addi s1,sp,68 81000232: 8100 0x8100 -81000234: 00bc addi a5,sp,72 +81000234: 00c8 addi a0,sp,68 81000236: 8100 0x8100 -81000238: 00c0 addi s0,sp,68 +81000238: 00cc addi a1,sp,68 8100023a: 8100 0x8100 -8100023c: 00c4 addi s1,sp,68 +8100023c: 00d0 addi a2,sp,68 8100023e: 8100 0x8100 -81000240: 00c8 addi a0,sp,68 +81000240: 00d4 addi a3,sp,68 81000242: 8100 0x8100 -81000244: 00cc addi a1,sp,68 -81000246: 8100 0x8100 -81000248: 00d0 addi a2,sp,68 -8100024a: 8100 0x8100 -8100024c : +81000244 : +81000244: 00d8 addi a4,sp,68 +81000246: 8100 0x8100 +81000248: 00dc addi a5,sp,68 +8100024a: 8100 0x8100 8100024c: 00e0 addi s0,sp,76 8100024e: 8100 0x8100 81000250: 00e4 addi s1,sp,76 @@ -2038,64 +2027,60 @@ Disassembly of section .data: 8100027e: 8100 0x8100 81000280: 0114 addi a3,sp,128 81000282: 8100 0x8100 -81000284: 0118 addi a4,sp,128 -81000286: 8100 0x8100 -81000288: 011c addi a5,sp,128 -8100028a: 8100 0x8100 Disassembly of section .bss: -8100028c : +81000284 : ... -81000330 : -81000330: 0000 unimp +81000328 : +81000328: 0000 unimp ... -81000334 : +8100032c : ... -81000434 : +8100042c : ... -81026134 : +8102612c : ... -810261d8 : -810261d8: 0000 unimp +810261d0 : +810261d0: 0000 unimp ... -810261dc : +810261d4 : ... -810261f0 : +810261e8 : ... -81026208 : +81026200 : ... -81026220 : +81026218 : ... -81026240 : +81026238 : ... -81027240 : +81027238 : ... -81028240 : +81028238 : ... -81029240 : +81029238 : ... -810292e4 : -810292e4: 0000 unimp +810292dc : +810292dc: 0000 unimp ... Disassembly of section .sbss: -810292e8 : +810292e0 : ... Disassembly of section .comment: diff --git a/kernel/vortex_test.elf b/kernel/vortex_test.elf index 38dd847fc6e722c71faed7e6ad40b7c532811721..f2b2353a8b06bc096bfc68c0e752d96ae9b5705f 100755 GIT binary patch delta 2620 zcmb`JdrVVz6vxlKeO%mzJX%UY?ZewrR8+tU6$qKRw&7Tz0QTP6PD^IabFdLmvk|U8VytP>qk%joQ17 z(64z1ucT)gq)nVZiW+V*rW;r4cxDirbPJffctSUS(k-4+cp)D9Lr#rnb%se3r&dI8 zJ26SmGv8yL-kk9raxB!haq2im>p(>q`dzp|Z_tXjun_l>>m}^c7i)eBM@DYqu)c08 zYH&iqm4)jw8p>Pj!Du2Brw)UADebw+Te@R>jyl!|f)=?{;B)T9c$=vERidxT;g3yr zU@T)^xu}tgFk?fZ35pk!&?p`(QaOUL7Dq5Tmi^!%KQ|teO~mj_#^^0I@GMh}UZa=B z%f@;d`K*fKPeQZ%-ei5$=Q)%i%6}9BS$m>+2q{aod6FIenQR=nhnOx7htLm0caB&1V_`o?ur;CHv`cWH5%2*@l_k3)Brr zET8Pf+U&*5<=#WtolI4C$dt$)Fipo6wGvy@!3hyt_NOw4HXLckVw;OGVUumvGE)L{ zU{D5akIJ9{g*`ZtAZmXUj;y&J2OVjXL8&?8wneP@2zusRWVtbP^Eo)zc=>JjBUw;BU*{A4#Ao??L`oTLgeaf9UeaasR`s6tM*A}8rj??cp zd8)fYmP9i-%k<`pTG@P2E1NIssphv4e-XoBqit3RXOY^^D+*A&CrbNN0jI;G-p7do z6z@sOg+u}UXtaOD6cPVRY@mqPOL2go|5VsVy(3Rx=T^z=YXrIZlkB2hVjuO!!lULN zfoFX}^#mVi+NE1Sfbeaun zI#R-Y$5|*Iu2}&nIfIpnOS{q2CCO*RTxpTDx zy71`8L)@D?tKeVhu+o$9?-tsEfz0>;C2prfC}r$gNb;#BAM-t|HDu$jxyJbcUd)26 zG}Eb~qd6Q&@h8Fs43yxnzCdEV*EVlh+u4zKINzwY-h&w8TTCm5J2^=B7{#;X7&b4YKRwS`8JX$4MI{y^1u{$@&%C z?$i~y4o}Z8Oj?=2qsUN45!R!9sd-6CdZeR;bmE~EmaQA0Xt{Ro}gJ1L!L zf069!G!R^pe;3Vp1`ynm{S;}-3=nLR{WF?Rq=2wl(pPBSt4*|4jCYLz{AQ`unv^83 zJtm)REC|C=OdaLiiJBtwx?AK`BdwOu>Nd)pD@Cp#U6u|)t)$nI?vWmcnCW%WuKjXl z8%XQ1xoGjeJbD4hAzm-N9B@mqtBl^H;IneQon%i^*cXsKYXqS|q7rA<4mrz7vKy(N z7Frkk*+Y7io(iQSt$~XSu+V_^Vsk-I5%xB@9a89V(w=8P5TxSnlg`8DV)MEN4G0km zCYER-*de{#f`z2J6wNLrJ@K6UFsex>5qyud-%R>A{$A|XzPi;}+4M3laQU?FZm#hx ze+$pM)@oNYHCI+{?@d~EiDmToZK;Ft;h&{ujh{YueoQOl#ovB(w~X$@BK^3r%)$8a TJsOYWIU2|DXBx|pc|P+$LQfjd delta 2714 zcmb_eeM}Q)7=Q0*doW>zwm^}OD_o(SZc9xXdiuFdK2qEc-%XA8umS441j#*Af?5XyRBk(X`7nIMdcWZ+mcO!hhRKxc7eV z^YQ+E&vW-)`?eq4-e+NU_ZJFUF^3Sb|FK-Hk0s>l=P!JvXU{AEYx)SwmcV5C8!Vd- zof$ve>#iH-W{7boM?z$5C5Q&m1Y8;cTo~nu2MwAK5!*pZ&x5}7RQykYorcU}bsSj( zoR+li2901ia&L!eG`-cabseR`3{dvg9DHHws#AcGHI-)hIAOfy20%nTB=7 zMYC>kPGW65_uHHXx{X=0CQhTuK+541X7~}V8Trgpz_FxtH>XLkch`l8Q~?%KmX6+z zErJ@8zms5SXBf!LX2xMO z^S;s^TW>7Mrion+1S3f{f2_ymk6t#-+!l(cx5QEsNj6u^n5f4vpCzyuT4!#;>j&mm zh665VMdc^KywT@b4^}Kc$<`Yc-VYK5yQ0FN8f&7$;UEcxn|6Ve(~#_6 zN}xX`3 zT+HW+wcf(q#jcE4C_HcsTa17vnmP)Og{91Q!_5o(8TU}IAi;;@?-oX}S{TLt2o
  • ik}Xdea^_ zZe7Ci0N1Q$aOA(oj!(mx{AXD1PiPhjp}xTNKMDGD9zhY6pbPT|Li?Pcb13NW{DSlW zMNq?3T#){%B1jM278H~&3wmUwB~fp$i$qX*Popzr-JobpgS*jy+v+N ziAs;^;qt2Nb9#nCfr0rRE^Lr~M5X6gLeB}*^EJyY!{(I0FU4u#7P49QGSt-O9t{3> zMS+3Ic@&K|D2n!Zln%`*qIOwPVBk(D&~$$O4o&zJMS349DrMe`3v#!}f~>5!1;tcD zY00xJR|LM23Oe~q*4VkC9(?!cku6AgLchg&j9fYqdV@=h+GY*Dej&Oh^ultRgYm*< z+o}T28b9GV2N4e8>-7qYCz4-2kvJ<{u&vQ?2Bdo%?Dis^+Y|~+%|N3)H|?LqvEs#* zrkfD3Wy0(B6x}#N{%;Vo7Q%?#yoj^XjQF{*(gz7Y7gp?9Pa=}b#$4A&y@~bVTlPua zeutR)c-z+2j<$_2ceX9JK%~?K2OO^ChW7TYZQJApbJ@pCBb+R&WexySUJI+stF&f@ zc=EtgzN*lNcLYZg{?UP7I2mi=_zGMv-&aUi2N5$wLte$%kwiSyPBC@&!MhLEmgR9o zLV$xIzv8t+g)br=Q{hX9Cn3$r8%VMeRlpEpN`{A>1alO5`dP5aegHKO* zfugq`?N*h2G2%%xkv7V#=q$dZ>@t9M3)a(u>$ILjh_7H*a680WGQtp+^g(_lUlvfM zy@YNwL1Iyz50cQq`#2P`|0ZZNnGKjio%SY1y diff --git a/kernel/vortex_test.hex b/kernel/vortex_test.hex index 26fccb24..f6f9e8b6 100644 --- a/kernel/vortex_test.hex +++ b/kernel/vortex_test.hex @@ -1,7 +1,7 @@ :0200000480007A :1000000013058000731005021305400073101502DC :10001000731040F17310103037F1FF7FEF00801E36 -:10002000EF10D00B73000000938B0600130D070038 +:10002000EF10100973000000938B0600130D0700FA :10003000130F01009303050013051000635C7500A6 :1000400013010180130305006B5003001305150015 :100050006FF0DFFE1300000013000000130000002B @@ -12,7 +12,7 @@ :1000A0001300000013000000130000001300000004 :1000B0001300000013000000170500001305451B86 :1000C0006B40050017030000130343F66B000300A9 -:1000D000678000001702000113020226232002009D +:1000D000678000001702000113028225232002001E :1000E0002322120023242200232632002328420048 :1000F000232A5200232C6200232E72002320820226 :10010000232292022324A2022326B2022328C2021F @@ -21,7 +21,7 @@ :10013000232A5205232C6205232E720523208207D1 :10014000232292072324A2072326B2072328C207CB :10015000232AD207232CE207232EF20713021000D2 -:1001600067800000170200011302021D0320020035 +:1001600067800000170200011302821C03200200B6 :1001700083204200032182008321C2000322020166 :1001800083224201032382018323C201032402024A :1001900083244202032582028325C202032602032E @@ -34,416 +34,414 @@ :1002000067800000130101FE232E1100232C8100C2 :1002100013040102232604FE6F0040030327C4FEDB :10022000B7170000938747973307F702B707008196 -:1002300093874743B307F70013850700EF00C045D6 +:100230009387C742B307F70013850700EF00004418 :100240008327C4FE938717002326F4FE0327C4FEEA :100250009307F001E3D4E7FC130000008320C10101 :10026000032481011301010267800000130101FDD5 :1002700023261102232481022322A1031304010354 -:1002800093070D0093850700B707008113850704C6 -:10029000EF00406613000000130000001300000090 -:1002A0001300000013000000130000001300000002 -:1002B00013000000130000001300000013000000F2 -:1002C0001300000013070D00B7170000938747972E -:1002D0003307F702B707008193874743B307F70057 -:1002E00013850700EF00004E93070500638A07029D -:1002F00013070D00B7070081131727009387C7283E -:10030000B307F7001307100023A0E70093070D00C1 -:1003100063960700EFF01FE56F00C0057300000053 -:1003200013070D00B7170000938747973307F702AD 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b/kernel/vx_include/vx_front.c index 33fdf8fd..082cbd41 100644 --- a/kernel/vx_include/vx_front.c +++ b/kernel/vx_include/vx_front.c @@ -23,7 +23,7 @@ void vx_sq_mat_mult(void * x, void * y, void * z, unsigned mat_dim) off += 1; } - vx_printf("Offset: ", off); + // vx_printf("Offset: ", off); mat_mult_args.offset = off; diff --git a/kernel/vx_os/vx_back/vx_back.c b/kernel/vx_os/vx_back/vx_back.c index 2217d26b..e7288aba 100644 --- a/kernel/vx_os/vx_back/vx_back.c +++ b/kernel/vx_os/vx_back/vx_back.c @@ -16,18 +16,7 @@ void vx_reschedule_warps() { register unsigned curr_warp asm("s10"); - vx_printf("Reschedule: ", curr_warp); - asm __volatile__("nop"); - asm __volatile__("nop"); - asm __volatile__("nop"); - asm __volatile__("nop"); - asm __volatile__("nop"); - asm __volatile__("nop"); - asm __volatile__("nop"); - asm __volatile__("nop"); - asm __volatile__("nop"); - asm __volatile__("nop"); - asm __volatile__("nop"); + // vx_printf("Reschedule: ", curr_warp); asm __volatile__("nop"); if (queue_isEmpty(q+curr_warp)) @@ -131,20 +120,20 @@ void vx_spawnWarps(unsigned num_Warps, unsigned num_threads, FUNC, void * args) void vx_wait_for_warps(unsigned num_wait) { - // vx_printf("wait for: ", num_wait); + vx_printf("wait for: ", num_wait); unsigned num_available_warps = vx_available_warps(); unsigned num = 0; while (num != num_wait) { - num = 0; - for (int i = 0; i < num_available_warps; i++) + num = 1; + for (int i = 0; i < 32; i++) { if (done[i] == 1) { num += 1; } } - // vx_printf("Found: ", num); + vx_printf("Found: ", num); } // vx_printf("num found: ", num); diff --git a/rtl/.DS_Store b/rtl/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..dc18f1dfad92c3e8c6cda286c951ef491e6a83b7 GIT binary patch literal 8196 zcmeHMy>1jS5FRH%93+H*B9V?uM-_<@(VU`CP*5SEbm4wU;Qn%dIl61|4v074WsrCa z8Y&(jeBao6^4hznR0&dSX?ON^=bIUSGqz(#M9kr|^-^R{L@Kx_cQ$b=X#CDAYHRMz zKBNI&q$vaG%UC9I5NW3uiGjpGVjwY)7)T8K4-8<>0 zH76HV>ePXoZUG=S@LC(5u@6v8)ybNZ3o8{0n|AkL9MrfihOuybuTmYd=H$Xk3m0SI zVw`8=b|^-@16NgbF*PgGJu#3Nh#A<&t4G+kcjb$m4V@QO9Zw?naX!$H&+ycO{wUD?5oq6&5v=!cmT;Qa zG|vLfO=z}p?l46R6UYPH=Q0UUmjUVtG}}PV5D)R^kY_l*=pf2M3-VKBeb?*HHvG`< z1jq)S`e5)B*rp6+7u@<^KnlLaVN+^7rtk( z6Z>Z7eH%MV8)Gnef}GWnyA~@LzaucnwsT6|kE_Wj$lBdMkQHM&<>KFpKQlRO>V98>^-e*MTpxS;C}p z;`?Jov)VfFHgTga>>C;JF^`uRj-LzUe5CVGzbJQx%=qYx8M1Ow9;w#KZ;zQQ=RHK) z(~E^9D{-9;U+ zlI;B7R3 New num_ecalls = %h", num_ecalls+1); - end - end + // always @(posedge clk) begin + // if (in_ebreak) begin + // num_ecalls <= num_ecalls + 1; + // $display("--------> New num_ecalls = %h", num_ecalls+1); + // end + // end wire add_warp = in_wspawn && !in_ebreak && !in_clone_stall; wire remove_warp = in_ebreak && !in_wspawn && !in_clone_stall; @@ -65,7 +65,7 @@ module VX_fetch ( warp_num <= 0; `ifndef ONLY end else if (!warp_glob_valid[warp_num+1]) begin - $display("Skipping one"); + // $display("Skipping one"); warp_num <= warp_num + 2; `endif end else begin @@ -75,12 +75,12 @@ module VX_fetch ( if (add_warp) begin warp_state <= warp_state + 1; warp_count <= warp_count + 1; - $display("Adding a new warp %h", warp_state+1); + // $display("Adding a new warp %h", warp_state+1); end else if (remove_warp) begin // No removing, just invalidating warp_count <= warp_count - 1; - $display("Removing a warp %h %h", in_decode_warp_num, warp_count); + // $display("Removing a warp %h %h", in_decode_warp_num, warp_count); if (warp_count == 2) begin - $display("&&&&&&&&&&&&& STATE 0"); + // $display("&&&&&&&&&&&&& STATE 0"); warp_state <= 0; end end @@ -103,9 +103,9 @@ module VX_fetch ( wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc; wire warp_zero_remove = remove_warp && (in_decode_warp_num == 0); - always @(*) begin : proc_ - if (warp_zero_remove) $display("4Removing warp: %h", 0); - end + // always @(*) begin : proc_ + // if (warp_zero_remove) $display("4Removing warp: %h", 0); + // end VX_warp VX_Warp( .clk (clk), @@ -140,9 +140,9 @@ module VX_fetch ( wire[31:0] warp_zero_wspawn_pc = in_wspawn_pc; wire warp_zero_remove = remove_warp && (in_decode_warp_num == cur_warp); - always @(*) begin : proc_ - if (warp_zero_remove) $display("4Removing warp: %h", cur_warp); - end + // always @(*) begin : proc_ + // if (warp_zero_remove) $display("4Removing warp: %h", cur_warp); + // end VX_warp VX_Warp( .clk (clk), @@ -184,11 +184,11 @@ module VX_fetch ( assign out_PC = out_PC_var; assign out_valid = out_valid_var; - always @(*) begin - if (out_valid[0]) begin - $display("[%d] %h #%b#",out_warp_num, out_PC, out_valid); - end - end + // always @(*) begin + // if (out_valid[0]) begin + // $display("[%d] %h #%b#",out_warp_num, out_PC, out_valid); + // end + // end `endif diff --git a/rtl/VX_shared_memory.v b/rtl/VX_shared_memory.v index c3e949b5..9340a973 100644 --- a/rtl/VX_shared_memory.v +++ b/rtl/VX_shared_memory.v @@ -1,7 +1,7 @@ `include "VX_define.v" - +// Old SM file module VX_shared_memory( input wire clk, diff --git a/rtl/Vortex.qpf b/rtl/Vortex.qpf new file mode 100644 index 00000000..de9229d9 --- /dev/null +++ b/rtl/Vortex.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition +# Date created = 20:33:29 May 12, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.0" +DATE = "20:33:29 May 12, 2019" + +# Revisions + +PROJECT_REVISION = "Vortex" diff --git a/rtl/Vortex.qsf b/rtl/Vortex.qsf new file mode 100644 index 00000000..638a44b5 --- /dev/null +++ b/rtl/Vortex.qsf @@ -0,0 +1,47 @@ +set_global_assignment -name FAMILY "Arria 10" +set_global_assignment -name TOP_LEVEL_ENTITY Vortex +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:33:29 MAY 12, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Pro Edition" +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/Vortex.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_alu.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_context.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_context_slave.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_csr_handler.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_d_e_reg.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_decode.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_define.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_e_m_reg.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_execute.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_f_d_reg.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_fetch.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_forwarding.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_m_w_reg.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_memory.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_register_file.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_register_file_master_slave.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_register_file_slave.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_warp.v +set_global_assignment -name VERILOG_FILE ../../Users/fsabbaghgt/Documents/GitHub/Vortex/rtl/VX_writeback.v +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name DEVICE 10AX115U3F45I2SG +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name POWER_AUTO_COMPUTE_TJ ON +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 50000 +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SDC_FILE clk_const.sdc +set_global_assignment -name ALLOW_REGISTER_RETIMING OFF +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF +set_global_assignment -name AUTO_ROM_RECOGNITION OFF +set_global_assignment -name AUTO_RAM_RECOGNITION OFF +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS ON +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF +set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON +set_instance_assignment -name PARTITION_COLOUR 4288217044 -to Vortex -entity Vortex diff --git a/rtl/clk_const.sdc b/rtl/clk_const.sdc new file mode 100644 index 00000000..9e9cfa24 --- /dev/null +++ b/rtl/clk_const.sdc @@ -0,0 +1 @@ +create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] \ No newline at end of file diff --git a/rtl/obj_dir/VVortex b/rtl/obj_dir/VVortex new file mode 100755 index 0000000000000000000000000000000000000000..17b723b288f9d7cb7721e12208d53887ac71fd33 GIT binary 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z14<907{~{|eI5eFUw(W4eyDTU(cA_3d9AbfQ73-XiyvJ@kJ|0%QRgCh)NRF&;u*W= z@ms=Jm(g1nF%YeG3~Q?s&)Mop&tgDY7t*sBl-8vHOT377H(Ep|-jz*vJ)>#a2>nw)2bryr% zIul@S2|L;n<`DL@)t259=Isi2=?e39h4l(-)9MQA?Mm|s>+K11^n~$x!nfzbvkPHu z7s8%PTznzWfk51?3jscX{@MclwFSCr3pCUgXsF$e*U=V4V!Iu$qb+cEM-&3_9GzZF zSDo{C-#UV9=v>Bp)D>vF+llF~+llAx3bfnp#_R2Ng?YO%y>xpqy>tZ{>Rt%nUd6cT z3UttG#qaf6F%9(uEz;}6eAE-x+Y{E-yAZw=G)C_--pk%)yx!hbyhrDPMmxWZ=RLoQ z@q8iR`9i?yg`g)c1VwRi731_$Fh4E@p1Blw;Zo4xmjdoD1zNil8DWWbwd{BN zx|lA$d{jI(>vtf=G@TMBFVILBbUIwmpSPpU(-v?kih-z7FMYmp@c2{G~Squuxm4eO@<<(FUn4>~lB;Q#;t literal 0 HcmV?d00001 diff --git a/rtl/obj_dir/VVortex.cpp b/rtl/obj_dir/VVortex.cpp new file mode 100644 index 00000000..d9bec965 --- /dev/null +++ b/rtl/obj_dir/VVortex.cpp @@ -0,0 +1,14783 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See VVortex.h for the primary calling header + +#include "VVortex.h" +#include "VVortex__Syms.h" + + +//-------------------- +// STATIC VARIABLES + +// Begin mtask footprint all: +VL_ST_SIG8(VVortex::__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0); + +//-------------------- + +VL_CTOR_IMP(VVortex) { + VVortex__Syms* __restrict vlSymsp = __VlSymsp = new VVortex__Syms(this, name()); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + VL_CELL(__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one, VVortex_VX_context_slave); + VL_CELL(__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one, VVortex_VX_context_slave); + VL_CELL(__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one, VVortex_VX_context_slave); + VL_CELL(__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one, VVortex_VX_context_slave); + VL_CELL(__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one, VVortex_VX_context_slave); + VL_CELL(__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one, VVortex_VX_context_slave); + VL_CELL(__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one, VVortex_VX_context_slave); + // Reset internal values + + // Reset structure values + _ctor_var_reset(); +} + +void VVortex::__Vconfigure(VVortex__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +VVortex::~VVortex() { + delete __VlSymsp; __VlSymsp=NULL; +} + +//-------------------- + + +void VVortex::eval() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVortex::eval\n"); ); + VVortex__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +#ifdef VL_DEBUG + // Debug assertions + _eval_debug_assertions(); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +void VVortex::_eval_initial_loop(VVortex__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + _eval_initial(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + _eval_settle(vlSymsp); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +//-------------------- +// Internal Methods + +void VVortex::_initial__TOP__1(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_initial__TOP__1\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // INITIAL at VX_warp.v:30 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__real_PC = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[0U] = 1U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero[0U] = 0U; + // INITIAL at VX_warp.v:30 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__real_PC = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[0U] = 1U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero[0U] = 0U; + // INITIAL at VX_warp.v:30 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__real_PC = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[0U] = 1U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero[0U] = 0U; + // INITIAL at VX_warp.v:30 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__real_PC = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[0U] = 1U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero[0U] = 0U; + // INITIAL at VX_warp.v:30 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__real_PC = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[0U] = 1U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero[0U] = 0U; + // INITIAL at VX_warp.v:30 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__real_PC = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[0U] = 1U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero[0U] = 0U; + // INITIAL at VX_warp.v:30 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__real_PC = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[0U] = 1U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero[0U] = 0U; + // INITIAL at VX_warp.v:30 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__real_PC = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero[1U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero[2U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero[3U] = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[0U] = 1U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero[0U] = 0U; + // INITIAL at VX_context.v:31 + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall = 0U; + // INITIAL at VX_m_w_reg.v:41 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = 0U; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = 0U; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = 0U; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num = 0U; + // INITIAL at VX_csr_handler.v:29 + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle = VL_ULL(0); + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret = VL_ULL(0); + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address = 0U; + // INITIAL at VX_e_m_reg.v:79 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read = 7U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write = 7U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__is_csr = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_result = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[0U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[0U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[0U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[2U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[2U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[2U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[2U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[3U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[3U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[3U] = 0U; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[3U] = 0U; + // INITIAL at VX_d_e_reg.v:87 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[0U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[0U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[0U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[0U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[1U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[2U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[2U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[2U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[2U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[2U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[3U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[3U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[3U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[3U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[3U] = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read = 7U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write = 7U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__is_csr = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset = 0U; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num = 0U; + // INITIAL at VX_fetch.v:45 + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state = 0U; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_count = 1U; +} + +void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_settle__TOP__2\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[0U] = 1U; + vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[1U] = 0U; + vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[2U] = 0U; + vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[3U] = 0U; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[3U] + = vlTOPp->in_cache_driver_out_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2U] + = vlTOPp->in_cache_driver_out_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1U] + = vlTOPp->in_cache_driver_out_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] + = vlTOPp->in_cache_driver_out_data[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[3U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data; + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[3U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[3U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[3U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype = + ((0x13U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + | (3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))); + vlTOPp->Vortex__DOT__decode_csr_address = (0xfffU + & (((0U + != + (7U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU))) + & (2U + <= + (0xfffU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))) + ? + (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U) + : 0x55U)); + // ALWAYS at VX_decode.v:577 + vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)); + vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = + vlTOPp->__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu + [vlTOPp->__Vtableidx1]; + vlTOPp->Vortex__DOT__vx_decode__DOT__alu_tempp + = (0xfffU & (((1U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU))) | (5U + == + (7U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)))) + ? (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)) : (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))); + vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr = ( + (0x73U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & (0U + != + (7U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__jal_sys_jal + = ((0U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU))) & (2U > (0xfffU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt = + ((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & (4U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn + = ((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & (0U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone = + ((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & (5U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs = + ((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & (6U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)))); + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[2U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[3U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[3U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U + == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) + ? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle) + : + ((0xc80U + == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) + ? (IData)( + (vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle + >> 0x20U)) + : + ((0xc02U + == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) + ? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret) + : + ((0xc82U + == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) + ? (IData)( + (vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret + >> 0x20U)) + : + ((0x400U + >= + (0x7ffU + & (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address))) + ? + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr + [ + (0x7ffU + & (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address))] + : 0U))))); + vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read; + vlTOPp->out_cache_driver_in_mem_write = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write; + vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset + << 1U)); + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[3U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [0U]; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[3U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[3U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[3U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [0U]; + vlTOPp->Vortex__DOT__execute_branch_stall = ((0U + != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) + | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal)); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[3U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd + = (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))) + & ((IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num) + == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd + = (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))) & (0U + != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))) + & ((IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num) + == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [0U]; + vlTOPp->Vortex__DOT__m_w_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [3U]; + vlTOPp->Vortex__DOT__m_w_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [2U]; + vlTOPp->Vortex__DOT__m_w_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__m_w_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [0U]; + vlTOPp->Vortex__DOT__f_d_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [3U]; + vlTOPp->Vortex__DOT__f_d_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [2U]; + vlTOPp->Vortex__DOT__f_d_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0U]; + vlTOPp->Vortex__DOT__m_w_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [3U]; + vlTOPp->Vortex__DOT__m_w_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [2U]; + vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [0U]; + vlTOPp->Vortex__DOT__m_w_mem_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [3U]; + vlTOPp->Vortex__DOT__m_w_mem_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [2U]; + vlTOPp->Vortex__DOT__m_w_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [1U]; + vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [0U]; + // ALWAYS at VX_decode.v:508 + vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ( + (0x20U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0x10U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((8U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((4U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((2U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((1U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x1fU)))) + << 0xcU)) + | ((0x800U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)) + | ((0x400U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + << 3U)) + | ((0x3f0U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x15U)) + | (0xfU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 8U)))))) + : 0xdeadbeefU) + : 0xdeadbeefU)))) + : 0xdeadbeefU) + : ( + (0x20U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0x10U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((8U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((4U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((2U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((1U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x1fU)))) + << 0xcU)) + | ((0xfe0U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)) + | (0x1fU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 7U)))) + : 0xdeadbeefU) + : 0xdeadbeefU)))) + : + ((0x10U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((8U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((4U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((2U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((1U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__alu_tempp) + >> 0xbU)))) + << 0xcU)) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__alu_tempp)) + : 0xdeadbeefU) + : 0xdeadbeefU))) + : + ((8U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((4U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((2U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((1U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x1fU)))) + << 0xcU)) + | (0xfffU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))) + : 0xdeadbeefU) + : 0xdeadbeefU)))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (1U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (2U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (3U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (4U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (5U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (6U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (7U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__real_zero_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (1U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (2U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (3U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (4U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (5U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (6U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (7U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + // ALWAYS at VX_decode.v:451 + if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_jal_offset + = ((8U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU : ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((1U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + (((0U + == + (7U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU))) + & (2U + > + (0xfffU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))) + ? 0xb0000000U + : 0xdeadbeefU) + : 0xdeadbeefU) + : 0xdeadbeefU))); + } else { + if ((8U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_jal_offset + = ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((0xffe00000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x1fU)))) + << 0x15U)) + | ((0x100000U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xbU)) + | ((0xff000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + | ((0x800U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 9U)) + | (0x7feU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))))) + : 0xdeadbeefU) : 0xdeadbeefU); + } else { + if ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt))) { + vlTOPp->Vortex__DOT__decode_jal_offset = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_jal_offset = 0xdeadbeefU; + } + } else { + vlTOPp->Vortex__DOT__decode_jal_offset = 0xdeadbeefU; + } + } + } else { + vlTOPp->Vortex__DOT__decode_jal_offset + = ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x1fU)))) + << 0xcU)) + | (0xfffU & + (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))) + : 0xdeadbeefU) : 0xdeadbeefU) + : 0xdeadbeefU); + } + } + } else { + vlTOPp->Vortex__DOT__decode_jal_offset = 0xdeadbeefU; + } + } else { + vlTOPp->Vortex__DOT__decode_jal_offset = 0xdeadbeefU; + } + // ALWAYS at VX_decode.v:519 + if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } else { + if ((8U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } else { + if ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt))) { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } + } + } else { + vlTOPp->Vortex__DOT__decode_branch_type + = ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0U : ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((0x4000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((0x2000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 6U + : 5U) + : + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 4U + : 3U)) + : ((0x2000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0U + : + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 2U + : 1U))) + : 0U) : 0U)); + } + } + } else { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } + vlTOPp->Vortex__DOT__decode_change_mask = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt)); + vlTOPp->Vortex__DOT__e_m_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__e_m_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__e_m_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__e_m_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__e_m_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [3U]; + vlTOPp->Vortex__DOT__e_m_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [2U]; + vlTOPp->Vortex__DOT__e_m_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__e_m_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [0U]; + vlTOPp->Vortex__DOT__e_m_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result + [3U]; + vlTOPp->Vortex__DOT__e_m_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result + [2U]; + vlTOPp->Vortex__DOT__e_m_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result + [0U]; + vlTOPp->Vortex__DOT__d_e_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [3U]; + vlTOPp->Vortex__DOT__d_e_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [2U]; + vlTOPp->Vortex__DOT__d_e_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [0U]; + vlTOPp->Vortex__DOT__d_e_a_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__d_e_a_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__d_e_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__d_e_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__d_e_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__d_e_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__d_e_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__d_e_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd + = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)))) & (0U + != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) + & ((IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num) + == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd + = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))) & (0U + != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd))) + & ((IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num) + == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__memory_mem_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [3U]; + vlTOPp->Vortex__DOT__memory_mem_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [2U]; + vlTOPp->Vortex__DOT__memory_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [1U]; + vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[3U] + = vlTOPp->Vortex__DOT__m_w_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2U] + = vlTOPp->Vortex__DOT__m_w_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1U] + = vlTOPp->Vortex__DOT__m_w_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[0U] + = vlTOPp->Vortex__DOT__m_w_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[3U] + = vlTOPp->Vortex__DOT__f_d_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[2U] + = vlTOPp->Vortex__DOT__f_d_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[1U] + = vlTOPp->Vortex__DOT__f_d_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] + = vlTOPp->Vortex__DOT__f_d_valid[0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[3U] + = vlTOPp->Vortex__DOT__m_w_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2U] + = vlTOPp->Vortex__DOT__m_w_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] + = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] + = vlTOPp->Vortex__DOT__m_w_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[3U] + = vlTOPp->Vortex__DOT__m_w_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2U] + = vlTOPp->Vortex__DOT__m_w_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1U] + = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[0U] + = vlTOPp->Vortex__DOT__m_w_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[3U] + = vlTOPp->Vortex__DOT__m_w_mem_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2U] + = vlTOPp->Vortex__DOT__m_w_mem_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1U] + = vlTOPp->Vortex__DOT__m_w_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[0U] + = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[3U] + = vlTOPp->Vortex__DOT__m_w_mem_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2U] + = vlTOPp->Vortex__DOT__m_w_mem_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1U] + = vlTOPp->Vortex__DOT__m_w_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[0U] + = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[0U] + = (((0U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall)) + | (1U != (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__real_zero_isclone)); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[1U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[2U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[3U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[4U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[5U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[6U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[7U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu + = ((0x63U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? ((5U > (IData)(vlTOPp->Vortex__DOT__decode_branch_type)) + ? 1U : 0xaU) : ((0x37U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? 0xbU : ((0x17U == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? 0xcU : + ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr) + ? ((1U + == + (3U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU))) + ? 0xdU + : + ((2U + == + (3U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU))) + ? 0xeU + : 0xfU)) + : (((0x23U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + | (3U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) + ? 0U + : + ((0x4000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0x2000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 9U + : 8U) + : + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0U + == + (0x7fU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x19U))) + ? 6U + : 7U) + : 5U)) + : + ((0x2000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 4U + : 3U) + : + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 2U + : + ((0x13U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? 0U + : + ((0U + == + (0x7fU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x19U))) + ? 0U + : 1U)))))))))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (1U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (2U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (3U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (4U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (5U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (6U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (7U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[3U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[2U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[3U] + = vlTOPp->Vortex__DOT__e_m_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[2U] + = vlTOPp->Vortex__DOT__e_m_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[1U] + = vlTOPp->Vortex__DOT__e_m_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[0U] + = vlTOPp->Vortex__DOT__e_m_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[3U] + = vlTOPp->Vortex__DOT__e_m_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2U] + = vlTOPp->Vortex__DOT__e_m_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] + = vlTOPp->Vortex__DOT__e_m_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] + = vlTOPp->Vortex__DOT__e_m_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[3U] + = vlTOPp->Vortex__DOT__d_e_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[2U] + = vlTOPp->Vortex__DOT__d_e_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[1U] + = vlTOPp->Vortex__DOT__d_e_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[0U] + = vlTOPp->Vortex__DOT__d_e_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[3U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[2U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[0U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[3U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[2U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[0U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[0U]; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd + = (((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)))) & (0U + != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) + & ((IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num) + == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd))); + vlTOPp->Vortex__DOT__forwarding_fwd_stall = ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)) + & (2U + == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))) + | (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) + & (2U + == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)))); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd + = (((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))) & (0U + != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd))) + & ((IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num) + == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[3U] + = vlTOPp->Vortex__DOT__memory_mem_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2U] + = vlTOPp->Vortex__DOT__memory_mem_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1U] + = vlTOPp->Vortex__DOT__memory_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[0U] + = vlTOPp->Vortex__DOT__memory_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[3U] + = vlTOPp->Vortex__DOT__memory_mem_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2U] + = vlTOPp->Vortex__DOT__memory_mem_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1U] + = vlTOPp->Vortex__DOT__memory_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[0U] + = vlTOPp->Vortex__DOT__memory_mem_result[0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]; + // ALWAYS at VX_decode.v:451 + if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_jal = ( + (~ + (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 3U)) + & ((~ + (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 2U)) + & ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 1U) + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__jal_sys_jal) + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]))))); + } else { + if ((8U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_jal + = ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 1U) & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U])); + } else { + if ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt))) { + vlTOPp->Vortex__DOT__decode_jal + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]; + } + } else { + vlTOPp->Vortex__DOT__decode_jal = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_jal = 0U; + } + } + } else { + vlTOPp->Vortex__DOT__decode_jal + = ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 2U) & ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 1U) & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]))); + } + } + } else { + vlTOPp->Vortex__DOT__decode_jal = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_jal = 0U; + } + // ALWAYS at VX_decode.v:519 + if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_branch_stall = 0U; + } else { + if ((8U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_branch_stall + = ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 1U) & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U])); + } else { + if ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt))) { + vlTOPp->Vortex__DOT__decode_branch_stall + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]; + } + } else { + vlTOPp->Vortex__DOT__decode_branch_stall = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_branch_stall = 0U; + } + } + } else { + vlTOPp->Vortex__DOT__decode_branch_stall + = ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 1U) & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U])) : + ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 1U) & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]))); + } + } + } else { + vlTOPp->Vortex__DOT__decode_branch_stall = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_branch_stall = 0U; + } + vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak + = ((0x73U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__jal_sys_jal) + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U])); + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[3U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [3U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [3U])); + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[2U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [2U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [2U])); + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[1U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [1U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [1U])); + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[0U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [0U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [0U])); + // ALWAYS at VX_decode.v:276 + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [1U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [2U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [3U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [4U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [5U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [6U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [7U]); + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U]; + // ALWAYS at VX_memory.v:113 + vlTOPp->Vortex__DOT__memory_branch_dir = (1U & + ((4U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? ( + (2U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? + ((~ (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + & (~ + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] + >> 0x1fU))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] + >> 0x1fU) + : + (~ + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] + >> 0x1fU)))) + : ( + (2U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] + >> 0x1fU) + : + (0U + != + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U])) + : + ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type) + & (0U + == + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U]))))); + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [0U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [1U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [2U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [3U]); + vlTOPp->Vortex__DOT__forwarding_src1_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)); + vlTOPp->Vortex__DOT__forwarding_src2_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid + [0U]; + vlTOPp->Vortex__DOT__decode_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [3U]; + vlTOPp->Vortex__DOT__decode_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [2U]; + vlTOPp->Vortex__DOT__decode_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [1U]; + vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [0U]; + vlTOPp->out_ebreak = ((0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak)); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__writeback_write_data[3U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [3U]; + vlTOPp->Vortex__DOT__writeback_write_data[2U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [2U]; + vlTOPp->Vortex__DOT__writeback_write_data[1U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [1U]; + vlTOPp->Vortex__DOT__writeback_write_data[0U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__add_warp = + (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall))); + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling + = (((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) + | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall)); + vlTOPp->Vortex__DOT__vx_fetch__DOT__stall = ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | (IData)(vlTOPp->Vortex__DOT__decode_branch_stall)) + | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) + | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); + vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp + = (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall))); + vlTOPp->out_cache_driver_in_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [3U]; + vlTOPp->out_cache_driver_in_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [2U]; + vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [1U]; + vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [0U]; + vlTOPp->out_cache_driver_in_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [3U]; + vlTOPp->out_cache_driver_in_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [2U]; + vlTOPp->out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [1U]; + vlTOPp->out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [0U]; + vlTOPp->Vortex__DOT__memory_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [3U]; + vlTOPp->Vortex__DOT__memory_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [2U]; + vlTOPp->Vortex__DOT__memory_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [1U]; + vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [0U]; + vlTOPp->out_cache_driver_in_address[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [3U]; + vlTOPp->out_cache_driver_in_address[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [2U]; + vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [1U]; + vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [0U]; + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (1U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (1U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (4U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (4U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (5U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (5U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (6U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (6U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (7U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (7U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__real_PC)); + vlTOPp->Vortex__DOT__memory_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [3U]; + vlTOPp->Vortex__DOT__memory_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [2U]; + vlTOPp->Vortex__DOT__memory_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [0U]; + vlTOPp->Vortex__DOT__execute_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [3U]; + vlTOPp->Vortex__DOT__execute_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [2U]; + vlTOPp->Vortex__DOT__execute_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [1U]; + vlTOPp->Vortex__DOT__execute_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [0U]; + vlTOPp->Vortex__DOT__execute_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__execute_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__execute_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__execute_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[3U] + = vlTOPp->Vortex__DOT__decode_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2U] + = vlTOPp->Vortex__DOT__decode_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__decode_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__decode_valid[0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[3U] + = vlTOPp->Vortex__DOT__writeback_write_data + [3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[2U] + = vlTOPp->Vortex__DOT__writeback_write_data + [2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[1U] + = vlTOPp->Vortex__DOT__writeback_write_data + [1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[0U] + = vlTOPp->Vortex__DOT__writeback_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (0U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (1U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (2U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (3U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (4U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (5U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (6U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (7U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[3U] + = vlTOPp->Vortex__DOT__memory_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2U] + = vlTOPp->Vortex__DOT__memory_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__memory_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__memory_valid[0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[4U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[5U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[6U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[7U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[3U] + = vlTOPp->Vortex__DOT__memory_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2U] + = vlTOPp->Vortex__DOT__memory_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1U] + = vlTOPp->Vortex__DOT__memory_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[0U] + = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[3U] + = vlTOPp->Vortex__DOT__memory_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2U] + = vlTOPp->Vortex__DOT__memory_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1U] + = vlTOPp->Vortex__DOT__memory_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] + = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[3U] + = vlTOPp->Vortex__DOT__execute_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2U] + = vlTOPp->Vortex__DOT__execute_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__execute_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__execute_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[3U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[2U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[0U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[0U]; + // ALWAYS at VX_alu.v:48 + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + >> 0x1fU)))))) + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U]) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))))); + // ALWAYS at VX_alu.v:48 + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + >> 0x1fU)))))) + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))))); + // ALWAYS at VX_alu.v:48 + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] + >> 0x1fU)))))) + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U]) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))))); + // ALWAYS at VX_alu.v:48 + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] + >> 0x1fU)))))) + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U]) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))))); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + // ALWAYS at VX_fetch.v:170 + if ((0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [0U]; + } + if ((1U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [1U]; + } + if ((2U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [2U]; + } + if ((3U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [3U]; + } + if ((4U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [4U]; + } + if ((5U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [5U]; + } + if ((6U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [6U]; + } + if ((7U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [7U]; + } + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[2U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[3U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data + [0U]; + vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var; + vlTOPp->Vortex__DOT__execute_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [3U]; + vlTOPp->Vortex__DOT__execute_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [2U]; + vlTOPp->Vortex__DOT__execute_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__execute_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[3U] + = vlTOPp->Vortex__DOT__execute_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2U] + = vlTOPp->Vortex__DOT__execute_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1U] + = vlTOPp->Vortex__DOT__execute_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[0U] + = vlTOPp->Vortex__DOT__execute_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[3U] + = vlTOPp->Vortex__DOT__execute_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2U] + = vlTOPp->Vortex__DOT__execute_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1U] + = vlTOPp->Vortex__DOT__execute_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[0U] + = vlTOPp->Vortex__DOT__execute_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[3U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [3U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [3U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [3U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [3U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [3U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [3U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [3U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [2U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [2U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [2U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [2U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [2U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [2U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [2U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [1U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [1U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [1U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [0U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [0U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [0U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [0U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [0U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[3U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [3U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [3U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [3U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [3U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [3U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [3U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [3U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [2U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [2U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [2U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [2U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [2U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [2U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [2U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [1U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [1U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [1U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [0U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [0U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [0U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [0U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [0U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]))); + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[0U] + = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data + [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register + [0U])); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[1U] + = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register + [1U])); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[2U] + = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data + [2U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register + [2U])); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[3U] + = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data + [3U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register + [3U])); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[0U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data + [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register + [0U]); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register + [1U]); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[2U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data + [2U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register + [2U]); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[3U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data + [3U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register + [3U]); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[0U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[0U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[0U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[0U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[0U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[0U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[0U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[0U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data + [0U]; +} + +VL_INLINE_OPT void VVortex::_settle__TOP__3(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_settle__TOP__3\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data[3U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data[2U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data[1U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data[0U] + = vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[1U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[1U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[1U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[1U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[1U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[1U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[1U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[1U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[2U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[2U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[2U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[2U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[2U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[2U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[2U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[2U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[3U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[3U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[3U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[3U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[3U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[3U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[3U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[3U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[4U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[4U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[4U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[4U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[4U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[4U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[4U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[4U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[5U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[5U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[5U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[5U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[5U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[5U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[5U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[5U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[6U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[6U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[6U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[6U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[6U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[6U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[6U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[6U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[7U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[7U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[7U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[7U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[7U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[7U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[7U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[7U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data + [0U]; + // ALWAYS at VX_decode.v:247 + if ((0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [0U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [0U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [0U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [0U][0U]; + } + if ((1U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [1U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [1U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [1U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [1U][0U]; + } + if ((2U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [2U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [2U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [2U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [2U][0U]; + } + if ((3U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [3U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [3U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [3U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [3U][0U]; + } + if ((4U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [4U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [4U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [4U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [4U][0U]; + } + if ((5U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [5U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [5U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [5U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [5U][0U]; + } + if ((6U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [6U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [6U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [6U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [6U][0U]; + } + if ((7U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [7U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [7U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [7U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data + [7U][0U]; + } + // ALWAYS at VX_decode.v:247 + if ((0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [0U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [0U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [0U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [0U][0U]; + } + if ((1U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [1U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [1U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [1U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [1U][0U]; + } + if ((2U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [2U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [2U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [2U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [2U][0U]; + } + if ((3U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [3U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [3U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [3U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [3U][0U]; + } + if ((4U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [4U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [4U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [4U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [4U][0U]; + } + if ((5U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [5U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [5U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [5U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [5U][0U]; + } + if ((6U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [6U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [6U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [6U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [6U][0U]; + } + if ((7U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [7U][3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [7U][2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [7U][1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data + [7U][0U]; + } + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__decode_a_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__decode_a_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__decode_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__decode_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__decode_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__decode_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__decode_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__decode_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[0U] + = VL_LTES_III(1,32,32, 0U, vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data + [0U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[1U] + = VL_LTES_III(1,32,32, 1U, vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data + [0U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[2U] + = VL_LTES_III(1,32,32, 2U, vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data + [0U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[3U] + = VL_LTES_III(1,32,32, 3U, vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data + [0U]); + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[3U] + = vlTOPp->Vortex__DOT__decode_a_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[2U] + = vlTOPp->Vortex__DOT__decode_a_reg_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[1U] + = vlTOPp->Vortex__DOT__decode_a_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[0U] + = vlTOPp->Vortex__DOT__decode_a_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[3U] + = vlTOPp->Vortex__DOT__decode_b_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[2U] + = vlTOPp->Vortex__DOT__decode_b_reg_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__decode_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[0U] + = vlTOPp->Vortex__DOT__decode_b_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask[3U] + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + ? vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask + [3U] : vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask + [3U]); + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask[2U] + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + ? vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask + [2U] : vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask + [2U]); + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + ? vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask + [1U]); + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + ? vlTOPp->Vortex__DOT__vx_decode__DOT__jalrs_thread_mask + [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__jmprt_thread_mask + [0U]); + vlTOPp->Vortex__DOT__decode_thread_mask[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask + [3U]; + vlTOPp->Vortex__DOT__decode_thread_mask[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask + [2U]; + vlTOPp->Vortex__DOT__decode_thread_mask[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask + [1U]; + vlTOPp->Vortex__DOT__decode_thread_mask[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_thread_mask + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[3U] + = vlTOPp->Vortex__DOT__decode_thread_mask[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[2U] + = vlTOPp->Vortex__DOT__decode_thread_mask[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[1U] + = vlTOPp->Vortex__DOT__decode_thread_mask[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[0U] + = vlTOPp->Vortex__DOT__decode_thread_mask[0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask + [0U]; + // ALWAYS at VX_warp.v:41 + if (((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp) + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero + [0U]; + } else { + if (vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask + [0U]; + } + } + // ALWAYS at VX_warp.v:41 + if (((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp) + & (1U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero + [0U]; + } else { + if (vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_change_mask) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask + [0U]; + } + } + // ALWAYS at VX_warp.v:41 + if (((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp) + & (2U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero + [0U]; + } else { + if (vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_change_mask) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask + [0U]; + } + } + // ALWAYS at VX_warp.v:41 + if (((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp) + & (3U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero + [0U]; + } else { + if (vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_change_mask) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask + [0U]; + } + } + // ALWAYS at VX_warp.v:41 + if (((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp) + & (4U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero + [0U]; + } else { + if (vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_change_mask) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask + [0U]; + } + } + // ALWAYS at VX_warp.v:41 + if (((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp) + & (5U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero + [0U]; + } else { + if (vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_change_mask) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask + [0U]; + } + } + // ALWAYS at VX_warp.v:41 + if (((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp) + & (6U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero + [0U]; + } else { + if (vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_change_mask) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask + [0U]; + } + } + // ALWAYS at VX_warp.v:41 + if (((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp) + & (7U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero + [0U]; + } else { + if (vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_change_mask) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask + [0U]; + } + } + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask + [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid + [0U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask + [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid + [1U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid[2U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask + [2U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid + [2U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid[3U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask + [3U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid + [3U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask + [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid + [0U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask + [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid + [1U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid[2U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask + [2U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid + [2U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid[3U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask + [3U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid + [3U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask + [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid + [0U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask + [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid + [1U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid[2U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask + [2U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid + [2U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid[3U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask + [3U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid + [3U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask + [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid + [0U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask + [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid + [1U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid[2U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask + [2U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid + [2U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid[3U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask + [3U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid + [3U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask + [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid + [0U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask + [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid + [1U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid[2U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask + [2U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid + [2U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid[3U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask + [3U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid + [3U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask + [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid + [0U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask + [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid + [1U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid[2U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask + [2U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid + [2U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid[3U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask + [3U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid + [3U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask + [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid + [0U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask + [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid + [1U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid[2U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask + [2U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid + [2U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid[3U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask + [3U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid + [3U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask + [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid + [0U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask + [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid + [1U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid[2U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask + [2U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid + [2U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid[3U] + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_change_mask) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask + [3U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_stall)) + & vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid + [3U])); + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[0U][3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[0U][2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[0U][1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[0U][0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[1U][3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[1U][2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[1U][1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[1U][0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[2U][3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[2U][2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[2U][1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[2U][0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[3U][3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[3U][2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[3U][1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[3U][0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[4U][3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[4U][2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[4U][1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[4U][0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[5U][3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[5U][2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[5U][1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[5U][0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[6U][3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[6U][2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[6U][1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[6U][0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[7U][3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid + [3U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[7U][2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid + [2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[7U][1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid + [1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid[7U][0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid + [0U]; + // ALWAYS at VX_fetch.v:170 + if ((0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [0U][0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [0U][1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [0U][2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [0U][3U]; + } + if ((1U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [1U][0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [1U][1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [1U][2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [1U][3U]; + } + if ((2U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [2U][0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [2U][1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [2U][2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [2U][3U]; + } + if ((3U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [3U][0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [3U][1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [3U][2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [3U][3U]; + } + if ((4U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [4U][0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [4U][1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [4U][2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [4U][3U]; + } + if ((5U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [5U][0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [5U][1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [5U][2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [5U][3U]; + } + if ((6U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [6U][0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [6U][1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [6U][2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [6U][3U]; + } + if ((7U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [7U][0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [7U][1U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [7U][2U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [7U][3U]; + } + vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__out_valid_var + [0U]; + vlTOPp->Vortex__DOT__fetch_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid + [3U]; + vlTOPp->Vortex__DOT__fetch_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid + [2U]; + vlTOPp->Vortex__DOT__fetch_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid + [1U]; + vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[3U] + = vlTOPp->Vortex__DOT__fetch_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2U] + = vlTOPp->Vortex__DOT__fetch_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__fetch_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__fetch_valid[0U]; +} + +VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__4\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + // Begin mtask footprint all: + VL_SIG8(__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall,5,0); + VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0,0,0); + VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0); + VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0); + VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v2,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v3,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v2,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v3,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v2,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v3,0,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0,0,0); + VL_SIG16(__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0,10,0); + VL_SIG16(__Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2,31,0); 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+ VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v2,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v3,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v2,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v3,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v2,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v3,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v2,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v3,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v2,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v3,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v2,31,0); + VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v3,31,0); + // Body + __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + // ALWAYS at VX_e_m_reg.v:128 + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data + [3U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data + [2U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v2 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data + [1U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v3 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data + [0U]; + // ALWAYS at VX_m_w_reg.v:63 + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid + [3U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid + [2U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v2 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid + [1U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v3 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid + [0U]; + // ALWAYS at VX_e_m_reg.v:128 + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid + [3U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid + [2U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v2 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid + [1U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v3 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid + [0U]; + // ALWAYS at VX_context.v:83 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__real_zero_isclone) + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall)))) { + __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall = 0xaU; + } else { + if ((1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall))) { + __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall = 0U; + } else { + if ((0U < (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall))) { + __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall + = (0x3fU & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + = (0xfffffU & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U : ((0x37U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU) : ((0x17U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? + (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU) + : 0U)))); + // ALWAYS at VX_m_w_reg.v:63 + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result + [3U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result + [2U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v2 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result + [1U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v3 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result + [0U]; + // ALWAYS at VX_m_w_reg.v:63 + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result + [3U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result + [2U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v2 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result + [1U]; + __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v3 + = vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result + [0U]; + // ALWAYS at VX_csr_handler.v:36 + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address + = vlTOPp->Vortex__DOT__decode_csr_address; + // ALWAYS at VX_csr_handler.v:36 + if (vlTOPp->Vortex__DOT__m_w_valid[0U]) { + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret + = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret); + } + // ALWAYS at VX_csr_handler.v:36 + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle + = (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle); + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src = + (1U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U : (1U & (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype) + | (0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) + ? 1U : 0U)))); + // ALWAYS at VX_e_m_reg.v:128 + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result + [3U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result + [2U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v2 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result + [1U]; + __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v3 + = vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result + [0U]; + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type; + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal; + // ALWAYS at VX_d_e_reg.v:145 + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid + [3U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid + [2U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid + [1U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v3 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid + [0U]); + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write; + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read; + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC; + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed; + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + = (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset); + // ALWAYS at VX_m_w_reg.v:63 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + // ALWAYS at VX_register_file.v:45 + if (((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid + [0U]) & (0U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num)))) { + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data + [0U]; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0 = 1U; + __Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } + // ALWAYS at VX_d_e_reg.v:145 + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data + [3U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data + [2U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data + [1U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v3 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data + [0U]); + // ALWAYS at VX_csr_handler.v:45 + if (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__is_csr) { + vlTOPp->Vortex__DOT__vx_csr_handler__DOT____Vlvbound1 + = (0xfffU & vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_result); + if (VL_LIKELY((0x400U >= (0x7ffU & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address))))) { + __Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0 + = vlTOPp->Vortex__DOT__vx_csr_handler__DOT____Vlvbound1; + __Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = 1U; + __Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0 + = (0x7ffU & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address)); + } + } + // ALWAYS at VX_d_e_reg.v:145 + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data + [3U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data + [2U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data + [1U]); + __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v3 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data + [0U]); + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid + [3U]) & (0U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__real_zero_isclone)))) { + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data + [3U]; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + __Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__real_zero_isclone) + & ((3U == vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register + [0U]) & (1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall)))) + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [9U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [8U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [7U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [6U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [5U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [4U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [3U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [2U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [1U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid + [2U]) & (0U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__real_zero_isclone)))) { + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data + [2U]; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + __Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__real_zero_isclone) + & ((2U == vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register + [0U]) & (1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall)))) + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [9U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [8U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [7U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [6U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [5U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [4U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [3U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [2U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [1U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid + [1U]) & (0U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__real_zero_isclone)))) { + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data + [1U]; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + __Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__real_zero_isclone) + & ((1U == vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register + [0U]) & (1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall)))) + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [9U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [8U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [7U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [6U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [5U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [4U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [3U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [2U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [1U]; + __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYSPOST at VX_e_m_reg.v:139 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[3U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v0; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[2U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v1; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[1U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v2; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[0U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v3; + // ALWAYSPOST at VX_m_w_reg.v:72 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[3U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[2U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[1U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v2; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[0U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v3; + // ALWAYSPOST at VX_e_m_reg.v:148 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[3U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[2U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[1U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v2; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[0U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v3; + // ALWAYSPOST at VX_m_w_reg.v:66 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[3U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[2U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[1U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v2; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[0U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v3; + // ALWAYSPOST at VX_m_w_reg.v:65 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[3U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[2U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[1U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v2; + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[0U] + = __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v3; + // ALWAYSPOST at VX_e_m_reg.v:130 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[3U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[2U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v2; + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] + = __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v3; + // ALWAYSPOST at VX_d_e_reg.v:167 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[3U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[2U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v2; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v3; + // ALWAYSPOST at VX_register_file.v:48 + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0) { + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0; + } + // ALWAYSPOST at VX_d_e_reg.v:150 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[3U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[2U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[1U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v2; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[0U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v3; + // ALWAYSPOST at VX_csr_handler.v:48 + if (__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0) { + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr[__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0] + = __Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0; + } + // ALWAYSPOST at VX_d_e_reg.v:151 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[3U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[2U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[1U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v2; + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[0U] + = __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v3; + // ALWAYSPOST at VX_register_file_slave.v:56 + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall + = __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[3U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[3U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[3U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[3U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[3U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result + [0U]; + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U : (IData)(vlTOPp->Vortex__DOT__decode_branch_type)); + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal = ((~ (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)) + & (IData)(vlTOPp->Vortex__DOT__decode_jal)); + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[3U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid + [0U]; + vlTOPp->out_cache_driver_in_mem_write = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write; + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_write + = (7U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 7U : ((0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU) : 7U))); + vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read; + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read + = (7U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 7U : ((3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU) : 7U))); + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC = + ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U : vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC); + vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset + << 1U)); + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0xdeadbeefU : vlTOPp->Vortex__DOT__decode_itype_immed); + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U : vlTOPp->Vortex__DOT__decode_jal_offset); + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[2U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[3U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[3U] + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next; + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data + [0U]; + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__is_csr = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__is_csr; + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address; + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_result + = ((0xdU == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask + : ((0xeU == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT__csr_decode_csr_data + | vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask) + : ((0xfU == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT__csr_decode_csr_data + & ((IData)(0xffffffffU) - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask)) + : 0xdeadbeefU))); + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[3U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[2U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data + [0U]; + vlTOPp->Vortex__DOT__e_m_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__e_m_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__e_m_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__e_m_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__m_w_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [3U]; + vlTOPp->Vortex__DOT__m_w_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [2U]; + vlTOPp->Vortex__DOT__m_w_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__m_w_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid + [0U]; + vlTOPp->Vortex__DOT__e_m_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [3U]; + vlTOPp->Vortex__DOT__e_m_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [2U]; + vlTOPp->Vortex__DOT__e_m_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__e_m_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid + [0U]; + vlTOPp->Vortex__DOT__m_w_mem_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [3U]; + vlTOPp->Vortex__DOT__m_w_mem_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [2U]; + vlTOPp->Vortex__DOT__m_w_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [1U]; + vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result + [0U]; + vlTOPp->Vortex__DOT__m_w_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [3U]; + vlTOPp->Vortex__DOT__m_w_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [2U]; + vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result + [0U]; + vlTOPp->Vortex__DOT__e_m_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result + [3U]; + vlTOPp->Vortex__DOT__e_m_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result + [2U]; + vlTOPp->Vortex__DOT__e_m_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result + [0U]; + vlTOPp->Vortex__DOT__d_e_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [3U]; + vlTOPp->Vortex__DOT__d_e_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [2U]; + vlTOPp->Vortex__DOT__d_e_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs + [0U]; + vlTOPp->Vortex__DOT__d_e_a_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__d_e_a_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__d_e_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__d_e_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U + == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) + ? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle) + : + ((0xc80U + == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) + ? (IData)( + (vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle + >> 0x20U)) + : + ((0xc02U + == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) + ? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret) + : + ((0xc82U + == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) + ? (IData)( + (vlTOPp->Vortex__DOT__vx_csr_handler__DOT__instret + >> 0x20U)) + : + ((0x400U + >= + (0x7ffU + & (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address))) + ? + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr + [ + (0x7ffU + & (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address))] + : 0U))))); + vlTOPp->Vortex__DOT__d_e_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__d_e_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__d_e_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__d_e_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[3U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[2U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] + = vlTOPp->Vortex__DOT__e_m_b_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[3U] + = vlTOPp->Vortex__DOT__m_w_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2U] + = vlTOPp->Vortex__DOT__m_w_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1U] + = vlTOPp->Vortex__DOT__m_w_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[0U] + = vlTOPp->Vortex__DOT__m_w_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[3U] + = vlTOPp->Vortex__DOT__e_m_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[2U] + = vlTOPp->Vortex__DOT__e_m_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[1U] + = vlTOPp->Vortex__DOT__e_m_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[0U] + = vlTOPp->Vortex__DOT__e_m_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[3U] + = vlTOPp->Vortex__DOT__m_w_mem_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2U] + = vlTOPp->Vortex__DOT__m_w_mem_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1U] + = vlTOPp->Vortex__DOT__m_w_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[0U] + = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[3U] + = vlTOPp->Vortex__DOT__m_w_mem_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2U] + = vlTOPp->Vortex__DOT__m_w_mem_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1U] + = vlTOPp->Vortex__DOT__m_w_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[0U] + = vlTOPp->Vortex__DOT__m_w_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[3U] + = vlTOPp->Vortex__DOT__m_w_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2U] + = vlTOPp->Vortex__DOT__m_w_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] + = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] + = vlTOPp->Vortex__DOT__m_w_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[3U] + = vlTOPp->Vortex__DOT__m_w_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2U] + = vlTOPp->Vortex__DOT__m_w_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1U] + = vlTOPp->Vortex__DOT__m_w_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[0U] + = vlTOPp->Vortex__DOT__m_w_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[3U] + = vlTOPp->Vortex__DOT__e_m_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2U] + = vlTOPp->Vortex__DOT__e_m_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] + = vlTOPp->Vortex__DOT__e_m_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] + = vlTOPp->Vortex__DOT__e_m_alu_result[0U]; + vlTOPp->Vortex__DOT__execute_branch_stall = ((0U + != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) + | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal)); + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[3U] + = vlTOPp->Vortex__DOT__d_e_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[2U] + = vlTOPp->Vortex__DOT__d_e_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[1U] + = vlTOPp->Vortex__DOT__d_e_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[0U] + = vlTOPp->Vortex__DOT__d_e_valid[0U]; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[3U] + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next; + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U : ((IData)(4U) + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC)); + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[3U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[2U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[0U] + = vlTOPp->Vortex__DOT__d_e_a_reg_data[0U]; + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__is_csr = + ((~ (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr)); + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U : (IData)(vlTOPp->Vortex__DOT__decode_csr_address)); + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U : (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr) + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xeU)) ? (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)) + : vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [0U])); + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op = + ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0xfU : (((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x19U) & (0x33U == (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) + ? (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu) + : (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu))); + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[3U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[2U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[0U] + = vlTOPp->Vortex__DOT__d_e_b_reg_data[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2 + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U]; + // ALWAYS at VX_memory.v:113 + vlTOPp->Vortex__DOT__memory_branch_dir = (1U & + ((4U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? ( + (2U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? + ((~ (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + & (~ + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] + >> 0x1fU))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] + >> 0x1fU) + : + (~ + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] + >> 0x1fU)))) + : ( + (2U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U] + >> 0x1fU) + : + (0U + != + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U])) + : + ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type) + & (0U + == + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U]))))); + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [0U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [1U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [2U]); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2 + = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rs2_src) + ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed + : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data + [3U]); + vlTOPp->out_cache_driver_in_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [3U]; + vlTOPp->out_cache_driver_in_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [2U]; + vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [1U]; + vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data + [0U]; + vlTOPp->out_cache_driver_in_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [3U]; + vlTOPp->out_cache_driver_in_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [2U]; + vlTOPp->out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [1U]; + vlTOPp->out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid + [0U]; + vlTOPp->Vortex__DOT__memory_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [3U]; + vlTOPp->Vortex__DOT__memory_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [2U]; + vlTOPp->Vortex__DOT__memory_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [1U]; + vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid + [0U]; + vlTOPp->out_cache_driver_in_address[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [3U]; + vlTOPp->out_cache_driver_in_address[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [2U]; + vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [1U]; + vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address + [0U]; + vlTOPp->Vortex__DOT__memory_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [3U]; + vlTOPp->Vortex__DOT__memory_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [2U]; + vlTOPp->Vortex__DOT__memory_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result + [0U]; + vlTOPp->Vortex__DOT__execute_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [3U]; + vlTOPp->Vortex__DOT__execute_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [2U]; + vlTOPp->Vortex__DOT__execute_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [1U]; + vlTOPp->Vortex__DOT__execute_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid + [0U]; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[3U] + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1fU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1eU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1dU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1cU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1bU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x1aU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x19U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x18U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x17U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x16U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x15U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x14U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x13U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x12U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x11U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0x10U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xfU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xeU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xdU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xcU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xbU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0xaU]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [9U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [8U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [7U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [6U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [5U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [4U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers + [0U]; + vlTOPp->Vortex__DOT__execute_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__execute_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__execute_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__execute_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result + = VL_MULS_QQQ(64,64,64, VL_EXTENDS_QI(64,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U]), + VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)); + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[3U] + = vlTOPp->Vortex__DOT__memory_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2U] + = vlTOPp->Vortex__DOT__memory_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__memory_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__memory_valid[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[3U] + = vlTOPp->Vortex__DOT__memory_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2U] + = vlTOPp->Vortex__DOT__memory_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1U] + = vlTOPp->Vortex__DOT__memory_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[0U] + = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[3U] + = vlTOPp->Vortex__DOT__memory_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2U] + = vlTOPp->Vortex__DOT__memory_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1U] + = vlTOPp->Vortex__DOT__memory_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] + = vlTOPp->Vortex__DOT__memory_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[3U] + = vlTOPp->Vortex__DOT__execute_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2U] + = vlTOPp->Vortex__DOT__execute_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__execute_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__execute_valid[0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x1fU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1fU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x1eU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1eU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x1dU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1dU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x1cU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1cU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x1bU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1bU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x1aU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x1aU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x19U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x19U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x18U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x18U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x17U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x17U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x16U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x16U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x15U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x15U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x14U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x14U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x13U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x13U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x12U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x12U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x11U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x11U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0x10U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0x10U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0xfU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0xfU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0xeU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0xeU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0xdU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0xdU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0xcU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0xcU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0xbU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0xbU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0xaU] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0xaU]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[9U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [9U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[8U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [8U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[7U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [7U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[6U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [6U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[5U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [5U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[4U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [4U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_wspawn_regs[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[3U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[2U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[1U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[0U] + = vlTOPp->Vortex__DOT__execute_b_reg_data[0U]; + // ALWAYS at VX_alu.v:48 + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + >> 0x1fU)))))) + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U]) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [0U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2)))))); + // ALWAYS at VX_alu.v:48 + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + >> 0x1fU)))))) + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U]) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [1U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2)))))); + // ALWAYS at VX_alu.v:48 + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] + >> 0x1fU)))))) + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U]) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [2U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2)))))); + // ALWAYS at VX_alu.v:48 + vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result + = ((0x10U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? 0U : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] : VL_MODDIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] : VL_MODDIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIV_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)) + : ((0U == vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0xffffffffU : + VL_DIVS_III(32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((((QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U])) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U)) + : (IData)((((((QData)((IData)( + VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] + >> 0x1fU)))))) + << 0x20U) + | (QData)((IData)( + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U]))) + * (QData)((IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) + >> 0x20U))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (IData)((vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result + >> 0x20U)) + : (IData)(vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result))))) + : ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? vlTOPp->Vortex__DOT__csr_decode_csr_data + : (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC + + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU)))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed + << 0xcU) + : + ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] + >= vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? 0U + : 0xffffffffU)) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2 + & vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U]) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] + | vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))) + : ((4U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? VL_SHIFTRS_III(32,32,5, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U], + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)) + : (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] >> (0x1fU & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) + : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] ^ vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + : ((vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] < vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U : 0U))) : ((2U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (VL_LTS_III(1,32,32, + vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U], vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + ? 1U + : 0U) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2))) + : + ((1U + & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) + ? + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] + - vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2) + : + (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data + [3U] + + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2)))))); + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[1U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[2U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[3U] + = vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result; + vlTOPp->Vortex__DOT__execute_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [3U]; + vlTOPp->Vortex__DOT__execute_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [2U]; + vlTOPp->Vortex__DOT__execute_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [1U]; + vlTOPp->Vortex__DOT__execute_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[3U] + = vlTOPp->Vortex__DOT__execute_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2U] + = vlTOPp->Vortex__DOT__execute_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1U] + = vlTOPp->Vortex__DOT__execute_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[0U] + = vlTOPp->Vortex__DOT__execute_alu_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[3U] + = vlTOPp->Vortex__DOT__execute_alu_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2U] + = vlTOPp->Vortex__DOT__execute_alu_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1U] + = vlTOPp->Vortex__DOT__execute_alu_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[0U] + = vlTOPp->Vortex__DOT__execute_alu_result[0U]; +} + +VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__5\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_valid[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_valid[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_valid[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_valid[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid + [0U]; + // ALWAYS at VX_m_w_reg.v:63 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd; + // ALWAYS at VX_m_w_reg.v:63 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num + = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num; + // ALWAYS at VX_m_w_reg.v:63 + vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb; + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd; + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num + = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num; + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[3U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [3U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [3U])); + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[2U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [2U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [2U])); + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[1U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [1U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [1U])); + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[0U] + = ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data + [0U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result + [0U])); + // ALWAYS at VX_e_m_reg.v:128 + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb; + vlTOPp->Vortex__DOT__writeback_write_data[3U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [3U]; + vlTOPp->Vortex__DOT__writeback_write_data[2U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [2U]; + vlTOPp->Vortex__DOT__writeback_write_data[1U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [1U]; + vlTOPp->Vortex__DOT__writeback_write_data[0U] = + vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data + [0U]; + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = (0x1fU + & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U + : + (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 7U))); + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num + = (0xfU & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U : (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[3U] + = vlTOPp->Vortex__DOT__writeback_write_data + [3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[2U] + = vlTOPp->Vortex__DOT__writeback_write_data + [2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[1U] + = vlTOPp->Vortex__DOT__writeback_write_data + [1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[0U] + = vlTOPp->Vortex__DOT__writeback_write_data + [0U]; + // ALWAYS at VX_d_e_reg.v:145 + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) + ? 0U + : + (((((0x6fU + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + | (0x67U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs)) + | ((0x73U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & (0U + == + (7U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU))))) + ? 3U + : + ((3U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? 2U + : + ((((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype) + | (0x33U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) + | (0x37U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) + | (0x17U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr)) + ? 1U + : 0U)))); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_write_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_write_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_write_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_write_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data + [0U]; +} + +VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__6\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + // Begin mtask footprint all: + VL_SIG8(__Vdly__Vortex__DOT__vx_fetch__DOT__warp_num,3,0); + VL_SIG8(__Vdly__Vortex__DOT__vx_fetch__DOT__warp_count,3,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v4,0,0); + VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v4,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v5,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v6,0,0); + VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v7,0,0); + // Body + __Vdly__Vortex__DOT__vx_fetch__DOT__warp_count + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_count; + __Vdly__Vortex__DOT__vx_fetch__DOT__warp_num = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num; + __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 0U; + __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v4 = 0U; + // ALWAYS at VX_warp.v:71 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__real_PC + = ((IData)(vlTOPp->reset) ? 0U : ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_stall) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC + : ((IData)(4U) + + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC))); + // ALWAYS at VX_f_d_reg.v:36 + if (vlTOPp->reset) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall))))) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + = vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var; + } + } + // ALWAYS at VX_warp.v:71 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__real_PC + = ((IData)(vlTOPp->reset) ? 0U : (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (7U == + ((IData)(1U) + + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state)))) + ? vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [0U] : ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_stall) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC + : + ((IData)(4U) + + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC)))); + // ALWAYS at VX_warp.v:71 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__real_PC + = ((IData)(vlTOPp->reset) ? 0U : (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (6U == + ((IData)(1U) + + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state)))) + ? vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [0U] : ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_stall) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC + : + ((IData)(4U) + + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC)))); + // ALWAYS at VX_warp.v:71 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__real_PC + = ((IData)(vlTOPp->reset) ? 0U : (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (5U == + ((IData)(1U) + + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state)))) + ? vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [0U] : ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_stall) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC + : + ((IData)(4U) + + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC)))); + // ALWAYS at VX_warp.v:71 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__real_PC + = ((IData)(vlTOPp->reset) ? 0U : (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (4U == + ((IData)(1U) + + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state)))) + ? vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [0U] : ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_stall) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC + : + ((IData)(4U) + + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC)))); + // ALWAYS at VX_warp.v:71 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__real_PC + = ((IData)(vlTOPp->reset) ? 0U : (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (3U == + ((IData)(1U) + + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state)))) + ? vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [0U] : ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_stall) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC + : + ((IData)(4U) + + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC)))); + // ALWAYS at VX_warp.v:71 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__real_PC + = ((IData)(vlTOPp->reset) ? 0U : (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (2U == + ((IData)(1U) + + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state)))) + ? vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [0U] : ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_stall) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC + : + ((IData)(4U) + + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC)))); + // ALWAYS at VX_warp.v:71 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__real_PC + = ((IData)(vlTOPp->reset) ? 0U : (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (1U == + ((IData)(1U) + + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state)))) + ? vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data + [0U] : ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_stall) + ? vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC + : + ((IData)(4U) + + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC)))); + // ALWAYS at VX_fetch.v:63 + __Vdly__Vortex__DOT__vx_fetch__DOT__warp_num = + (0xfU & (((((IData)(vlTOPp->reset) | ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num) + >= (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))) + | (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp)) + | (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__add_warp)) + ? 0U : (vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_valid + [(7U & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num)))] + ? ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num)) + : ((IData)(2U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))))); + if (vlTOPp->Vortex__DOT__vx_fetch__DOT__add_warp) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))); + __Vdly__Vortex__DOT__vx_fetch__DOT__warp_count + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_count))); + } else { + if (vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp) { + __Vdly__Vortex__DOT__vx_fetch__DOT__warp_count + = (0xfU & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_count) + - (IData)(1U))); + if ((2U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_count))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state = 0U; + } + } + } + // ALWAYS at VX_f_d_reg.v:36 + if (vlTOPp->reset) { + __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 1U; + } else { + if ((1U & (~ ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall))))) { + __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v4 + = vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid + [3U]; + __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v4 = 1U; + __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v5 + = vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid + [2U]; + __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v6 + = vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid + [1U]; + __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v7 + = vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid + [0U]; + } + } + // ALWAYS at VX_f_d_reg.v:36 + if (vlTOPp->reset) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall))))) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num; + } + } + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_count + = __Vdly__Vortex__DOT__vx_fetch__DOT__warp_count; + // ALWAYSPOST at VX_f_d_reg.v:42 + if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] = 0U; + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] = 0U; + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[2U] = 0U; + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[3U] = 0U; + } + if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v4) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[3U] + = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v4; + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[2U] + = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v5; + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] + = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v6; + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] + = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v7; + } + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num = __Vdly__Vortex__DOT__vx_fetch__DOT__warp_num; + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (7U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (7U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (6U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (6U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (5U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (5U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (4U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (4U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__real_PC)); + // ALWAYS at VX_warp.v:57 + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC + = (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) + & (1U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest + : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) + & (1U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))) + ? vlTOPp->Vortex__DOT__memory_branch_dest + : vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__real_PC)); + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[3U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[0U] + = vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + [0U]; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[0U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[7U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[6U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[5U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[4U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[3U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[2U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc[1U] + = vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC; + vlTOPp->Vortex__DOT__f_d_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [3U]; + vlTOPp->Vortex__DOT__f_d_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [2U]; + vlTOPp->Vortex__DOT__f_d_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [1U]; + vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid + [0U]; + // ALWAYS at VX_fetch.v:170 + if ((0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [0U]; + } + if ((1U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [1U]; + } + if ((2U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [2U]; + } + if ((3U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [3U]; + } + if ((4U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [4U]; + } + if ((5U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [5U]; + } + if ((6U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [6U]; + } + if ((7U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))) { + vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var + = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_glob_pc + [7U]; + } + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[3U] + = vlTOPp->Vortex__DOT__f_d_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[2U] + = vlTOPp->Vortex__DOT__f_d_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[1U] + = vlTOPp->Vortex__DOT__f_d_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] + = vlTOPp->Vortex__DOT__f_d_valid[0U]; + vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC_var; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]; + vlTOPp->Vortex__DOT__decode_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [3U]; + vlTOPp->Vortex__DOT__decode_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [2U]; + vlTOPp->Vortex__DOT__decode_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [1U]; + vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[3U] + = vlTOPp->Vortex__DOT__decode_valid[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2U] + = vlTOPp->Vortex__DOT__decode_valid[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1U] + = vlTOPp->Vortex__DOT__decode_valid[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[0U] + = vlTOPp->Vortex__DOT__decode_valid[0U]; +} + +VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__7\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // ALWAYS at VX_register_file_slave.v:68 + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; + // ALWAYS at VX_register_file_slave.v:68 + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; + // ALWAYS at VX_register_file_slave.v:68 + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; + // ALWAYS at VX_register_file.v:52 + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; + // ALWAYS at VX_register_file_slave.v:68 + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + // ALWAYS at VX_register_file_slave.v:68 + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + // ALWAYS at VX_register_file_slave.v:68 + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + // ALWAYS at VX_register_file.v:52 + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data; + vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data; +} + +VL_INLINE_OPT void VVortex::_combo__TOP__8(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_combo__TOP__8\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[3U] + = vlTOPp->in_cache_driver_out_data[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2U] + = vlTOPp->in_cache_driver_out_data[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1U] + = vlTOPp->in_cache_driver_out_data[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] + = vlTOPp->in_cache_driver_out_data[0U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [3U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [2U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [1U]; + vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data + [0U]; + vlTOPp->Vortex__DOT__memory_mem_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [3U]; + vlTOPp->Vortex__DOT__memory_mem_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [2U]; + vlTOPp->Vortex__DOT__memory_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [1U]; + vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[3U] + = vlTOPp->Vortex__DOT__memory_mem_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2U] + = vlTOPp->Vortex__DOT__memory_mem_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1U] + = vlTOPp->Vortex__DOT__memory_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[0U] + = vlTOPp->Vortex__DOT__memory_mem_result[0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[3U] + = vlTOPp->Vortex__DOT__memory_mem_result[3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2U] + = vlTOPp->Vortex__DOT__memory_mem_result[2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1U] + = vlTOPp->Vortex__DOT__memory_mem_result[1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[0U] + = vlTOPp->Vortex__DOT__memory_mem_result[0U]; +} + +VL_INLINE_OPT void VVortex::_sequent__TOP__9(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__9\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // ALWAYS at VX_f_d_reg.v:36 + if (vlTOPp->reset) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall))))) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + ? 0U : vlTOPp->fe_instruction); + } + } + vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype = + ((0x13U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + | (3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))); + vlTOPp->Vortex__DOT__decode_csr_address = (0xfffU + & (((0U + != + (7U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU))) + & (2U + <= + (0xfffU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))) + ? + (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U) + : 0x55U)); + // ALWAYS at VX_decode.v:577 + vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)); + vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = + vlTOPp->__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu + [vlTOPp->__Vtableidx1]; + vlTOPp->Vortex__DOT__vx_decode__DOT__alu_tempp + = (0xfffU & (((1U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU))) | (5U + == + (7U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)))) + ? (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)) : (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))); + vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr = ( + (0x73U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & (0U + != + (7U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__jal_sys_jal + = ((0U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU))) & (2U > (0xfffU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt = + ((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & (4U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn + = ((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & (0U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone = + ((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & (5U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs = + ((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & (6U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU)))); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd + = (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))) + & ((IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num) + == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd + = (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))) & (0U + != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))) + & ((IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num) + == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num))); + // ALWAYS at VX_decode.v:508 + vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ( + (0x20U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0x10U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((8U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((4U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((2U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((1U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x1fU)))) + << 0xcU)) + | ((0x800U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)) + | ((0x400U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + << 3U)) + | ((0x3f0U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x15U)) + | (0xfU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 8U)))))) + : 0xdeadbeefU) + : 0xdeadbeefU)))) + : 0xdeadbeefU) + : ( + (0x20U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0x10U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((8U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((4U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((2U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((1U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x1fU)))) + << 0xcU)) + | ((0xfe0U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)) + | (0x1fU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 7U)))) + : 0xdeadbeefU) + : 0xdeadbeefU)))) + : + ((0x10U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((8U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((4U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((2U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((1U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__alu_tempp) + >> 0xbU)))) + << 0xcU)) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__alu_tempp)) + : 0xdeadbeefU) + : 0xdeadbeefU))) + : + ((8U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((4U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : + ((2U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((1U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x1fU)))) + << 0xcU)) + | (0xfffU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))) + : 0xdeadbeefU) + : 0xdeadbeefU)))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak + = ((0x73U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__jal_sys_jal) + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U])); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (1U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (2U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (3U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (4U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (5U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (6U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_wspawn + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (7U == (0xfU & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))))); + vlTOPp->Vortex__DOT__vx_decode__DOT__real_zero_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (1U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (2U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (3U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (4U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (5U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (6U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) + & (7U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + // ALWAYS at VX_decode.v:451 + if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_jal_offset + = ((8U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU : ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0xdeadbeefU + : ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((1U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + (((0U + == + (7U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU))) + & (2U + > + (0xfffU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))) + ? 0xb0000000U + : 0xdeadbeefU) + : 0xdeadbeefU) + : 0xdeadbeefU))); + } else { + if ((8U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_jal_offset + = ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((0xffe00000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x1fU)))) + << 0x15U)) + | ((0x100000U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xbU)) + | ((0xff000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + | ((0x800U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 9U)) + | (0x7feU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))))) + : 0xdeadbeefU) : 0xdeadbeefU); + } else { + if ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt))) { + vlTOPp->Vortex__DOT__decode_jal_offset = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_jal_offset = 0xdeadbeefU; + } + } else { + vlTOPp->Vortex__DOT__decode_jal_offset = 0xdeadbeefU; + } + } + } else { + vlTOPp->Vortex__DOT__decode_jal_offset + = ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((0xfffff000U + & (VL_NEGATE_I((IData)( + (1U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x1fU)))) + << 0xcU)) + | (0xfffU & + (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))) + : 0xdeadbeefU) : 0xdeadbeefU) + : 0xdeadbeefU); + } + } + } else { + vlTOPp->Vortex__DOT__decode_jal_offset = 0xdeadbeefU; + } + } else { + vlTOPp->Vortex__DOT__decode_jal_offset = 0xdeadbeefU; + } + // ALWAYS at VX_decode.v:451 + if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_jal = ( + (~ + (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 3U)) + & ((~ + (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 2U)) + & ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 1U) + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__jal_sys_jal) + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]))))); + } else { + if ((8U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_jal + = ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 1U) & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U])); + } else { + if ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt))) { + vlTOPp->Vortex__DOT__decode_jal + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]; + } + } else { + vlTOPp->Vortex__DOT__decode_jal = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_jal = 0U; + } + } + } else { + vlTOPp->Vortex__DOT__decode_jal + = ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 2U) & ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 1U) & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]))); + } + } + } else { + vlTOPp->Vortex__DOT__decode_jal = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_jal = 0U; + } + // ALWAYS at VX_decode.v:519 + if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } else { + if ((8U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } else { + if ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt))) { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } + } + } else { + vlTOPp->Vortex__DOT__decode_branch_type + = ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0U : ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((0x4000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((0x2000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 6U + : 5U) + : + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 4U + : 3U)) + : ((0x2000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 0U + : + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 2U + : 1U))) + : 0U) : 0U)); + } + } + } else { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_branch_type = 0U; + } + // ALWAYS at VX_decode.v:519 + if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_branch_stall = 0U; + } else { + if ((8U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + vlTOPp->Vortex__DOT__decode_branch_stall + = ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 1U) & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U])); + } else { + if ((2U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if ((1U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt))) { + vlTOPp->Vortex__DOT__decode_branch_stall + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]; + } + } else { + vlTOPp->Vortex__DOT__decode_branch_stall = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_branch_stall = 0U; + } + } + } else { + vlTOPp->Vortex__DOT__decode_branch_stall + = ((4U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 1U) & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U])) : + ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 1U) & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid + [0U]))); + } + } + } else { + vlTOPp->Vortex__DOT__decode_branch_stall = 0U; + } + } else { + vlTOPp->Vortex__DOT__decode_branch_stall = 0U; + } + vlTOPp->Vortex__DOT__decode_change_mask = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt)); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd + = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)))) & (0U + != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) + & ((IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num) + == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd + = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))) & (0U + != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd))) + & ((IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num) + == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num))); + vlTOPp->out_ebreak = ((0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak)); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[0U] + = (((0U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall)) + | (1U != (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__real_zero_isclone)); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[1U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[2U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[3U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[4U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[5U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[6U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall[7U] + = ((((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.__PVT__clone_state_stall)) + | (1U != (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.__PVT__clone_state_stall))) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone)) + | (((0U == (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)) + & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_wspawn)) + | (1U < (IData)(vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.__PVT__wspawn_state_stall)))); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu + = ((0x63U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? ((5U > (IData)(vlTOPp->Vortex__DOT__decode_branch_type)) + ? 1U : 0xaU) : ((0x37U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? 0xbU : ((0x17U == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? 0xcU : + ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr) + ? ((1U + == + (3U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU))) + ? 0xdU + : + ((2U + == + (3U + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xcU))) + ? 0xeU + : 0xfU)) + : (((0x23U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + | (3U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))) + ? 0U + : + ((0x4000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0x2000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 9U + : 8U) + : + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0U + == + (0x7fU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x19U))) + ? 6U + : 7U) + : 5U)) + : + ((0x2000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 4U + : 3U) + : + ((0x1000U + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) + ? 2U + : + ((0x13U + == + (0x7fU + & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? 0U + : + ((0U + == + (0x7fU + & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x19U))) + ? 0U + : 1U)))))))))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (1U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (2U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (3U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (4U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (5U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (6U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_change_mask + = ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) + & (7U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd + = (((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)))) & (0U + != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) + & ((IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num) + == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd))); + vlTOPp->Vortex__DOT__forwarding_fwd_stall = ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)) + & (2U + == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))) + | (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) + & (2U + == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)))); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd + = (((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U)))) & (0U + != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd))) + & ((IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num) + == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))); + // ALWAYS at VX_decode.v:276 + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [1U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [2U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [3U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [4U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [5U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [6U]); + vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | vlTOPp->Vortex__DOT__vx_decode__DOT__glob_clone_stall + [7U]); + vlTOPp->Vortex__DOT__forwarding_src1_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)); + vlTOPp->Vortex__DOT__forwarding_src2_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)); + vlTOPp->Vortex__DOT__vx_fetch__DOT__add_warp = + (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall))); + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling + = (((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) + | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)) + | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall)); + vlTOPp->Vortex__DOT__vx_fetch__DOT__stall = ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall) + | (IData)(vlTOPp->Vortex__DOT__decode_branch_stall)) + | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) + | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); + vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp + = (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_out_clone_stall))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (0U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (1U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (2U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (3U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (4U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (5U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (6U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); + vlTOPp->Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_stall + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + | (7U != (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))); +} + +VL_INLINE_OPT void VVortex::_combo__TOP__10(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_combo__TOP__10\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[3U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [3U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [3U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [3U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [3U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [3U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [3U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [3U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [2U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [2U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [2U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [2U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [2U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [2U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [2U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [1U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [1U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [1U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [0U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [0U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [0U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [0U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [0U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[3U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [3U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [3U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [3U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [3U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [3U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [3U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [3U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [2U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [2U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [2U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [2U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [2U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [2U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [2U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [1U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [1U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [1U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [1U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [1U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [1U]))); + vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[0U] + = ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd) + ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next + [0U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)) + ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data + [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result + [0U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd) + ? ((3U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next + [0U] + : + ((2U + == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + ? + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data + [0U] + : + vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result + [0U])) + : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result + [0U]))); + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__forwarding_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__forwarding_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[0U] + = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data + [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register + [0U])); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[1U] + = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register + [1U])); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[2U] + = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data + [2U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register + [2U])); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[3U] + = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data + [3U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register + [3U])); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src1_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src1_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src1_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src1_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[0U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data + [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register + [0U]); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[1U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data + [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register + [1U]); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[2U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data + [2U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register + [2U]); + vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[3U] + = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data + [3U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register + [3U]); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src2_fwd_data[3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data + [3U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src2_fwd_data[2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data + [2U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src2_fwd_data[1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data + [1U]; + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.in_src2_fwd_data[0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[0U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[0U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[0U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_a_reg_data[0U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data + [0U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[0U][3U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data + [3U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[0U][2U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data + [2U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[0U][1U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data + [1U]; + vlTOPp->Vortex__DOT__vx_decode__DOT__glob_b_reg_data[0U][0U] + = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data + [0U]; +} + +void VVortex::_eval(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_eval\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) { + vlTOPp->_sequent__TOP__4(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__15(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one__16(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one__17(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one__18(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one__19(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one__20(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one__21(vlSymsp); + vlTOPp->_sequent__TOP__5(vlSymsp); + } + if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk))) + | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) { + vlTOPp->_sequent__TOP__6(vlSymsp); + } + if (((~ (IData)(vlTOPp->clk)) & (IData)(vlTOPp->__Vclklast__TOP__clk))) { + vlTOPp->_sequent__TOP__7(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__22(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__22(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__22(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__22(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__22(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__22(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one._sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__22(vlSymsp); + } + vlTOPp->_combo__TOP__8(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__29(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__29(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__29(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__29(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__29(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__29(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__29(vlSymsp); + if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk))) + | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) { + vlTOPp->_sequent__TOP__9(vlSymsp); + } + vlTOPp->_combo__TOP__10(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__36(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__36(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__36(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__36(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__36(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__36(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one._combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__36(vlSymsp); + vlTOPp->_settle__TOP__3(vlSymsp); + // Final + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; + vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset; +} + +void VVortex::_eval_initial(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_eval_initial\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_initial__TOP__1(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one._initial__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__1(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one._initial__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__1(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one._initial__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__1(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one._initial__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__1(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one._initial__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__1(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one._initial__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__1(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one._initial__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__1(vlSymsp); + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; + vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset; +} + +void VVortex::final() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::final\n"); ); + // Variables + VVortex__Syms* __restrict vlSymsp = this->__VlSymsp; + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void VVortex::_eval_settle(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_eval_settle\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_settle__TOP__2(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one._settle__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__8(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one._settle__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__8(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one._settle__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__8(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one._settle__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__8(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one._settle__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__8(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one._settle__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__8(vlSymsp); + vlSymsp->TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one._settle__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__8(vlSymsp); + vlTOPp->_settle__TOP__3(vlSymsp); +} + +VL_INLINE_OPT QData VVortex::_change_request(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_change_request\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // Change detection + QData __req = false; // Logically a bool + return __req; +} + +#ifdef VL_DEBUG +void VVortex::_eval_debug_assertions() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((clk & 0xfeU))) { + Verilated::overWidthError("clk");} + if (VL_UNLIKELY((reset & 0xfeU))) { + Verilated::overWidthError("reset");} +} +#endif // VL_DEBUG + +void VVortex::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_ctor_var_reset\n"); ); + // Body + clk = VL_RAND_RESET_I(1); + reset = VL_RAND_RESET_I(1); + fe_instruction = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32); + }} + curr_PC = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32); + }} + out_cache_driver_in_mem_read = VL_RAND_RESET_I(3); + out_cache_driver_in_mem_write = VL_RAND_RESET_I(3); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + out_cache_driver_in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32); + }} + out_ebreak = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__fetch_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__f_d_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__decode_branch_stall = VL_RAND_RESET_I(1); + Vortex__DOT__decode_csr_address = VL_RAND_RESET_I(12); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__decode_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__decode_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__decode_itype_immed = VL_RAND_RESET_I(32); + Vortex__DOT__decode_branch_type = VL_RAND_RESET_I(3); + Vortex__DOT__decode_jal = VL_RAND_RESET_I(1); + Vortex__DOT__decode_jal_offset = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__decode_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__decode_change_mask = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__decode_thread_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__d_e_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__d_e_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__d_e_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__execute_branch_stall = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__execute_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__execute_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__execute_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__e_m_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__e_m_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__e_m_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__memory_branch_dir = VL_RAND_RESET_I(1); + Vortex__DOT__memory_branch_dest = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__memory_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__memory_mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__memory_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__m_w_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__m_w_mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__m_w_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__writeback_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__csr_decode_csr_data = VL_RAND_RESET_I(32); + Vortex__DOT__forwarding_fwd_stall = VL_RAND_RESET_I(1); + Vortex__DOT__forwarding_src1_fwd = VL_RAND_RESET_I(1); + Vortex__DOT__forwarding_src2_fwd = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__forwarding_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__forwarding_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_fetch__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_decode__out_thread_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_decode__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_decode__in_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_decode__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_execute__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_execute__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_execute__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_memory__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_memory__out_mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_memory__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_memory__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_memory__in_rd2[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_memory__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_writeback__out_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_fetch__DOT__stall = VL_RAND_RESET_I(1); + Vortex__DOT__vx_fetch__DOT__warp_num = VL_RAND_RESET_I(4); + Vortex__DOT__vx_fetch__DOT__warp_state = VL_RAND_RESET_I(4); + Vortex__DOT__vx_fetch__DOT__warp_count = VL_RAND_RESET_I(4); + Vortex__DOT__vx_fetch__DOT__add_warp = VL_RAND_RESET_I(1); + Vortex__DOT__vx_fetch__DOT__remove_warp = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__warp_glob_pc[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + { int __Vi1=0; for (; __Vi1<4; ++__Vi1) { + Vortex__DOT__vx_fetch__DOT__warp_glob_valid[__Vi0][__Vi1] = VL_RAND_RESET_I(1); + }} + }} + Vortex__DOT__vx_fetch__DOT__out_PC_var = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__out_valid_var[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask = VL_RAND_RESET_I(1); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_stall = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_change_mask = VL_RAND_RESET_I(1); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_stall = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_change_mask = VL_RAND_RESET_I(1); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_stall = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_change_mask = VL_RAND_RESET_I(1); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_stall = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_change_mask = VL_RAND_RESET_I(1); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_stall = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_change_mask = VL_RAND_RESET_I(1); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_stall = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_change_mask = VL_RAND_RESET_I(1); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_stall = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_change_mask = VL_RAND_RESET_I(1); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_stall = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__real_PC = VL_RAND_RESET_I(32); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__real_PC = VL_RAND_RESET_I(32); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__real_PC = VL_RAND_RESET_I(32); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__real_PC = VL_RAND_RESET_I(32); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__real_PC = VL_RAND_RESET_I(32); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__real_PC = VL_RAND_RESET_I(32); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__real_PC = VL_RAND_RESET_I(32); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__real_PC = VL_RAND_RESET_I(32); + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_f_d_reg__DOT__instruction = VL_RAND_RESET_I(32); + Vortex__DOT__vx_f_d_reg__DOT__curr_PC = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_f_d_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_f_d_reg__DOT__warp_num = VL_RAND_RESET_I(4); + Vortex__DOT__vx_decode__DOT__is_itype = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__is_csr = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__is_clone = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__is_jalrs = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__is_jmprt = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__is_wspawn = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__jal_sys_jal = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__alu_tempp = VL_RAND_RESET_I(12); + Vortex__DOT__vx_decode__DOT__mul_alu = VL_RAND_RESET_I(5); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__w0_t0_registers[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + { int __Vi1=0; for (; __Vi1<4; ++__Vi1) { + Vortex__DOT__vx_decode__DOT__glob_a_reg_data[__Vi0][__Vi1] = VL_RAND_RESET_I(32); + }} + }} + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + { int __Vi1=0; for (; __Vi1<4; ++__Vi1) { + Vortex__DOT__vx_decode__DOT__glob_b_reg_data[__Vi0][__Vi1] = VL_RAND_RESET_I(32); + }} + }} + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__glob_clone_stall[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_decode__DOT__real_zero_isclone = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_decode__DOT__temp_out_clone_stall = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_decode__DOT__is_ebreak = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__temp_final_alu = VL_RAND_RESET_I(5); + Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_wspawn = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_wspawn = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_wspawn = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_wspawn = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_wspawn = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_wspawn = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_wspawn = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall = VL_RAND_RESET_I(6); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data = VL_RAND_RESET_I(32); + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data = VL_RAND_RESET_I(32); + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data = VL_RAND_RESET_I(32); + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data = VL_RAND_RESET_I(32); + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_d_e_reg__DOT__rd = VL_RAND_RESET_I(5); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_d_e_reg__DOT__alu_op = VL_RAND_RESET_I(5); + Vortex__DOT__vx_d_e_reg__DOT__wb = VL_RAND_RESET_I(2); + Vortex__DOT__vx_d_e_reg__DOT__PC_next_out = VL_RAND_RESET_I(32); + Vortex__DOT__vx_d_e_reg__DOT__rs2_src = VL_RAND_RESET_I(1); + Vortex__DOT__vx_d_e_reg__DOT__itype_immed = VL_RAND_RESET_I(32); + Vortex__DOT__vx_d_e_reg__DOT__mem_read = VL_RAND_RESET_I(3); + Vortex__DOT__vx_d_e_reg__DOT__mem_write = VL_RAND_RESET_I(3); + Vortex__DOT__vx_d_e_reg__DOT__branch_type = VL_RAND_RESET_I(3); + Vortex__DOT__vx_d_e_reg__DOT__upper_immed = VL_RAND_RESET_I(20); + Vortex__DOT__vx_d_e_reg__DOT__csr_address = VL_RAND_RESET_I(12); + Vortex__DOT__vx_d_e_reg__DOT__is_csr = VL_RAND_RESET_I(1); + Vortex__DOT__vx_d_e_reg__DOT__csr_mask = VL_RAND_RESET_I(32); + Vortex__DOT__vx_d_e_reg__DOT__curr_PC = VL_RAND_RESET_I(32); + Vortex__DOT__vx_d_e_reg__DOT__jal = VL_RAND_RESET_I(1); + Vortex__DOT__vx_d_e_reg__DOT__jal_offset = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_d_e_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_d_e_reg__DOT__valid_z[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_d_e_reg__DOT__warp_num = VL_RAND_RESET_I(4); + Vortex__DOT__vx_d_e_reg__DOT__stalling = VL_RAND_RESET_I(1); + Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32); + Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32); + Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32); + Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result = VL_RAND_RESET_I(32); + Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32); + Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64); + Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32); + Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64); + Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32); + Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64); + Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2 = VL_RAND_RESET_I(32); + Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result = VL_RAND_RESET_Q(64); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_e_m_reg__DOT__alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_e_m_reg__DOT__rd = VL_RAND_RESET_I(5); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_e_m_reg__DOT__wb = VL_RAND_RESET_I(2); + Vortex__DOT__vx_e_m_reg__DOT__PC_next = VL_RAND_RESET_I(32); + Vortex__DOT__vx_e_m_reg__DOT__mem_read = VL_RAND_RESET_I(3); + Vortex__DOT__vx_e_m_reg__DOT__mem_write = VL_RAND_RESET_I(3); + Vortex__DOT__vx_e_m_reg__DOT__csr_address = VL_RAND_RESET_I(12); + Vortex__DOT__vx_e_m_reg__DOT__is_csr = VL_RAND_RESET_I(1); + Vortex__DOT__vx_e_m_reg__DOT__csr_result = VL_RAND_RESET_I(32); + Vortex__DOT__vx_e_m_reg__DOT__curr_PC = VL_RAND_RESET_I(32); + Vortex__DOT__vx_e_m_reg__DOT__branch_offset = VL_RAND_RESET_I(32); + Vortex__DOT__vx_e_m_reg__DOT__branch_type = VL_RAND_RESET_I(3); + Vortex__DOT__vx_e_m_reg__DOT__jal = VL_RAND_RESET_I(1); + Vortex__DOT__vx_e_m_reg__DOT__jal_dest = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_e_m_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_e_m_reg__DOT__warp_num = VL_RAND_RESET_I(4); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_m_w_reg__DOT__alu_result[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_m_w_reg__DOT__mem_result[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_m_w_reg__DOT__rd = VL_RAND_RESET_I(5); + Vortex__DOT__vx_m_w_reg__DOT__wb = VL_RAND_RESET_I(2); + Vortex__DOT__vx_m_w_reg__DOT__PC_next = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_m_w_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1); + }} + Vortex__DOT__vx_m_w_reg__DOT__warp_num = VL_RAND_RESET_I(4); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_writeback__DOT__out_pc_data[__Vi0] = VL_RAND_RESET_I(32); + }} + Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd = VL_RAND_RESET_I(1); + Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd = VL_RAND_RESET_I(1); + Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd = VL_RAND_RESET_I(1); + Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd = VL_RAND_RESET_I(1); + Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd = VL_RAND_RESET_I(1); + Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<1025; ++__Vi0) { + Vortex__DOT__vx_csr_handler__DOT__csr[__Vi0] = VL_RAND_RESET_I(12); + }} + Vortex__DOT__vx_csr_handler__DOT__cycle = VL_RAND_RESET_Q(64); + Vortex__DOT__vx_csr_handler__DOT__instret = VL_RAND_RESET_Q(64); + Vortex__DOT__vx_csr_handler__DOT__decode_csr_address = VL_RAND_RESET_I(12); + Vortex__DOT__vx_csr_handler__DOT____Vlvbound1 = VL_RAND_RESET_I(12); + __Vtableidx1 = VL_RAND_RESET_I(3); + __Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[0] = 0x10U; + __Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[1] = 0x11U; + __Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[2] = 0x12U; + __Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[3] = 0x13U; + __Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[4] = 0x14U; + __Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[5] = 0x15U; + __Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[6] = 0x16U; + __Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[7] = 0x17U; +} diff --git a/rtl/obj_dir/VVortex.h b/rtl/obj_dir/VVortex.h new file mode 100644 index 00000000..04c0976e --- /dev/null +++ b/rtl/obj_dir/VVortex.h @@ -0,0 +1,489 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary design header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef _VVortex_H_ +#define _VVortex_H_ + +#include "verilated.h" + +class VVortex__Syms; +class VVortex_VX_context_slave; + +//---------- + +VL_MODULE(VVortex) { + public: + // CELLS + // Public to allow access to /*verilator_public*/ items; + // otherwise the application code can consider these internals. + VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one; + VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one; + VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one; + VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one; + VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one; + VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one; + VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one; + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + // Begin mtask footprint all: + VL_IN8(clk,0,0); + VL_IN8(reset,0,0); + VL_OUT8(out_cache_driver_in_mem_read,2,0); + VL_OUT8(out_cache_driver_in_mem_write,2,0); + VL_OUT8(out_ebreak,0,0); + VL_IN(fe_instruction,31,0); + VL_OUT(curr_PC,31,0); + VL_IN(in_cache_driver_out_data[4],31,0); + VL_OUT(out_cache_driver_in_address[4],31,0); + VL_OUT8(out_cache_driver_in_valid[4],0,0); + VL_OUT(out_cache_driver_in_data[4],31,0); + + // LOCAL SIGNALS + // Internals; generally not touched by application code + // Anonymous structures to workaround compiler member-count bugs + struct { + // Begin mtask footprint all: + VL_SIG8(Vortex__DOT__decode_branch_stall,0,0); + VL_SIG8(Vortex__DOT__decode_branch_type,2,0); + VL_SIG8(Vortex__DOT__decode_jal,0,0); + VL_SIG8(Vortex__DOT__decode_change_mask,0,0); + VL_SIG8(Vortex__DOT__execute_branch_stall,0,0); + VL_SIG8(Vortex__DOT__memory_branch_dir,0,0); + VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0); + VL_SIG8(Vortex__DOT__forwarding_src1_fwd,0,0); + VL_SIG8(Vortex__DOT__forwarding_src2_fwd,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_num,3,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_state,3,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_count,3,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__add_warp,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__remove_warp,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_stall,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_change_mask,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_stall,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_change_mask,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_stall,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_change_mask,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_stall,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_change_mask,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_stall,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_change_mask,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_stall,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_change_mask,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_stall,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_change_mask,0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_stall,0,0); + VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__warp_num,3,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__is_clone,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jalrs,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jmprt,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__is_wspawn,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__jal_sys_jal,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__real_zero_isclone,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_out_clone_stall,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__is_ebreak,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_final_alu,4,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_wspawn,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_wspawn,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_wspawn,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_wspawn,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_wspawn,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_wspawn,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_wspawn,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone,0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall,5,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__alu_op,4,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__wb,1,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rs2_src,0,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_read,2,0); + }; + struct { + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_write,2,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__branch_type,2,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__is_csr,0,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__jal,0,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__warp_num,3,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__stalling,0,0); + VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__rd,4,0); + VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__wb,1,0); + VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__mem_read,2,0); + VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__mem_write,2,0); + VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__is_csr,0,0); + VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__branch_type,2,0); + VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__jal,0,0); + VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__warp_num,3,0); + VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__rd,4,0); + VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__wb,1,0); + VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__warp_num,3,0); + VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0); + VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0); + VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0); + VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd,0,0); + VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd,0,0); + VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd,0,0); + VL_SIG16(Vortex__DOT__decode_csr_address,11,0); + VL_SIG16(Vortex__DOT__vx_decode__DOT__alu_tempp,11,0); + VL_SIG16(Vortex__DOT__vx_d_e_reg__DOT__csr_address,11,0); + VL_SIG16(Vortex__DOT__vx_e_m_reg__DOT__csr_address,11,0); + VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0); + VL_SIG(Vortex__DOT__decode_itype_immed,31,0); + VL_SIG(Vortex__DOT__decode_jal_offset,31,0); + VL_SIG(Vortex__DOT__memory_branch_dest,31,0); + VL_SIG(Vortex__DOT__csr_decode_csr_data,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__out_PC_var,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__real_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__real_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__real_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__real_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__real_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__real_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__real_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__real_PC,31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC,31,0); + VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0); + VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2,31,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0); + }; + struct { + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0); + VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0); + VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0); + VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result,63,0); + VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0); + VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result,63,0); + VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0); + VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0); + VL_SIG8(Vortex__DOT__fetch_valid[4],0,0); + VL_SIG8(Vortex__DOT__f_d_valid[4],0,0); + VL_SIG(Vortex__DOT__decode_a_reg_data[4],31,0); + VL_SIG(Vortex__DOT__decode_b_reg_data[4],31,0); + VL_SIG8(Vortex__DOT__decode_valid[4],0,0); + VL_SIG8(Vortex__DOT__decode_thread_mask[4],0,0); + VL_SIG(Vortex__DOT__d_e_a_reg_data[4],31,0); + VL_SIG(Vortex__DOT__d_e_b_reg_data[4],31,0); + VL_SIG8(Vortex__DOT__d_e_valid[4],0,0); + VL_SIG(Vortex__DOT__execute_alu_result[4],31,0); + VL_SIG(Vortex__DOT__execute_b_reg_data[4],31,0); + VL_SIG8(Vortex__DOT__execute_valid[4],0,0); + VL_SIG(Vortex__DOT__e_m_alu_result[4],31,0); + VL_SIG(Vortex__DOT__e_m_b_reg_data[4],31,0); + VL_SIG8(Vortex__DOT__e_m_valid[4],0,0); + VL_SIG(Vortex__DOT__memory_alu_result[4],31,0); + VL_SIG(Vortex__DOT__memory_mem_result[4],31,0); + VL_SIG8(Vortex__DOT__memory_valid[4],0,0); + VL_SIG(Vortex__DOT__m_w_alu_result[4],31,0); + VL_SIG(Vortex__DOT__m_w_mem_result[4],31,0); + VL_SIG8(Vortex__DOT__m_w_valid[4],0,0); + VL_SIG(Vortex__DOT__writeback_write_data[4],31,0); + VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[4],31,0); + VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[4],31,0); + VL_SIG(Vortex__DOT__vx_fetch__DOT__warp_glob_pc[8],31,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_glob_valid[8][4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__out_valid_var[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0); + VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[4],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__w0_t0_registers[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__glob_a_reg_data[8][4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__glob_b_reg_data[8][4],31,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__glob_clone_stall[8],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[4],31,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[4],0,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[4],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[32],31,0); + }; + struct { + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[4],31,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[4],0,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[4],31,0); + VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[4],0,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[4],31,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[4],31,0); + VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[4],0,0); + VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[4],31,0); + VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[4],31,0); + VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[4],0,0); + VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[4],31,0); + VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[4],31,0); + VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[4],31,0); + VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[4],31,0); + VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[1025],11,0); + }; + + // LOCAL VARIABLES + // Internals; generally not touched by application code + // Anonymous structures to workaround compiler member-count bugs + struct { + // Begin mtask footprint all: + VL_SIG8(__Vtableidx1,2,0); + VL_SIG8(__Vclklast__TOP__clk,0,0); + VL_SIG8(__Vclklast__TOP__reset,0,0); + VL_SIG16(Vortex__DOT__vx_csr_handler__DOT____Vlvbound1,11,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0); + VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[4],0,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[4],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[4],0,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[4],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_thread_mask[4],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[4],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[4],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[4],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[4],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[4],0,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[4],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[4],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[4],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[4],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[4],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[4],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[4],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[4],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[4],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[4],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[4],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[4],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[4],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[4],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[4],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[4],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[4],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[4],31,0); + VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[4],0,0); + VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[4],31,0); + VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[4],0,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[4],31,0); + }; + struct { + VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[4],31,0); + VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[4],31,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid[4],0,0); + VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask[4],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[4],31,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[4],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid[4],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid[4],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid[4],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid[4],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data[4],31,0); + }; + struct { + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid[4],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid[4],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0); + VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid[4],0,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[32],31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[32],31,0); + }; + static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0); + + // INTERNAL VARIABLES + // Internals; generally not touched by application code + VVortex__Syms* __VlSymsp; // Symbol table + + // PARAMETERS + // Parameters marked /*verilator public*/ for use by application code + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(VVortex); ///< Copying not allowed + public: + /// Construct the model; called by application code + /// The special name may be used to make a wrapper with a + /// single model invisible with respect to DPI scope names. + VVortex(const char* name="TOP"); + /// Destroy the model; called (often implicitly) by application code + ~VVortex(); + + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval(); + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + + // INTERNAL METHODS + private: + static void _eval_initial_loop(VVortex__Syms* __restrict vlSymsp); + public: + void __Vconfigure(VVortex__Syms* symsp, bool first); + private: + static QData _change_request(VVortex__Syms* __restrict vlSymsp); + public: + static void _combo__TOP__10(VVortex__Syms* __restrict vlSymsp); + static void _combo__TOP__8(VVortex__Syms* __restrict vlSymsp); + private: + void _ctor_var_reset(); + public: + static void _eval(VVortex__Syms* __restrict vlSymsp); + private: +#ifdef VL_DEBUG + void _eval_debug_assertions(); +#endif // VL_DEBUG + public: + static void _eval_initial(VVortex__Syms* __restrict vlSymsp); + static void _eval_settle(VVortex__Syms* __restrict vlSymsp); + static void _initial__TOP__1(VVortex__Syms* __restrict vlSymsp); + static void _sequent__TOP__4(VVortex__Syms* __restrict vlSymsp); + static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp); + static void _sequent__TOP__6(VVortex__Syms* __restrict vlSymsp); + static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp); + static void _sequent__TOP__9(VVortex__Syms* __restrict vlSymsp); + static void _settle__TOP__2(VVortex__Syms* __restrict vlSymsp); + static void _settle__TOP__3(VVortex__Syms* __restrict vlSymsp); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git a/rtl/obj_dir/VVortex.mk b/rtl/obj_dir/VVortex.mk new file mode 100644 index 00000000..edc5fcca --- /dev/null +++ b/rtl/obj_dir/VVortex.mk @@ -0,0 +1,66 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable +# +# Execute this makefile from the object directory: +# make -f VVortex.mk + +default: VVortex + +### Constants... +# Perl executable (from $PERL) +PERL = perl +# Path to Verilator kit (from $VERILATOR_ROOT) +VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator +# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) +SYSTEMC_INCLUDE ?= +# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) +SYSTEMC_LIBDIR ?= + +### Switches... +# SystemC output mode? 0/1 (from --sc) +VM_SC = 0 +# Legacy or SystemC output mode? 0/1 (from --sc) +VM_SP_OR_SC = $(VM_SC) +# Deprecated +VM_PCLI = 1 +# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) +VM_SC_TARGET_ARCH = linux + +### Vars... +# Design prefix (from --prefix) +VM_PREFIX = VVortex +# Module prefix (from --prefix) +VM_MODPREFIX = VVortex +# User CFLAGS (from -CFLAGS on Verilator command line) +VM_USER_CFLAGS = \ + +# User LDLIBS (from -LDFLAGS on Verilator command line) +VM_USER_LDLIBS = \ + +# User .cpp files (from .cpp's on Verilator command line) +VM_USER_CLASSES = \ + test_bench \ + +# User .cpp directories (from .cpp's on Verilator command line) +VM_USER_DIR = \ + . \ + + +### Default rules... +# Include list of all generated classes +include VVortex_classes.mk +# Include global rules +include $(VERILATOR_ROOT)/include/verilated.mk + +### Executable rules... (from --exe) +VPATH += $(VM_USER_DIR) + +test_bench.o: test_bench.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< + +### Link rules... (from --exe) +VVortex: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a + $(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) + + +# Verilated -*- Makefile -*- diff --git a/rtl/obj_dir/VVortex_VX_context_slave.cpp b/rtl/obj_dir/VVortex_VX_context_slave.cpp new file mode 100644 index 00000000..e8e9c3e2 --- /dev/null +++ b/rtl/obj_dir/VVortex_VX_context_slave.cpp @@ -0,0 +1,8879 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See VVortex.h for the primary calling header + +#include "VVortex_VX_context_slave.h" +#include "VVortex__Syms.h" + + +//-------------------- +// STATIC VARIABLES + + +//-------------------- + +VL_CTOR_IMP(VVortex_VX_context_slave) { + // Reset internal values + // Reset structure values + _ctor_var_reset(); +} + +void VVortex_VX_context_slave::__Vconfigure(VVortex__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +VVortex_VX_context_slave::~VVortex_VX_context_slave() { +} + +//-------------------- +// Internal Methods + +void VVortex_VX_context_slave::_initial__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__1(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_context_slave::_initial__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__1\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // INITIAL at VX_context_slave.v:38 + // INITIAL at VX_context_slave.v:39 + // INITIAL at VX_context_slave.v:41 + this->__PVT__clone_state_stall = 0U; + this->__PVT__wspawn_state_stall = 0U; +} + +void VVortex_VX_context_slave::_settle__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__8(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_context_slave::_settle__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__8\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__Vcellout__vx_register_file_master__out_regs[0x1fU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1fU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1eU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1eU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1dU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1dU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1cU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1cU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1bU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1bU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1aU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1aU]; + this->__Vcellout__vx_register_file_master__out_regs[0x19U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x19U]; + this->__Vcellout__vx_register_file_master__out_regs[0x18U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x18U]; + this->__Vcellout__vx_register_file_master__out_regs[0x17U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x17U]; + this->__Vcellout__vx_register_file_master__out_regs[0x16U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x16U]; + this->__Vcellout__vx_register_file_master__out_regs[0x15U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x15U]; + this->__Vcellout__vx_register_file_master__out_regs[0x14U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x14U]; + this->__Vcellout__vx_register_file_master__out_regs[0x13U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x13U]; + this->__Vcellout__vx_register_file_master__out_regs[0x12U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x12U]; + this->__Vcellout__vx_register_file_master__out_regs[0x11U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x11U]; + this->__Vcellout__vx_register_file_master__out_regs[0x10U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x10U]; + this->__Vcellout__vx_register_file_master__out_regs[0xfU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xfU]; + this->__Vcellout__vx_register_file_master__out_regs[0xeU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xeU]; + this->__Vcellout__vx_register_file_master__out_regs[0xdU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xdU]; + this->__Vcellout__vx_register_file_master__out_regs[0xcU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xcU]; + this->__Vcellout__vx_register_file_master__out_regs[0xbU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xbU]; + this->__Vcellout__vx_register_file_master__out_regs[0xaU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xaU]; + this->__Vcellout__vx_register_file_master__out_regs[9U] + = this->__PVT__vx_register_file_master__DOT__registers + [9U]; + this->__Vcellout__vx_register_file_master__out_regs[8U] + = this->__PVT__vx_register_file_master__DOT__registers + [8U]; + this->__Vcellout__vx_register_file_master__out_regs[7U] + = this->__PVT__vx_register_file_master__DOT__registers + [7U]; + this->__Vcellout__vx_register_file_master__out_regs[6U] + = this->__PVT__vx_register_file_master__DOT__registers + [6U]; + this->__Vcellout__vx_register_file_master__out_regs[5U] + = this->__PVT__vx_register_file_master__DOT__registers + [5U]; + this->__Vcellout__vx_register_file_master__out_regs[4U] + = this->__PVT__vx_register_file_master__DOT__registers + [4U]; + this->__Vcellout__vx_register_file_master__out_regs[3U] + = this->__PVT__vx_register_file_master__DOT__registers + [3U]; + this->__Vcellout__vx_register_file_master__out_regs[2U] + = this->__PVT__vx_register_file_master__DOT__registers + [2U]; + this->__Vcellout__vx_register_file_master__out_regs[1U] + = this->__PVT__vx_register_file_master__DOT__registers + [1U]; + this->__Vcellout__vx_register_file_master__out_regs[0U] + = this->__PVT__vx_register_file_master__DOT__registers + [0U]; + this->__PVT__rd1_register[0U] = this->__Vcellout__vx_register_file_master__out_src1_data; + this->__PVT__rd1_register[1U] = this->__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data; + this->__PVT__rd1_register[2U] = this->__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data; + this->__PVT__rd1_register[3U] = this->__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data; + this->__PVT__rd2_register[0U] = this->__Vcellout__vx_register_file_master__out_src2_data; + this->__PVT__rd2_register[1U] = this->__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data; + this->__PVT__rd2_register[2U] = this->__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data; + this->__PVT__rd2_register[3U] = this->__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x1fU] + = this->in_wspawn_regs[0x1fU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x1eU] + = this->in_wspawn_regs[0x1eU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x1dU] + = this->in_wspawn_regs[0x1dU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x1cU] + = this->in_wspawn_regs[0x1cU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x1bU] + = this->in_wspawn_regs[0x1bU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x1aU] + = this->in_wspawn_regs[0x1aU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x19U] + = this->in_wspawn_regs[0x19U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x18U] + = this->in_wspawn_regs[0x18U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x17U] + = this->in_wspawn_regs[0x17U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x16U] + = this->in_wspawn_regs[0x16U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x15U] + = this->in_wspawn_regs[0x15U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x14U] + = this->in_wspawn_regs[0x14U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x13U] + = this->in_wspawn_regs[0x13U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x12U] + = this->in_wspawn_regs[0x12U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x11U] + = this->in_wspawn_regs[0x11U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x10U] + = this->in_wspawn_regs[0x10U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0xfU] + = this->in_wspawn_regs[0xfU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0xeU] + = this->in_wspawn_regs[0xeU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0xdU] + = this->in_wspawn_regs[0xdU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0xcU] + = this->in_wspawn_regs[0xcU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0xbU] + = this->in_wspawn_regs[0xbU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0xaU] + = this->in_wspawn_regs[0xaU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[9U] + = this->in_wspawn_regs[9U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[8U] + = this->in_wspawn_regs[8U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[7U] + = this->in_wspawn_regs[7U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[6U] + = this->in_wspawn_regs[6U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[5U] + = this->in_wspawn_regs[5U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[4U] + = this->in_wspawn_regs[4U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[3U] + = this->in_wspawn_regs[3U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[2U] + = this->in_wspawn_regs[2U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[1U] + = this->in_wspawn_regs[1U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0U] + = this->in_wspawn_regs[0U]; + this->__PVT__clone_regsiters[0x1fU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1fU]; + this->__PVT__clone_regsiters[0x1eU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1eU]; + this->__PVT__clone_regsiters[0x1dU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1dU]; + this->__PVT__clone_regsiters[0x1cU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1cU]; + this->__PVT__clone_regsiters[0x1bU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1bU]; + this->__PVT__clone_regsiters[0x1aU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1aU]; + this->__PVT__clone_regsiters[0x19U] = this->__Vcellout__vx_register_file_master__out_regs + [0x19U]; + this->__PVT__clone_regsiters[0x18U] = this->__Vcellout__vx_register_file_master__out_regs + [0x18U]; + this->__PVT__clone_regsiters[0x17U] = this->__Vcellout__vx_register_file_master__out_regs + [0x17U]; + this->__PVT__clone_regsiters[0x16U] = this->__Vcellout__vx_register_file_master__out_regs + [0x16U]; + this->__PVT__clone_regsiters[0x15U] = this->__Vcellout__vx_register_file_master__out_regs + [0x15U]; + this->__PVT__clone_regsiters[0x14U] = this->__Vcellout__vx_register_file_master__out_regs + [0x14U]; + this->__PVT__clone_regsiters[0x13U] = this->__Vcellout__vx_register_file_master__out_regs + [0x13U]; + this->__PVT__clone_regsiters[0x12U] = this->__Vcellout__vx_register_file_master__out_regs + [0x12U]; + this->__PVT__clone_regsiters[0x11U] = this->__Vcellout__vx_register_file_master__out_regs + [0x11U]; + this->__PVT__clone_regsiters[0x10U] = this->__Vcellout__vx_register_file_master__out_regs + [0x10U]; + this->__PVT__clone_regsiters[0xfU] = this->__Vcellout__vx_register_file_master__out_regs + [0xfU]; + this->__PVT__clone_regsiters[0xeU] = this->__Vcellout__vx_register_file_master__out_regs + [0xeU]; + this->__PVT__clone_regsiters[0xdU] = this->__Vcellout__vx_register_file_master__out_regs + [0xdU]; + this->__PVT__clone_regsiters[0xcU] = this->__Vcellout__vx_register_file_master__out_regs + [0xcU]; + this->__PVT__clone_regsiters[0xbU] = this->__Vcellout__vx_register_file_master__out_regs + [0xbU]; + this->__PVT__clone_regsiters[0xaU] = this->__Vcellout__vx_register_file_master__out_regs + [0xaU]; + this->__PVT__clone_regsiters[9U] = this->__Vcellout__vx_register_file_master__out_regs + [9U]; + this->__PVT__clone_regsiters[8U] = this->__Vcellout__vx_register_file_master__out_regs + [8U]; + this->__PVT__clone_regsiters[7U] = this->__Vcellout__vx_register_file_master__out_regs + [7U]; + this->__PVT__clone_regsiters[6U] = this->__Vcellout__vx_register_file_master__out_regs + [6U]; + this->__PVT__clone_regsiters[5U] = this->__Vcellout__vx_register_file_master__out_regs + [5U]; + this->__PVT__clone_regsiters[4U] = this->__Vcellout__vx_register_file_master__out_regs + [4U]; + this->__PVT__clone_regsiters[3U] = this->__Vcellout__vx_register_file_master__out_regs + [3U]; + this->__PVT__clone_regsiters[2U] = this->__Vcellout__vx_register_file_master__out_regs + [2U]; + this->__PVT__clone_regsiters[1U] = this->__Vcellout__vx_register_file_master__out_regs + [1U]; + this->__PVT__clone_regsiters[0U] = this->__Vcellout__vx_register_file_master__out_regs + [0U]; + this->out_a_reg_data[0U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? this->in_src1_fwd_data + [0U] : this->__PVT__rd1_register + [0U])); + this->out_a_reg_data[1U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? this->in_src1_fwd_data + [1U] : this->__PVT__rd1_register + [1U])); + this->out_a_reg_data[2U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? this->in_src1_fwd_data + [2U] : this->__PVT__rd1_register + [2U])); + this->out_a_reg_data[3U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? this->in_src1_fwd_data + [3U] : this->__PVT__rd1_register + [3U])); + this->out_b_reg_data[0U] = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? this->in_src2_fwd_data + [0U] : this->__PVT__rd2_register + [0U]); + this->out_b_reg_data[1U] = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? this->in_src2_fwd_data + [1U] : this->__PVT__rd2_register + [1U]); + this->out_b_reg_data[2U] = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? this->in_src2_fwd_data + [2U] : this->__PVT__rd2_register + [2U]); + this->out_b_reg_data[3U] = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? this->in_src2_fwd_data + [3U] : this->__PVT__rd2_register + [3U]); + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; +} + +VL_INLINE_OPT void VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__15(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__15\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__Vdly__wspawn_state_stall = this->__PVT__wspawn_state_stall; + this->__Vdly__clone_state_stall = this->__PVT__clone_state_stall; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 0U; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + // ALWAYS at VX_context_slave.v:119 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_wspawn) + & (0U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdly__wspawn_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = + (0x3fU & ((IData)(this->__PVT__wspawn_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_context_slave.v:104 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone) + & (0U == (IData)(this->__PVT__clone_state_stall)))) { + this->__Vdly__clone_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = (0x3fU + & ((IData)(this->__PVT__clone_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_register_file_master_slave.v:50 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[0U]) & (1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_wspawn)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v0 + = this->in_write_data[0U]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_wspawn) + & (2U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v1 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1fU]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 1U; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v2 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1eU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v3 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1dU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v4 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1cU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v5 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1bU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v6 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1aU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v7 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x19U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v8 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x18U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v9 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x17U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v10 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x16U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v11 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x15U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v12 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x14U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v13 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x13U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v14 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x12U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v15 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x11U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v16 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x10U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v17 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xfU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v18 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xeU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v19 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xdU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v20 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xcU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v21 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xbU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v22 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xaU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v23 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [9U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v24 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [8U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v25 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [7U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v26 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [6U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v27 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [5U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v28 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [4U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v29 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [3U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v30 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [2U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v31 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [1U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v32 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[3U]) & (1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[3U]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone) + & ((3U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (1U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[2U]) & (1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[2U]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone) + & ((2U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (1U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[1U]) & (1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[1U]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone) + & ((1U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (1U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYSPOST at VX_register_file_master_slave.v:53 + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v0) { + this->__PVT__vx_register_file_master__DOT__registers[this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v0; + } + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v1) { + this->__PVT__vx_register_file_master__DOT__registers[0x1fU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v1; + this->__PVT__vx_register_file_master__DOT__registers[0x1eU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v2; + this->__PVT__vx_register_file_master__DOT__registers[0x1dU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v3; + this->__PVT__vx_register_file_master__DOT__registers[0x1cU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v4; + this->__PVT__vx_register_file_master__DOT__registers[0x1bU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v5; + this->__PVT__vx_register_file_master__DOT__registers[0x1aU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v6; + this->__PVT__vx_register_file_master__DOT__registers[0x19U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v7; + this->__PVT__vx_register_file_master__DOT__registers[0x18U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v8; + this->__PVT__vx_register_file_master__DOT__registers[0x17U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v9; + this->__PVT__vx_register_file_master__DOT__registers[0x16U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v10; + this->__PVT__vx_register_file_master__DOT__registers[0x15U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v11; + this->__PVT__vx_register_file_master__DOT__registers[0x14U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v12; + this->__PVT__vx_register_file_master__DOT__registers[0x13U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v13; + this->__PVT__vx_register_file_master__DOT__registers[0x12U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v14; + this->__PVT__vx_register_file_master__DOT__registers[0x11U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v15; + this->__PVT__vx_register_file_master__DOT__registers[0x10U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v16; + this->__PVT__vx_register_file_master__DOT__registers[0xfU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v17; + this->__PVT__vx_register_file_master__DOT__registers[0xeU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v18; + this->__PVT__vx_register_file_master__DOT__registers[0xdU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v19; + this->__PVT__vx_register_file_master__DOT__registers[0xcU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v20; + this->__PVT__vx_register_file_master__DOT__registers[0xbU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v21; + this->__PVT__vx_register_file_master__DOT__registers[0xaU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v22; + this->__PVT__vx_register_file_master__DOT__registers[9U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v23; + this->__PVT__vx_register_file_master__DOT__registers[8U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v24; + this->__PVT__vx_register_file_master__DOT__registers[7U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v25; + this->__PVT__vx_register_file_master__DOT__registers[6U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v26; + this->__PVT__vx_register_file_master__DOT__registers[5U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v27; + this->__PVT__vx_register_file_master__DOT__registers[4U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v28; + this->__PVT__vx_register_file_master__DOT__registers[3U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v29; + this->__PVT__vx_register_file_master__DOT__registers[2U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v30; + this->__PVT__vx_register_file_master__DOT__registers[1U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v31; + this->__PVT__vx_register_file_master__DOT__registers[0U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v32; + } + this->__PVT__wspawn_state_stall = this->__Vdly__wspawn_state_stall; + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + this->__PVT__clone_state_stall = this->__Vdly__clone_state_stall; + this->__Vcellout__vx_register_file_master__out_regs[0x1fU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1fU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1eU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1eU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1dU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1dU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1cU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1cU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1bU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1bU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1aU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1aU]; + this->__Vcellout__vx_register_file_master__out_regs[0x19U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x19U]; + this->__Vcellout__vx_register_file_master__out_regs[0x18U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x18U]; + this->__Vcellout__vx_register_file_master__out_regs[0x17U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x17U]; + this->__Vcellout__vx_register_file_master__out_regs[0x16U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x16U]; + this->__Vcellout__vx_register_file_master__out_regs[0x15U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x15U]; + this->__Vcellout__vx_register_file_master__out_regs[0x14U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x14U]; + this->__Vcellout__vx_register_file_master__out_regs[0x13U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x13U]; + this->__Vcellout__vx_register_file_master__out_regs[0x12U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x12U]; + this->__Vcellout__vx_register_file_master__out_regs[0x11U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x11U]; + this->__Vcellout__vx_register_file_master__out_regs[0x10U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x10U]; + this->__Vcellout__vx_register_file_master__out_regs[0xfU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xfU]; + this->__Vcellout__vx_register_file_master__out_regs[0xeU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xeU]; + this->__Vcellout__vx_register_file_master__out_regs[0xdU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xdU]; + this->__Vcellout__vx_register_file_master__out_regs[0xcU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xcU]; + this->__Vcellout__vx_register_file_master__out_regs[0xbU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xbU]; + this->__Vcellout__vx_register_file_master__out_regs[0xaU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xaU]; + this->__Vcellout__vx_register_file_master__out_regs[9U] + = this->__PVT__vx_register_file_master__DOT__registers + [9U]; + this->__Vcellout__vx_register_file_master__out_regs[8U] + = this->__PVT__vx_register_file_master__DOT__registers + [8U]; + this->__Vcellout__vx_register_file_master__out_regs[7U] + = this->__PVT__vx_register_file_master__DOT__registers + [7U]; + this->__Vcellout__vx_register_file_master__out_regs[6U] + = this->__PVT__vx_register_file_master__DOT__registers + [6U]; + this->__Vcellout__vx_register_file_master__out_regs[5U] + = this->__PVT__vx_register_file_master__DOT__registers + [5U]; + this->__Vcellout__vx_register_file_master__out_regs[4U] + = this->__PVT__vx_register_file_master__DOT__registers + [4U]; + this->__Vcellout__vx_register_file_master__out_regs[3U] + = this->__PVT__vx_register_file_master__DOT__registers + [3U]; + this->__Vcellout__vx_register_file_master__out_regs[2U] + = this->__PVT__vx_register_file_master__DOT__registers + [2U]; + this->__Vcellout__vx_register_file_master__out_regs[1U] + = this->__PVT__vx_register_file_master__DOT__registers + [1U]; + this->__Vcellout__vx_register_file_master__out_regs[0U] + = this->__PVT__vx_register_file_master__DOT__registers + [0U]; + this->__PVT__clone_regsiters[0x1fU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1fU]; + this->__PVT__clone_regsiters[0x1eU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1eU]; + this->__PVT__clone_regsiters[0x1dU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1dU]; + this->__PVT__clone_regsiters[0x1cU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1cU]; + this->__PVT__clone_regsiters[0x1bU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1bU]; + this->__PVT__clone_regsiters[0x1aU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1aU]; + this->__PVT__clone_regsiters[0x19U] = this->__Vcellout__vx_register_file_master__out_regs + [0x19U]; + this->__PVT__clone_regsiters[0x18U] = this->__Vcellout__vx_register_file_master__out_regs + [0x18U]; + this->__PVT__clone_regsiters[0x17U] = this->__Vcellout__vx_register_file_master__out_regs + [0x17U]; + this->__PVT__clone_regsiters[0x16U] = this->__Vcellout__vx_register_file_master__out_regs + [0x16U]; + this->__PVT__clone_regsiters[0x15U] = this->__Vcellout__vx_register_file_master__out_regs + [0x15U]; + this->__PVT__clone_regsiters[0x14U] = this->__Vcellout__vx_register_file_master__out_regs + [0x14U]; + this->__PVT__clone_regsiters[0x13U] = this->__Vcellout__vx_register_file_master__out_regs + [0x13U]; + this->__PVT__clone_regsiters[0x12U] = this->__Vcellout__vx_register_file_master__out_regs + [0x12U]; + this->__PVT__clone_regsiters[0x11U] = this->__Vcellout__vx_register_file_master__out_regs + [0x11U]; + this->__PVT__clone_regsiters[0x10U] = this->__Vcellout__vx_register_file_master__out_regs + [0x10U]; + this->__PVT__clone_regsiters[0xfU] = this->__Vcellout__vx_register_file_master__out_regs + [0xfU]; + this->__PVT__clone_regsiters[0xeU] = this->__Vcellout__vx_register_file_master__out_regs + [0xeU]; + this->__PVT__clone_regsiters[0xdU] = this->__Vcellout__vx_register_file_master__out_regs + [0xdU]; + this->__PVT__clone_regsiters[0xcU] = this->__Vcellout__vx_register_file_master__out_regs + [0xcU]; + this->__PVT__clone_regsiters[0xbU] = this->__Vcellout__vx_register_file_master__out_regs + [0xbU]; + this->__PVT__clone_regsiters[0xaU] = this->__Vcellout__vx_register_file_master__out_regs + [0xaU]; + this->__PVT__clone_regsiters[9U] = this->__Vcellout__vx_register_file_master__out_regs + [9U]; + this->__PVT__clone_regsiters[8U] = this->__Vcellout__vx_register_file_master__out_regs + [8U]; + this->__PVT__clone_regsiters[7U] = this->__Vcellout__vx_register_file_master__out_regs + [7U]; + this->__PVT__clone_regsiters[6U] = this->__Vcellout__vx_register_file_master__out_regs + [6U]; + this->__PVT__clone_regsiters[5U] = this->__Vcellout__vx_register_file_master__out_regs + [5U]; + this->__PVT__clone_regsiters[4U] = this->__Vcellout__vx_register_file_master__out_regs + [4U]; + this->__PVT__clone_regsiters[3U] = this->__Vcellout__vx_register_file_master__out_regs + [3U]; + this->__PVT__clone_regsiters[2U] = this->__Vcellout__vx_register_file_master__out_regs + [2U]; + this->__PVT__clone_regsiters[1U] = this->__Vcellout__vx_register_file_master__out_regs + [1U]; + this->__PVT__clone_regsiters[0U] = this->__Vcellout__vx_register_file_master__out_regs + [0U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; +} + +VL_INLINE_OPT void VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__22(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__22\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // ALWAYS at VX_register_file_slave.v:68 + this->__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data + = this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; + // ALWAYS at VX_register_file_slave.v:68 + this->__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data + = this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; + // ALWAYS at VX_register_file_slave.v:68 + this->__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data + = this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; + // ALWAYS at VX_register_file_master_slave.v:66 + this->__Vcellout__vx_register_file_master__out_src1_data + = this->__PVT__vx_register_file_master__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; + // ALWAYS at VX_register_file_slave.v:68 + this->__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data + = this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + // ALWAYS at VX_register_file_slave.v:68 + this->__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data + = this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + // ALWAYS at VX_register_file_slave.v:68 + this->__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data + = this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + // ALWAYS at VX_register_file_master_slave.v:66 + this->__Vcellout__vx_register_file_master__out_src2_data + = this->__PVT__vx_register_file_master__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + this->__PVT__rd1_register[3U] = this->__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data; + this->__PVT__rd1_register[2U] = this->__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data; + this->__PVT__rd1_register[1U] = this->__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data; + this->__PVT__rd1_register[0U] = this->__Vcellout__vx_register_file_master__out_src1_data; + this->__PVT__rd2_register[3U] = this->__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data; + this->__PVT__rd2_register[2U] = this->__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data; + this->__PVT__rd2_register[1U] = this->__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data; + this->__PVT__rd2_register[0U] = this->__Vcellout__vx_register_file_master__out_src2_data; +} + +VL_INLINE_OPT void VVortex_VX_context_slave::_combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__29(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_context_slave::_combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__29\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x1fU] + = this->in_wspawn_regs[0x1fU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x1eU] + = this->in_wspawn_regs[0x1eU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x1dU] + = this->in_wspawn_regs[0x1dU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x1cU] + = this->in_wspawn_regs[0x1cU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x1bU] + = this->in_wspawn_regs[0x1bU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x1aU] + = this->in_wspawn_regs[0x1aU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x19U] + = this->in_wspawn_regs[0x19U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x18U] + = this->in_wspawn_regs[0x18U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x17U] + = this->in_wspawn_regs[0x17U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x16U] + = this->in_wspawn_regs[0x16U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x15U] + = this->in_wspawn_regs[0x15U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x14U] + = this->in_wspawn_regs[0x14U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x13U] + = this->in_wspawn_regs[0x13U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x12U] + = this->in_wspawn_regs[0x12U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x11U] + = this->in_wspawn_regs[0x11U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0x10U] + = this->in_wspawn_regs[0x10U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0xfU] + = this->in_wspawn_regs[0xfU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0xeU] + = this->in_wspawn_regs[0xeU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0xdU] + = this->in_wspawn_regs[0xdU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0xcU] + = this->in_wspawn_regs[0xcU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0xbU] + = this->in_wspawn_regs[0xbU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0xaU] + = this->in_wspawn_regs[0xaU]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[9U] + = this->in_wspawn_regs[9U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[8U] + = this->in_wspawn_regs[8U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[7U] + = this->in_wspawn_regs[7U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[6U] + = this->in_wspawn_regs[6U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[5U] + = this->in_wspawn_regs[5U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[4U] + = this->in_wspawn_regs[4U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[3U] + = this->in_wspawn_regs[3U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[2U] + = this->in_wspawn_regs[2U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[1U] + = this->in_wspawn_regs[1U]; + this->__Vcellinp__vx_register_file_master__in_wspawn_regs[0U] + = this->in_wspawn_regs[0U]; +} + +VL_INLINE_OPT void VVortex_VX_context_slave::_combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__36(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_context_slave::_combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__36\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->out_a_reg_data[0U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? this->in_src1_fwd_data + [0U] : this->__PVT__rd1_register + [0U])); + this->out_a_reg_data[1U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? this->in_src1_fwd_data + [1U] : this->__PVT__rd1_register + [1U])); + this->out_a_reg_data[2U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? this->in_src1_fwd_data + [2U] : this->__PVT__rd1_register + [2U])); + this->out_a_reg_data[3U] = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) + ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd) + ? this->in_src1_fwd_data + [3U] : this->__PVT__rd1_register + [3U])); + this->out_b_reg_data[0U] = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? this->in_src2_fwd_data + [0U] : this->__PVT__rd2_register + [0U]); + this->out_b_reg_data[1U] = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? this->in_src2_fwd_data + [1U] : this->__PVT__rd2_register + [1U]); + this->out_b_reg_data[2U] = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? this->in_src2_fwd_data + [2U] : this->__PVT__rd2_register + [2U]); + this->out_b_reg_data[3U] = ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd) + ? this->in_src2_fwd_data + [3U] : this->__PVT__rd2_register + [3U]); +} + +VL_INLINE_OPT void VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one__16(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one__16\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__Vdly__wspawn_state_stall = this->__PVT__wspawn_state_stall; + this->__Vdly__clone_state_stall = this->__PVT__clone_state_stall; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 0U; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + // ALWAYS at VX_context_slave.v:119 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_wspawn) + & (0U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdly__wspawn_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = + (0x3fU & ((IData)(this->__PVT__wspawn_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_context_slave.v:104 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone) + & (0U == (IData)(this->__PVT__clone_state_stall)))) { + this->__Vdly__clone_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = (0x3fU + & ((IData)(this->__PVT__clone_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_register_file_master_slave.v:50 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[0U]) & (2U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_wspawn)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v0 + = this->in_write_data[0U]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_wspawn) + & (2U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v1 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1fU]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 1U; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v2 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1eU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v3 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1dU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v4 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1cU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v5 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1bU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v6 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1aU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v7 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x19U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v8 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x18U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v9 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x17U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v10 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x16U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v11 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x15U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v12 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x14U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v13 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x13U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v14 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x12U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v15 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x11U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v16 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x10U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v17 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xfU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v18 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xeU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v19 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xdU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v20 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xcU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v21 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xbU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v22 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xaU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v23 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [9U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v24 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [8U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v25 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [7U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v26 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [6U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v27 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [5U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v28 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [4U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v29 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [3U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v30 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [2U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v31 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [1U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v32 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[3U]) & (2U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[3U]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone) + & ((3U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (2U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[2U]) & (2U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[2U]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone) + & ((2U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (2U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[1U]) & (2U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[1U]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone) + & ((1U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (2U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYSPOST at VX_register_file_master_slave.v:53 + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v0) { + this->__PVT__vx_register_file_master__DOT__registers[this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v0; + } + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v1) { + this->__PVT__vx_register_file_master__DOT__registers[0x1fU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v1; + this->__PVT__vx_register_file_master__DOT__registers[0x1eU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v2; + this->__PVT__vx_register_file_master__DOT__registers[0x1dU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v3; + this->__PVT__vx_register_file_master__DOT__registers[0x1cU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v4; + this->__PVT__vx_register_file_master__DOT__registers[0x1bU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v5; + this->__PVT__vx_register_file_master__DOT__registers[0x1aU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v6; + this->__PVT__vx_register_file_master__DOT__registers[0x19U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v7; + this->__PVT__vx_register_file_master__DOT__registers[0x18U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v8; + this->__PVT__vx_register_file_master__DOT__registers[0x17U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v9; + this->__PVT__vx_register_file_master__DOT__registers[0x16U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v10; + this->__PVT__vx_register_file_master__DOT__registers[0x15U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v11; + this->__PVT__vx_register_file_master__DOT__registers[0x14U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v12; + this->__PVT__vx_register_file_master__DOT__registers[0x13U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v13; + this->__PVT__vx_register_file_master__DOT__registers[0x12U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v14; + this->__PVT__vx_register_file_master__DOT__registers[0x11U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v15; + this->__PVT__vx_register_file_master__DOT__registers[0x10U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v16; + this->__PVT__vx_register_file_master__DOT__registers[0xfU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v17; + this->__PVT__vx_register_file_master__DOT__registers[0xeU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v18; + this->__PVT__vx_register_file_master__DOT__registers[0xdU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v19; + this->__PVT__vx_register_file_master__DOT__registers[0xcU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v20; + this->__PVT__vx_register_file_master__DOT__registers[0xbU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v21; + this->__PVT__vx_register_file_master__DOT__registers[0xaU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v22; + this->__PVT__vx_register_file_master__DOT__registers[9U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v23; + this->__PVT__vx_register_file_master__DOT__registers[8U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v24; + this->__PVT__vx_register_file_master__DOT__registers[7U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v25; + this->__PVT__vx_register_file_master__DOT__registers[6U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v26; + this->__PVT__vx_register_file_master__DOT__registers[5U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v27; + this->__PVT__vx_register_file_master__DOT__registers[4U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v28; + this->__PVT__vx_register_file_master__DOT__registers[3U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v29; + this->__PVT__vx_register_file_master__DOT__registers[2U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v30; + this->__PVT__vx_register_file_master__DOT__registers[1U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v31; + this->__PVT__vx_register_file_master__DOT__registers[0U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v32; + } + this->__PVT__wspawn_state_stall = this->__Vdly__wspawn_state_stall; + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + this->__PVT__clone_state_stall = this->__Vdly__clone_state_stall; + this->__Vcellout__vx_register_file_master__out_regs[0x1fU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1fU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1eU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1eU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1dU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1dU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1cU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1cU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1bU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1bU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1aU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1aU]; + this->__Vcellout__vx_register_file_master__out_regs[0x19U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x19U]; + this->__Vcellout__vx_register_file_master__out_regs[0x18U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x18U]; + this->__Vcellout__vx_register_file_master__out_regs[0x17U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x17U]; + this->__Vcellout__vx_register_file_master__out_regs[0x16U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x16U]; + this->__Vcellout__vx_register_file_master__out_regs[0x15U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x15U]; + this->__Vcellout__vx_register_file_master__out_regs[0x14U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x14U]; + this->__Vcellout__vx_register_file_master__out_regs[0x13U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x13U]; + this->__Vcellout__vx_register_file_master__out_regs[0x12U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x12U]; + this->__Vcellout__vx_register_file_master__out_regs[0x11U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x11U]; + this->__Vcellout__vx_register_file_master__out_regs[0x10U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x10U]; + this->__Vcellout__vx_register_file_master__out_regs[0xfU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xfU]; + this->__Vcellout__vx_register_file_master__out_regs[0xeU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xeU]; + this->__Vcellout__vx_register_file_master__out_regs[0xdU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xdU]; + this->__Vcellout__vx_register_file_master__out_regs[0xcU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xcU]; + this->__Vcellout__vx_register_file_master__out_regs[0xbU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xbU]; + this->__Vcellout__vx_register_file_master__out_regs[0xaU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xaU]; + this->__Vcellout__vx_register_file_master__out_regs[9U] + = this->__PVT__vx_register_file_master__DOT__registers + [9U]; + this->__Vcellout__vx_register_file_master__out_regs[8U] + = this->__PVT__vx_register_file_master__DOT__registers + [8U]; + this->__Vcellout__vx_register_file_master__out_regs[7U] + = this->__PVT__vx_register_file_master__DOT__registers + [7U]; + this->__Vcellout__vx_register_file_master__out_regs[6U] + = this->__PVT__vx_register_file_master__DOT__registers + [6U]; + this->__Vcellout__vx_register_file_master__out_regs[5U] + = this->__PVT__vx_register_file_master__DOT__registers + [5U]; + this->__Vcellout__vx_register_file_master__out_regs[4U] + = this->__PVT__vx_register_file_master__DOT__registers + [4U]; + this->__Vcellout__vx_register_file_master__out_regs[3U] + = this->__PVT__vx_register_file_master__DOT__registers + [3U]; + this->__Vcellout__vx_register_file_master__out_regs[2U] + = this->__PVT__vx_register_file_master__DOT__registers + [2U]; + this->__Vcellout__vx_register_file_master__out_regs[1U] + = this->__PVT__vx_register_file_master__DOT__registers + [1U]; + this->__Vcellout__vx_register_file_master__out_regs[0U] + = this->__PVT__vx_register_file_master__DOT__registers + [0U]; + this->__PVT__clone_regsiters[0x1fU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1fU]; + this->__PVT__clone_regsiters[0x1eU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1eU]; + this->__PVT__clone_regsiters[0x1dU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1dU]; + this->__PVT__clone_regsiters[0x1cU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1cU]; + this->__PVT__clone_regsiters[0x1bU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1bU]; + this->__PVT__clone_regsiters[0x1aU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1aU]; + this->__PVT__clone_regsiters[0x19U] = this->__Vcellout__vx_register_file_master__out_regs + [0x19U]; + this->__PVT__clone_regsiters[0x18U] = this->__Vcellout__vx_register_file_master__out_regs + [0x18U]; + this->__PVT__clone_regsiters[0x17U] = this->__Vcellout__vx_register_file_master__out_regs + [0x17U]; + this->__PVT__clone_regsiters[0x16U] = this->__Vcellout__vx_register_file_master__out_regs + [0x16U]; + this->__PVT__clone_regsiters[0x15U] = this->__Vcellout__vx_register_file_master__out_regs + [0x15U]; + this->__PVT__clone_regsiters[0x14U] = this->__Vcellout__vx_register_file_master__out_regs + [0x14U]; + this->__PVT__clone_regsiters[0x13U] = this->__Vcellout__vx_register_file_master__out_regs + [0x13U]; + this->__PVT__clone_regsiters[0x12U] = this->__Vcellout__vx_register_file_master__out_regs + [0x12U]; + this->__PVT__clone_regsiters[0x11U] = this->__Vcellout__vx_register_file_master__out_regs + [0x11U]; + this->__PVT__clone_regsiters[0x10U] = this->__Vcellout__vx_register_file_master__out_regs + [0x10U]; + this->__PVT__clone_regsiters[0xfU] = this->__Vcellout__vx_register_file_master__out_regs + [0xfU]; + this->__PVT__clone_regsiters[0xeU] = this->__Vcellout__vx_register_file_master__out_regs + [0xeU]; + this->__PVT__clone_regsiters[0xdU] = this->__Vcellout__vx_register_file_master__out_regs + [0xdU]; + this->__PVT__clone_regsiters[0xcU] = this->__Vcellout__vx_register_file_master__out_regs + [0xcU]; + this->__PVT__clone_regsiters[0xbU] = this->__Vcellout__vx_register_file_master__out_regs + [0xbU]; + this->__PVT__clone_regsiters[0xaU] = this->__Vcellout__vx_register_file_master__out_regs + [0xaU]; + this->__PVT__clone_regsiters[9U] = this->__Vcellout__vx_register_file_master__out_regs + [9U]; + this->__PVT__clone_regsiters[8U] = this->__Vcellout__vx_register_file_master__out_regs + [8U]; + this->__PVT__clone_regsiters[7U] = this->__Vcellout__vx_register_file_master__out_regs + [7U]; + this->__PVT__clone_regsiters[6U] = this->__Vcellout__vx_register_file_master__out_regs + [6U]; + this->__PVT__clone_regsiters[5U] = this->__Vcellout__vx_register_file_master__out_regs + [5U]; + this->__PVT__clone_regsiters[4U] = this->__Vcellout__vx_register_file_master__out_regs + [4U]; + this->__PVT__clone_regsiters[3U] = this->__Vcellout__vx_register_file_master__out_regs + [3U]; + this->__PVT__clone_regsiters[2U] = this->__Vcellout__vx_register_file_master__out_regs + [2U]; + this->__PVT__clone_regsiters[1U] = this->__Vcellout__vx_register_file_master__out_regs + [1U]; + this->__PVT__clone_regsiters[0U] = this->__Vcellout__vx_register_file_master__out_regs + [0U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; +} + +VL_INLINE_OPT void VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one__17(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one__17\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__Vdly__wspawn_state_stall = this->__PVT__wspawn_state_stall; + this->__Vdly__clone_state_stall = this->__PVT__clone_state_stall; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 0U; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + // ALWAYS at VX_context_slave.v:119 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_wspawn) + & (0U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdly__wspawn_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = + (0x3fU & ((IData)(this->__PVT__wspawn_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_context_slave.v:104 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone) + & (0U == (IData)(this->__PVT__clone_state_stall)))) { + this->__Vdly__clone_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = (0x3fU + & ((IData)(this->__PVT__clone_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_register_file_master_slave.v:50 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[0U]) & (3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_wspawn)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v0 + = this->in_write_data[0U]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_wspawn) + & (2U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v1 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1fU]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 1U; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v2 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1eU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v3 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1dU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v4 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1cU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v5 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1bU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v6 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1aU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v7 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x19U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v8 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x18U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v9 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x17U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v10 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x16U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v11 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x15U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v12 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x14U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v13 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x13U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v14 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x12U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v15 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x11U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v16 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x10U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v17 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xfU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v18 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xeU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v19 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xdU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v20 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xcU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v21 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xbU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v22 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xaU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v23 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [9U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v24 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [8U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v25 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [7U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v26 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [6U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v27 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [5U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v28 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [4U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v29 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [3U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v30 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [2U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v31 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [1U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v32 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[3U]) & (3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[3U]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone) + & ((3U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (3U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[2U]) & (3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[2U]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone) + & ((2U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (3U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[1U]) & (3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[1U]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone) + & ((1U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (3U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYSPOST at VX_register_file_master_slave.v:53 + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v0) { + this->__PVT__vx_register_file_master__DOT__registers[this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v0; + } + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v1) { + this->__PVT__vx_register_file_master__DOT__registers[0x1fU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v1; + this->__PVT__vx_register_file_master__DOT__registers[0x1eU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v2; + this->__PVT__vx_register_file_master__DOT__registers[0x1dU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v3; + this->__PVT__vx_register_file_master__DOT__registers[0x1cU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v4; + this->__PVT__vx_register_file_master__DOT__registers[0x1bU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v5; + this->__PVT__vx_register_file_master__DOT__registers[0x1aU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v6; + this->__PVT__vx_register_file_master__DOT__registers[0x19U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v7; + this->__PVT__vx_register_file_master__DOT__registers[0x18U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v8; + this->__PVT__vx_register_file_master__DOT__registers[0x17U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v9; + this->__PVT__vx_register_file_master__DOT__registers[0x16U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v10; + this->__PVT__vx_register_file_master__DOT__registers[0x15U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v11; + this->__PVT__vx_register_file_master__DOT__registers[0x14U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v12; + this->__PVT__vx_register_file_master__DOT__registers[0x13U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v13; + this->__PVT__vx_register_file_master__DOT__registers[0x12U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v14; + this->__PVT__vx_register_file_master__DOT__registers[0x11U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v15; + this->__PVT__vx_register_file_master__DOT__registers[0x10U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v16; + this->__PVT__vx_register_file_master__DOT__registers[0xfU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v17; + this->__PVT__vx_register_file_master__DOT__registers[0xeU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v18; + this->__PVT__vx_register_file_master__DOT__registers[0xdU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v19; + this->__PVT__vx_register_file_master__DOT__registers[0xcU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v20; + this->__PVT__vx_register_file_master__DOT__registers[0xbU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v21; + this->__PVT__vx_register_file_master__DOT__registers[0xaU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v22; + this->__PVT__vx_register_file_master__DOT__registers[9U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v23; + this->__PVT__vx_register_file_master__DOT__registers[8U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v24; + this->__PVT__vx_register_file_master__DOT__registers[7U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v25; + this->__PVT__vx_register_file_master__DOT__registers[6U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v26; + this->__PVT__vx_register_file_master__DOT__registers[5U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v27; + this->__PVT__vx_register_file_master__DOT__registers[4U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v28; + this->__PVT__vx_register_file_master__DOT__registers[3U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v29; + this->__PVT__vx_register_file_master__DOT__registers[2U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v30; + this->__PVT__vx_register_file_master__DOT__registers[1U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v31; + this->__PVT__vx_register_file_master__DOT__registers[0U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v32; + } + this->__PVT__wspawn_state_stall = this->__Vdly__wspawn_state_stall; + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + this->__PVT__clone_state_stall = this->__Vdly__clone_state_stall; + this->__Vcellout__vx_register_file_master__out_regs[0x1fU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1fU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1eU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1eU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1dU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1dU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1cU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1cU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1bU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1bU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1aU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1aU]; + this->__Vcellout__vx_register_file_master__out_regs[0x19U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x19U]; + this->__Vcellout__vx_register_file_master__out_regs[0x18U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x18U]; + this->__Vcellout__vx_register_file_master__out_regs[0x17U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x17U]; + this->__Vcellout__vx_register_file_master__out_regs[0x16U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x16U]; + this->__Vcellout__vx_register_file_master__out_regs[0x15U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x15U]; + this->__Vcellout__vx_register_file_master__out_regs[0x14U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x14U]; + this->__Vcellout__vx_register_file_master__out_regs[0x13U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x13U]; + this->__Vcellout__vx_register_file_master__out_regs[0x12U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x12U]; + this->__Vcellout__vx_register_file_master__out_regs[0x11U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x11U]; + this->__Vcellout__vx_register_file_master__out_regs[0x10U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x10U]; + this->__Vcellout__vx_register_file_master__out_regs[0xfU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xfU]; + this->__Vcellout__vx_register_file_master__out_regs[0xeU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xeU]; + this->__Vcellout__vx_register_file_master__out_regs[0xdU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xdU]; + this->__Vcellout__vx_register_file_master__out_regs[0xcU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xcU]; + this->__Vcellout__vx_register_file_master__out_regs[0xbU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xbU]; + this->__Vcellout__vx_register_file_master__out_regs[0xaU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xaU]; + this->__Vcellout__vx_register_file_master__out_regs[9U] + = this->__PVT__vx_register_file_master__DOT__registers + [9U]; + this->__Vcellout__vx_register_file_master__out_regs[8U] + = this->__PVT__vx_register_file_master__DOT__registers + [8U]; + this->__Vcellout__vx_register_file_master__out_regs[7U] + = this->__PVT__vx_register_file_master__DOT__registers + [7U]; + this->__Vcellout__vx_register_file_master__out_regs[6U] + = this->__PVT__vx_register_file_master__DOT__registers + [6U]; + this->__Vcellout__vx_register_file_master__out_regs[5U] + = this->__PVT__vx_register_file_master__DOT__registers + [5U]; + this->__Vcellout__vx_register_file_master__out_regs[4U] + = this->__PVT__vx_register_file_master__DOT__registers + [4U]; + this->__Vcellout__vx_register_file_master__out_regs[3U] + = this->__PVT__vx_register_file_master__DOT__registers + [3U]; + this->__Vcellout__vx_register_file_master__out_regs[2U] + = this->__PVT__vx_register_file_master__DOT__registers + [2U]; + this->__Vcellout__vx_register_file_master__out_regs[1U] + = this->__PVT__vx_register_file_master__DOT__registers + [1U]; + this->__Vcellout__vx_register_file_master__out_regs[0U] + = this->__PVT__vx_register_file_master__DOT__registers + [0U]; + this->__PVT__clone_regsiters[0x1fU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1fU]; + this->__PVT__clone_regsiters[0x1eU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1eU]; + this->__PVT__clone_regsiters[0x1dU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1dU]; + this->__PVT__clone_regsiters[0x1cU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1cU]; + this->__PVT__clone_regsiters[0x1bU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1bU]; + this->__PVT__clone_regsiters[0x1aU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1aU]; + this->__PVT__clone_regsiters[0x19U] = this->__Vcellout__vx_register_file_master__out_regs + [0x19U]; + this->__PVT__clone_regsiters[0x18U] = this->__Vcellout__vx_register_file_master__out_regs + [0x18U]; + this->__PVT__clone_regsiters[0x17U] = this->__Vcellout__vx_register_file_master__out_regs + [0x17U]; + this->__PVT__clone_regsiters[0x16U] = this->__Vcellout__vx_register_file_master__out_regs + [0x16U]; + this->__PVT__clone_regsiters[0x15U] = this->__Vcellout__vx_register_file_master__out_regs + [0x15U]; + this->__PVT__clone_regsiters[0x14U] = this->__Vcellout__vx_register_file_master__out_regs + [0x14U]; + this->__PVT__clone_regsiters[0x13U] = this->__Vcellout__vx_register_file_master__out_regs + [0x13U]; + this->__PVT__clone_regsiters[0x12U] = this->__Vcellout__vx_register_file_master__out_regs + [0x12U]; + this->__PVT__clone_regsiters[0x11U] = this->__Vcellout__vx_register_file_master__out_regs + [0x11U]; + this->__PVT__clone_regsiters[0x10U] = this->__Vcellout__vx_register_file_master__out_regs + [0x10U]; + this->__PVT__clone_regsiters[0xfU] = this->__Vcellout__vx_register_file_master__out_regs + [0xfU]; + this->__PVT__clone_regsiters[0xeU] = this->__Vcellout__vx_register_file_master__out_regs + [0xeU]; + this->__PVT__clone_regsiters[0xdU] = this->__Vcellout__vx_register_file_master__out_regs + [0xdU]; + this->__PVT__clone_regsiters[0xcU] = this->__Vcellout__vx_register_file_master__out_regs + [0xcU]; + this->__PVT__clone_regsiters[0xbU] = this->__Vcellout__vx_register_file_master__out_regs + [0xbU]; + this->__PVT__clone_regsiters[0xaU] = this->__Vcellout__vx_register_file_master__out_regs + [0xaU]; + this->__PVT__clone_regsiters[9U] = this->__Vcellout__vx_register_file_master__out_regs + [9U]; + this->__PVT__clone_regsiters[8U] = this->__Vcellout__vx_register_file_master__out_regs + [8U]; + this->__PVT__clone_regsiters[7U] = this->__Vcellout__vx_register_file_master__out_regs + [7U]; + this->__PVT__clone_regsiters[6U] = this->__Vcellout__vx_register_file_master__out_regs + [6U]; + this->__PVT__clone_regsiters[5U] = this->__Vcellout__vx_register_file_master__out_regs + [5U]; + this->__PVT__clone_regsiters[4U] = this->__Vcellout__vx_register_file_master__out_regs + [4U]; + this->__PVT__clone_regsiters[3U] = this->__Vcellout__vx_register_file_master__out_regs + [3U]; + this->__PVT__clone_regsiters[2U] = this->__Vcellout__vx_register_file_master__out_regs + [2U]; + this->__PVT__clone_regsiters[1U] = this->__Vcellout__vx_register_file_master__out_regs + [1U]; + this->__PVT__clone_regsiters[0U] = this->__Vcellout__vx_register_file_master__out_regs + [0U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; +} + +VL_INLINE_OPT void VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one__18(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one__18\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__Vdly__wspawn_state_stall = this->__PVT__wspawn_state_stall; + this->__Vdly__clone_state_stall = this->__PVT__clone_state_stall; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 0U; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + // ALWAYS at VX_context_slave.v:119 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_wspawn) + & (0U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdly__wspawn_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = + (0x3fU & ((IData)(this->__PVT__wspawn_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_context_slave.v:104 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone) + & (0U == (IData)(this->__PVT__clone_state_stall)))) { + this->__Vdly__clone_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = (0x3fU + & ((IData)(this->__PVT__clone_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_register_file_master_slave.v:50 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[0U]) & (4U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_wspawn)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v0 + = this->in_write_data[0U]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_wspawn) + & (2U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v1 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1fU]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 1U; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v2 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1eU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v3 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1dU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v4 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1cU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v5 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1bU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v6 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1aU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v7 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x19U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v8 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x18U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v9 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x17U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v10 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x16U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v11 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x15U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v12 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x14U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v13 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x13U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v14 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x12U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v15 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x11U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v16 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x10U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v17 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xfU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v18 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xeU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v19 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xdU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v20 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xcU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v21 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xbU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v22 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xaU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v23 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [9U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v24 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [8U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v25 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [7U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v26 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [6U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v27 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [5U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v28 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [4U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v29 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [3U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v30 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [2U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v31 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [1U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v32 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[3U]) & (4U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[3U]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone) + & ((3U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (4U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[2U]) & (4U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[2U]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone) + & ((2U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (4U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[1U]) & (4U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[1U]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone) + & ((1U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (4U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYSPOST at VX_register_file_master_slave.v:53 + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v0) { + this->__PVT__vx_register_file_master__DOT__registers[this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v0; + } + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v1) { + this->__PVT__vx_register_file_master__DOT__registers[0x1fU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v1; + this->__PVT__vx_register_file_master__DOT__registers[0x1eU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v2; + this->__PVT__vx_register_file_master__DOT__registers[0x1dU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v3; + this->__PVT__vx_register_file_master__DOT__registers[0x1cU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v4; + this->__PVT__vx_register_file_master__DOT__registers[0x1bU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v5; + this->__PVT__vx_register_file_master__DOT__registers[0x1aU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v6; + this->__PVT__vx_register_file_master__DOT__registers[0x19U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v7; + this->__PVT__vx_register_file_master__DOT__registers[0x18U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v8; + this->__PVT__vx_register_file_master__DOT__registers[0x17U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v9; + this->__PVT__vx_register_file_master__DOT__registers[0x16U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v10; + this->__PVT__vx_register_file_master__DOT__registers[0x15U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v11; + this->__PVT__vx_register_file_master__DOT__registers[0x14U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v12; + this->__PVT__vx_register_file_master__DOT__registers[0x13U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v13; + this->__PVT__vx_register_file_master__DOT__registers[0x12U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v14; + this->__PVT__vx_register_file_master__DOT__registers[0x11U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v15; + this->__PVT__vx_register_file_master__DOT__registers[0x10U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v16; + this->__PVT__vx_register_file_master__DOT__registers[0xfU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v17; + this->__PVT__vx_register_file_master__DOT__registers[0xeU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v18; + this->__PVT__vx_register_file_master__DOT__registers[0xdU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v19; + this->__PVT__vx_register_file_master__DOT__registers[0xcU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v20; + this->__PVT__vx_register_file_master__DOT__registers[0xbU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v21; + this->__PVT__vx_register_file_master__DOT__registers[0xaU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v22; + this->__PVT__vx_register_file_master__DOT__registers[9U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v23; + this->__PVT__vx_register_file_master__DOT__registers[8U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v24; + this->__PVT__vx_register_file_master__DOT__registers[7U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v25; + this->__PVT__vx_register_file_master__DOT__registers[6U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v26; + this->__PVT__vx_register_file_master__DOT__registers[5U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v27; + this->__PVT__vx_register_file_master__DOT__registers[4U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v28; + this->__PVT__vx_register_file_master__DOT__registers[3U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v29; + this->__PVT__vx_register_file_master__DOT__registers[2U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v30; + this->__PVT__vx_register_file_master__DOT__registers[1U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v31; + this->__PVT__vx_register_file_master__DOT__registers[0U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v32; + } + this->__PVT__wspawn_state_stall = this->__Vdly__wspawn_state_stall; + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + this->__PVT__clone_state_stall = this->__Vdly__clone_state_stall; + this->__Vcellout__vx_register_file_master__out_regs[0x1fU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1fU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1eU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1eU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1dU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1dU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1cU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1cU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1bU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1bU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1aU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1aU]; + this->__Vcellout__vx_register_file_master__out_regs[0x19U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x19U]; + this->__Vcellout__vx_register_file_master__out_regs[0x18U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x18U]; + this->__Vcellout__vx_register_file_master__out_regs[0x17U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x17U]; + this->__Vcellout__vx_register_file_master__out_regs[0x16U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x16U]; + this->__Vcellout__vx_register_file_master__out_regs[0x15U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x15U]; + this->__Vcellout__vx_register_file_master__out_regs[0x14U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x14U]; + this->__Vcellout__vx_register_file_master__out_regs[0x13U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x13U]; + this->__Vcellout__vx_register_file_master__out_regs[0x12U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x12U]; + this->__Vcellout__vx_register_file_master__out_regs[0x11U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x11U]; + this->__Vcellout__vx_register_file_master__out_regs[0x10U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x10U]; + this->__Vcellout__vx_register_file_master__out_regs[0xfU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xfU]; + this->__Vcellout__vx_register_file_master__out_regs[0xeU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xeU]; + this->__Vcellout__vx_register_file_master__out_regs[0xdU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xdU]; + this->__Vcellout__vx_register_file_master__out_regs[0xcU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xcU]; + this->__Vcellout__vx_register_file_master__out_regs[0xbU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xbU]; + this->__Vcellout__vx_register_file_master__out_regs[0xaU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xaU]; + this->__Vcellout__vx_register_file_master__out_regs[9U] + = this->__PVT__vx_register_file_master__DOT__registers + [9U]; + this->__Vcellout__vx_register_file_master__out_regs[8U] + = this->__PVT__vx_register_file_master__DOT__registers + [8U]; + this->__Vcellout__vx_register_file_master__out_regs[7U] + = this->__PVT__vx_register_file_master__DOT__registers + [7U]; + this->__Vcellout__vx_register_file_master__out_regs[6U] + = this->__PVT__vx_register_file_master__DOT__registers + [6U]; + this->__Vcellout__vx_register_file_master__out_regs[5U] + = this->__PVT__vx_register_file_master__DOT__registers + [5U]; + this->__Vcellout__vx_register_file_master__out_regs[4U] + = this->__PVT__vx_register_file_master__DOT__registers + [4U]; + this->__Vcellout__vx_register_file_master__out_regs[3U] + = this->__PVT__vx_register_file_master__DOT__registers + [3U]; + this->__Vcellout__vx_register_file_master__out_regs[2U] + = this->__PVT__vx_register_file_master__DOT__registers + [2U]; + this->__Vcellout__vx_register_file_master__out_regs[1U] + = this->__PVT__vx_register_file_master__DOT__registers + [1U]; + this->__Vcellout__vx_register_file_master__out_regs[0U] + = this->__PVT__vx_register_file_master__DOT__registers + [0U]; + this->__PVT__clone_regsiters[0x1fU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1fU]; + this->__PVT__clone_regsiters[0x1eU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1eU]; + this->__PVT__clone_regsiters[0x1dU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1dU]; + this->__PVT__clone_regsiters[0x1cU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1cU]; + this->__PVT__clone_regsiters[0x1bU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1bU]; + this->__PVT__clone_regsiters[0x1aU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1aU]; + this->__PVT__clone_regsiters[0x19U] = this->__Vcellout__vx_register_file_master__out_regs + [0x19U]; + this->__PVT__clone_regsiters[0x18U] = this->__Vcellout__vx_register_file_master__out_regs + [0x18U]; + this->__PVT__clone_regsiters[0x17U] = this->__Vcellout__vx_register_file_master__out_regs + [0x17U]; + this->__PVT__clone_regsiters[0x16U] = this->__Vcellout__vx_register_file_master__out_regs + [0x16U]; + this->__PVT__clone_regsiters[0x15U] = this->__Vcellout__vx_register_file_master__out_regs + [0x15U]; + this->__PVT__clone_regsiters[0x14U] = this->__Vcellout__vx_register_file_master__out_regs + [0x14U]; + this->__PVT__clone_regsiters[0x13U] = this->__Vcellout__vx_register_file_master__out_regs + [0x13U]; + this->__PVT__clone_regsiters[0x12U] = this->__Vcellout__vx_register_file_master__out_regs + [0x12U]; + this->__PVT__clone_regsiters[0x11U] = this->__Vcellout__vx_register_file_master__out_regs + [0x11U]; + this->__PVT__clone_regsiters[0x10U] = this->__Vcellout__vx_register_file_master__out_regs + [0x10U]; + this->__PVT__clone_regsiters[0xfU] = this->__Vcellout__vx_register_file_master__out_regs + [0xfU]; + this->__PVT__clone_regsiters[0xeU] = this->__Vcellout__vx_register_file_master__out_regs + [0xeU]; + this->__PVT__clone_regsiters[0xdU] = this->__Vcellout__vx_register_file_master__out_regs + [0xdU]; + this->__PVT__clone_regsiters[0xcU] = this->__Vcellout__vx_register_file_master__out_regs + [0xcU]; + this->__PVT__clone_regsiters[0xbU] = this->__Vcellout__vx_register_file_master__out_regs + [0xbU]; + this->__PVT__clone_regsiters[0xaU] = this->__Vcellout__vx_register_file_master__out_regs + [0xaU]; + this->__PVT__clone_regsiters[9U] = this->__Vcellout__vx_register_file_master__out_regs + [9U]; + this->__PVT__clone_regsiters[8U] = this->__Vcellout__vx_register_file_master__out_regs + [8U]; + this->__PVT__clone_regsiters[7U] = this->__Vcellout__vx_register_file_master__out_regs + [7U]; + this->__PVT__clone_regsiters[6U] = this->__Vcellout__vx_register_file_master__out_regs + [6U]; + this->__PVT__clone_regsiters[5U] = this->__Vcellout__vx_register_file_master__out_regs + [5U]; + this->__PVT__clone_regsiters[4U] = this->__Vcellout__vx_register_file_master__out_regs + [4U]; + this->__PVT__clone_regsiters[3U] = this->__Vcellout__vx_register_file_master__out_regs + [3U]; + this->__PVT__clone_regsiters[2U] = this->__Vcellout__vx_register_file_master__out_regs + [2U]; + this->__PVT__clone_regsiters[1U] = this->__Vcellout__vx_register_file_master__out_regs + [1U]; + this->__PVT__clone_regsiters[0U] = this->__Vcellout__vx_register_file_master__out_regs + [0U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; +} + +VL_INLINE_OPT void VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one__19(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one__19\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__Vdly__wspawn_state_stall = this->__PVT__wspawn_state_stall; + this->__Vdly__clone_state_stall = this->__PVT__clone_state_stall; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 0U; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + // ALWAYS at VX_context_slave.v:119 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_wspawn) + & (0U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdly__wspawn_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = + (0x3fU & ((IData)(this->__PVT__wspawn_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_context_slave.v:104 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone) + & (0U == (IData)(this->__PVT__clone_state_stall)))) { + this->__Vdly__clone_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = (0x3fU + & ((IData)(this->__PVT__clone_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_register_file_master_slave.v:50 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[0U]) & (5U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_wspawn)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v0 + = this->in_write_data[0U]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_wspawn) + & (2U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v1 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1fU]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 1U; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v2 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1eU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v3 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1dU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v4 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1cU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v5 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1bU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v6 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1aU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v7 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x19U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v8 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x18U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v9 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x17U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v10 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x16U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v11 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x15U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v12 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x14U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v13 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x13U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v14 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x12U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v15 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x11U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v16 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x10U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v17 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xfU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v18 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xeU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v19 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xdU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v20 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xcU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v21 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xbU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v22 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xaU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v23 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [9U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v24 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [8U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v25 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [7U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v26 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [6U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v27 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [5U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v28 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [4U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v29 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [3U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v30 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [2U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v31 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [1U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v32 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[3U]) & (5U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[3U]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone) + & ((3U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (5U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[2U]) & (5U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[2U]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone) + & ((2U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (5U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[1U]) & (5U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[1U]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone) + & ((1U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (5U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYSPOST at VX_register_file_master_slave.v:53 + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v0) { + this->__PVT__vx_register_file_master__DOT__registers[this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v0; + } + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v1) { + this->__PVT__vx_register_file_master__DOT__registers[0x1fU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v1; + this->__PVT__vx_register_file_master__DOT__registers[0x1eU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v2; + this->__PVT__vx_register_file_master__DOT__registers[0x1dU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v3; + this->__PVT__vx_register_file_master__DOT__registers[0x1cU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v4; + this->__PVT__vx_register_file_master__DOT__registers[0x1bU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v5; + this->__PVT__vx_register_file_master__DOT__registers[0x1aU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v6; + this->__PVT__vx_register_file_master__DOT__registers[0x19U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v7; + this->__PVT__vx_register_file_master__DOT__registers[0x18U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v8; + this->__PVT__vx_register_file_master__DOT__registers[0x17U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v9; + this->__PVT__vx_register_file_master__DOT__registers[0x16U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v10; + this->__PVT__vx_register_file_master__DOT__registers[0x15U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v11; + this->__PVT__vx_register_file_master__DOT__registers[0x14U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v12; + this->__PVT__vx_register_file_master__DOT__registers[0x13U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v13; + this->__PVT__vx_register_file_master__DOT__registers[0x12U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v14; + this->__PVT__vx_register_file_master__DOT__registers[0x11U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v15; + this->__PVT__vx_register_file_master__DOT__registers[0x10U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v16; + this->__PVT__vx_register_file_master__DOT__registers[0xfU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v17; + this->__PVT__vx_register_file_master__DOT__registers[0xeU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v18; + this->__PVT__vx_register_file_master__DOT__registers[0xdU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v19; + this->__PVT__vx_register_file_master__DOT__registers[0xcU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v20; + this->__PVT__vx_register_file_master__DOT__registers[0xbU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v21; + this->__PVT__vx_register_file_master__DOT__registers[0xaU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v22; + this->__PVT__vx_register_file_master__DOT__registers[9U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v23; + this->__PVT__vx_register_file_master__DOT__registers[8U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v24; + this->__PVT__vx_register_file_master__DOT__registers[7U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v25; + this->__PVT__vx_register_file_master__DOT__registers[6U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v26; + this->__PVT__vx_register_file_master__DOT__registers[5U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v27; + this->__PVT__vx_register_file_master__DOT__registers[4U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v28; + this->__PVT__vx_register_file_master__DOT__registers[3U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v29; + this->__PVT__vx_register_file_master__DOT__registers[2U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v30; + this->__PVT__vx_register_file_master__DOT__registers[1U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v31; + this->__PVT__vx_register_file_master__DOT__registers[0U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v32; + } + this->__PVT__wspawn_state_stall = this->__Vdly__wspawn_state_stall; + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + this->__PVT__clone_state_stall = this->__Vdly__clone_state_stall; + this->__Vcellout__vx_register_file_master__out_regs[0x1fU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1fU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1eU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1eU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1dU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1dU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1cU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1cU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1bU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1bU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1aU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1aU]; + this->__Vcellout__vx_register_file_master__out_regs[0x19U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x19U]; + this->__Vcellout__vx_register_file_master__out_regs[0x18U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x18U]; + this->__Vcellout__vx_register_file_master__out_regs[0x17U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x17U]; + this->__Vcellout__vx_register_file_master__out_regs[0x16U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x16U]; + this->__Vcellout__vx_register_file_master__out_regs[0x15U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x15U]; + this->__Vcellout__vx_register_file_master__out_regs[0x14U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x14U]; + this->__Vcellout__vx_register_file_master__out_regs[0x13U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x13U]; + this->__Vcellout__vx_register_file_master__out_regs[0x12U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x12U]; + this->__Vcellout__vx_register_file_master__out_regs[0x11U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x11U]; + this->__Vcellout__vx_register_file_master__out_regs[0x10U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x10U]; + this->__Vcellout__vx_register_file_master__out_regs[0xfU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xfU]; + this->__Vcellout__vx_register_file_master__out_regs[0xeU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xeU]; + this->__Vcellout__vx_register_file_master__out_regs[0xdU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xdU]; + this->__Vcellout__vx_register_file_master__out_regs[0xcU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xcU]; + this->__Vcellout__vx_register_file_master__out_regs[0xbU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xbU]; + this->__Vcellout__vx_register_file_master__out_regs[0xaU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xaU]; + this->__Vcellout__vx_register_file_master__out_regs[9U] + = this->__PVT__vx_register_file_master__DOT__registers + [9U]; + this->__Vcellout__vx_register_file_master__out_regs[8U] + = this->__PVT__vx_register_file_master__DOT__registers + [8U]; + this->__Vcellout__vx_register_file_master__out_regs[7U] + = this->__PVT__vx_register_file_master__DOT__registers + [7U]; + this->__Vcellout__vx_register_file_master__out_regs[6U] + = this->__PVT__vx_register_file_master__DOT__registers + [6U]; + this->__Vcellout__vx_register_file_master__out_regs[5U] + = this->__PVT__vx_register_file_master__DOT__registers + [5U]; + this->__Vcellout__vx_register_file_master__out_regs[4U] + = this->__PVT__vx_register_file_master__DOT__registers + [4U]; + this->__Vcellout__vx_register_file_master__out_regs[3U] + = this->__PVT__vx_register_file_master__DOT__registers + [3U]; + this->__Vcellout__vx_register_file_master__out_regs[2U] + = this->__PVT__vx_register_file_master__DOT__registers + [2U]; + this->__Vcellout__vx_register_file_master__out_regs[1U] + = this->__PVT__vx_register_file_master__DOT__registers + [1U]; + this->__Vcellout__vx_register_file_master__out_regs[0U] + = this->__PVT__vx_register_file_master__DOT__registers + [0U]; + this->__PVT__clone_regsiters[0x1fU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1fU]; + this->__PVT__clone_regsiters[0x1eU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1eU]; + this->__PVT__clone_regsiters[0x1dU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1dU]; + this->__PVT__clone_regsiters[0x1cU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1cU]; + this->__PVT__clone_regsiters[0x1bU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1bU]; + this->__PVT__clone_regsiters[0x1aU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1aU]; + this->__PVT__clone_regsiters[0x19U] = this->__Vcellout__vx_register_file_master__out_regs + [0x19U]; + this->__PVT__clone_regsiters[0x18U] = this->__Vcellout__vx_register_file_master__out_regs + [0x18U]; + this->__PVT__clone_regsiters[0x17U] = this->__Vcellout__vx_register_file_master__out_regs + [0x17U]; + this->__PVT__clone_regsiters[0x16U] = this->__Vcellout__vx_register_file_master__out_regs + [0x16U]; + this->__PVT__clone_regsiters[0x15U] = this->__Vcellout__vx_register_file_master__out_regs + [0x15U]; + this->__PVT__clone_regsiters[0x14U] = this->__Vcellout__vx_register_file_master__out_regs + [0x14U]; + this->__PVT__clone_regsiters[0x13U] = this->__Vcellout__vx_register_file_master__out_regs + [0x13U]; + this->__PVT__clone_regsiters[0x12U] = this->__Vcellout__vx_register_file_master__out_regs + [0x12U]; + this->__PVT__clone_regsiters[0x11U] = this->__Vcellout__vx_register_file_master__out_regs + [0x11U]; + this->__PVT__clone_regsiters[0x10U] = this->__Vcellout__vx_register_file_master__out_regs + [0x10U]; + this->__PVT__clone_regsiters[0xfU] = this->__Vcellout__vx_register_file_master__out_regs + [0xfU]; + this->__PVT__clone_regsiters[0xeU] = this->__Vcellout__vx_register_file_master__out_regs + [0xeU]; + this->__PVT__clone_regsiters[0xdU] = this->__Vcellout__vx_register_file_master__out_regs + [0xdU]; + this->__PVT__clone_regsiters[0xcU] = this->__Vcellout__vx_register_file_master__out_regs + [0xcU]; + this->__PVT__clone_regsiters[0xbU] = this->__Vcellout__vx_register_file_master__out_regs + [0xbU]; + this->__PVT__clone_regsiters[0xaU] = this->__Vcellout__vx_register_file_master__out_regs + [0xaU]; + this->__PVT__clone_regsiters[9U] = this->__Vcellout__vx_register_file_master__out_regs + [9U]; + this->__PVT__clone_regsiters[8U] = this->__Vcellout__vx_register_file_master__out_regs + [8U]; + this->__PVT__clone_regsiters[7U] = this->__Vcellout__vx_register_file_master__out_regs + [7U]; + this->__PVT__clone_regsiters[6U] = this->__Vcellout__vx_register_file_master__out_regs + [6U]; + this->__PVT__clone_regsiters[5U] = this->__Vcellout__vx_register_file_master__out_regs + [5U]; + this->__PVT__clone_regsiters[4U] = this->__Vcellout__vx_register_file_master__out_regs + [4U]; + this->__PVT__clone_regsiters[3U] = this->__Vcellout__vx_register_file_master__out_regs + [3U]; + this->__PVT__clone_regsiters[2U] = this->__Vcellout__vx_register_file_master__out_regs + [2U]; + this->__PVT__clone_regsiters[1U] = this->__Vcellout__vx_register_file_master__out_regs + [1U]; + this->__PVT__clone_regsiters[0U] = this->__Vcellout__vx_register_file_master__out_regs + [0U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; +} + +VL_INLINE_OPT void VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one__20(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one__20\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__Vdly__wspawn_state_stall = this->__PVT__wspawn_state_stall; + this->__Vdly__clone_state_stall = this->__PVT__clone_state_stall; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 0U; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + // ALWAYS at VX_context_slave.v:119 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_wspawn) + & (0U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdly__wspawn_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = + (0x3fU & ((IData)(this->__PVT__wspawn_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_context_slave.v:104 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone) + & (0U == (IData)(this->__PVT__clone_state_stall)))) { + this->__Vdly__clone_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = (0x3fU + & ((IData)(this->__PVT__clone_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_register_file_master_slave.v:50 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[0U]) & (6U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_wspawn)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v0 + = this->in_write_data[0U]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_wspawn) + & (2U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v1 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1fU]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 1U; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v2 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1eU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v3 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1dU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v4 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1cU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v5 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1bU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v6 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1aU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v7 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x19U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v8 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x18U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v9 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x17U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v10 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x16U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v11 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x15U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v12 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x14U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v13 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x13U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v14 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x12U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v15 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x11U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v16 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x10U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v17 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xfU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v18 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xeU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v19 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xdU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v20 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xcU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v21 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xbU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v22 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xaU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v23 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [9U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v24 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [8U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v25 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [7U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v26 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [6U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v27 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [5U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v28 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [4U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v29 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [3U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v30 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [2U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v31 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [1U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v32 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[3U]) & (6U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[3U]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone) + & ((3U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (6U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[2U]) & (6U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[2U]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone) + & ((2U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (6U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[1U]) & (6U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[1U]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone) + & ((1U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (6U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYSPOST at VX_register_file_master_slave.v:53 + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v0) { + this->__PVT__vx_register_file_master__DOT__registers[this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v0; + } + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v1) { + this->__PVT__vx_register_file_master__DOT__registers[0x1fU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v1; + this->__PVT__vx_register_file_master__DOT__registers[0x1eU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v2; + this->__PVT__vx_register_file_master__DOT__registers[0x1dU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v3; + this->__PVT__vx_register_file_master__DOT__registers[0x1cU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v4; + this->__PVT__vx_register_file_master__DOT__registers[0x1bU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v5; + this->__PVT__vx_register_file_master__DOT__registers[0x1aU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v6; + this->__PVT__vx_register_file_master__DOT__registers[0x19U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v7; + this->__PVT__vx_register_file_master__DOT__registers[0x18U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v8; + this->__PVT__vx_register_file_master__DOT__registers[0x17U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v9; + this->__PVT__vx_register_file_master__DOT__registers[0x16U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v10; + this->__PVT__vx_register_file_master__DOT__registers[0x15U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v11; + this->__PVT__vx_register_file_master__DOT__registers[0x14U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v12; + this->__PVT__vx_register_file_master__DOT__registers[0x13U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v13; + this->__PVT__vx_register_file_master__DOT__registers[0x12U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v14; + this->__PVT__vx_register_file_master__DOT__registers[0x11U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v15; + this->__PVT__vx_register_file_master__DOT__registers[0x10U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v16; + this->__PVT__vx_register_file_master__DOT__registers[0xfU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v17; + this->__PVT__vx_register_file_master__DOT__registers[0xeU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v18; + this->__PVT__vx_register_file_master__DOT__registers[0xdU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v19; + this->__PVT__vx_register_file_master__DOT__registers[0xcU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v20; + this->__PVT__vx_register_file_master__DOT__registers[0xbU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v21; + this->__PVT__vx_register_file_master__DOT__registers[0xaU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v22; + this->__PVT__vx_register_file_master__DOT__registers[9U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v23; + this->__PVT__vx_register_file_master__DOT__registers[8U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v24; + this->__PVT__vx_register_file_master__DOT__registers[7U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v25; + this->__PVT__vx_register_file_master__DOT__registers[6U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v26; + this->__PVT__vx_register_file_master__DOT__registers[5U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v27; + this->__PVT__vx_register_file_master__DOT__registers[4U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v28; + this->__PVT__vx_register_file_master__DOT__registers[3U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v29; + this->__PVT__vx_register_file_master__DOT__registers[2U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v30; + this->__PVT__vx_register_file_master__DOT__registers[1U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v31; + this->__PVT__vx_register_file_master__DOT__registers[0U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v32; + } + this->__PVT__wspawn_state_stall = this->__Vdly__wspawn_state_stall; + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + this->__PVT__clone_state_stall = this->__Vdly__clone_state_stall; + this->__Vcellout__vx_register_file_master__out_regs[0x1fU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1fU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1eU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1eU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1dU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1dU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1cU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1cU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1bU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1bU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1aU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1aU]; + this->__Vcellout__vx_register_file_master__out_regs[0x19U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x19U]; + this->__Vcellout__vx_register_file_master__out_regs[0x18U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x18U]; + this->__Vcellout__vx_register_file_master__out_regs[0x17U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x17U]; + this->__Vcellout__vx_register_file_master__out_regs[0x16U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x16U]; + this->__Vcellout__vx_register_file_master__out_regs[0x15U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x15U]; + this->__Vcellout__vx_register_file_master__out_regs[0x14U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x14U]; + this->__Vcellout__vx_register_file_master__out_regs[0x13U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x13U]; + this->__Vcellout__vx_register_file_master__out_regs[0x12U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x12U]; + this->__Vcellout__vx_register_file_master__out_regs[0x11U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x11U]; + this->__Vcellout__vx_register_file_master__out_regs[0x10U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x10U]; + this->__Vcellout__vx_register_file_master__out_regs[0xfU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xfU]; + this->__Vcellout__vx_register_file_master__out_regs[0xeU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xeU]; + this->__Vcellout__vx_register_file_master__out_regs[0xdU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xdU]; + this->__Vcellout__vx_register_file_master__out_regs[0xcU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xcU]; + this->__Vcellout__vx_register_file_master__out_regs[0xbU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xbU]; + this->__Vcellout__vx_register_file_master__out_regs[0xaU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xaU]; + this->__Vcellout__vx_register_file_master__out_regs[9U] + = this->__PVT__vx_register_file_master__DOT__registers + [9U]; + this->__Vcellout__vx_register_file_master__out_regs[8U] + = this->__PVT__vx_register_file_master__DOT__registers + [8U]; + this->__Vcellout__vx_register_file_master__out_regs[7U] + = this->__PVT__vx_register_file_master__DOT__registers + [7U]; + this->__Vcellout__vx_register_file_master__out_regs[6U] + = this->__PVT__vx_register_file_master__DOT__registers + [6U]; + this->__Vcellout__vx_register_file_master__out_regs[5U] + = this->__PVT__vx_register_file_master__DOT__registers + [5U]; + this->__Vcellout__vx_register_file_master__out_regs[4U] + = this->__PVT__vx_register_file_master__DOT__registers + [4U]; + this->__Vcellout__vx_register_file_master__out_regs[3U] + = this->__PVT__vx_register_file_master__DOT__registers + [3U]; + this->__Vcellout__vx_register_file_master__out_regs[2U] + = this->__PVT__vx_register_file_master__DOT__registers + [2U]; + this->__Vcellout__vx_register_file_master__out_regs[1U] + = this->__PVT__vx_register_file_master__DOT__registers + [1U]; + this->__Vcellout__vx_register_file_master__out_regs[0U] + = this->__PVT__vx_register_file_master__DOT__registers + [0U]; + this->__PVT__clone_regsiters[0x1fU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1fU]; + this->__PVT__clone_regsiters[0x1eU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1eU]; + this->__PVT__clone_regsiters[0x1dU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1dU]; + this->__PVT__clone_regsiters[0x1cU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1cU]; + this->__PVT__clone_regsiters[0x1bU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1bU]; + this->__PVT__clone_regsiters[0x1aU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1aU]; + this->__PVT__clone_regsiters[0x19U] = this->__Vcellout__vx_register_file_master__out_regs + [0x19U]; + this->__PVT__clone_regsiters[0x18U] = this->__Vcellout__vx_register_file_master__out_regs + [0x18U]; + this->__PVT__clone_regsiters[0x17U] = this->__Vcellout__vx_register_file_master__out_regs + [0x17U]; + this->__PVT__clone_regsiters[0x16U] = this->__Vcellout__vx_register_file_master__out_regs + [0x16U]; + this->__PVT__clone_regsiters[0x15U] = this->__Vcellout__vx_register_file_master__out_regs + [0x15U]; + this->__PVT__clone_regsiters[0x14U] = this->__Vcellout__vx_register_file_master__out_regs + [0x14U]; + this->__PVT__clone_regsiters[0x13U] = this->__Vcellout__vx_register_file_master__out_regs + [0x13U]; + this->__PVT__clone_regsiters[0x12U] = this->__Vcellout__vx_register_file_master__out_regs + [0x12U]; + this->__PVT__clone_regsiters[0x11U] = this->__Vcellout__vx_register_file_master__out_regs + [0x11U]; + this->__PVT__clone_regsiters[0x10U] = this->__Vcellout__vx_register_file_master__out_regs + [0x10U]; + this->__PVT__clone_regsiters[0xfU] = this->__Vcellout__vx_register_file_master__out_regs + [0xfU]; + this->__PVT__clone_regsiters[0xeU] = this->__Vcellout__vx_register_file_master__out_regs + [0xeU]; + this->__PVT__clone_regsiters[0xdU] = this->__Vcellout__vx_register_file_master__out_regs + [0xdU]; + this->__PVT__clone_regsiters[0xcU] = this->__Vcellout__vx_register_file_master__out_regs + [0xcU]; + this->__PVT__clone_regsiters[0xbU] = this->__Vcellout__vx_register_file_master__out_regs + [0xbU]; + this->__PVT__clone_regsiters[0xaU] = this->__Vcellout__vx_register_file_master__out_regs + [0xaU]; + this->__PVT__clone_regsiters[9U] = this->__Vcellout__vx_register_file_master__out_regs + [9U]; + this->__PVT__clone_regsiters[8U] = this->__Vcellout__vx_register_file_master__out_regs + [8U]; + this->__PVT__clone_regsiters[7U] = this->__Vcellout__vx_register_file_master__out_regs + [7U]; + this->__PVT__clone_regsiters[6U] = this->__Vcellout__vx_register_file_master__out_regs + [6U]; + this->__PVT__clone_regsiters[5U] = this->__Vcellout__vx_register_file_master__out_regs + [5U]; + this->__PVT__clone_regsiters[4U] = this->__Vcellout__vx_register_file_master__out_regs + [4U]; + this->__PVT__clone_regsiters[3U] = this->__Vcellout__vx_register_file_master__out_regs + [3U]; + this->__PVT__clone_regsiters[2U] = this->__Vcellout__vx_register_file_master__out_regs + [2U]; + this->__PVT__clone_regsiters[1U] = this->__Vcellout__vx_register_file_master__out_regs + [1U]; + this->__PVT__clone_regsiters[0U] = this->__Vcellout__vx_register_file_master__out_regs + [0U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; +} + +VL_INLINE_OPT void VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one__21(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_context_slave::_sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one__21\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + this->__Vdly__wspawn_state_stall = this->__PVT__wspawn_state_stall; + this->__Vdly__clone_state_stall = this->__PVT__clone_state_stall; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 0U; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U; + // ALWAYS at VX_context_slave.v:119 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_wspawn) + & (0U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdly__wspawn_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__wspawn_state_stall))) { + this->__Vdly__wspawn_state_stall = + (0x3fU & ((IData)(this->__PVT__wspawn_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_context_slave.v:104 + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone) + & (0U == (IData)(this->__PVT__clone_state_stall)))) { + this->__Vdly__clone_state_stall = 0xaU; + } else { + if ((1U == (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = 0U; + } else { + if ((0U < (IData)(this->__PVT__clone_state_stall))) { + this->__Vdly__clone_state_stall = (0x3fU + & ((IData)(this->__PVT__clone_state_stall) + - (IData)(1U))); + } + } + } + // ALWAYS at VX_register_file_master_slave.v:50 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[0U]) & (7U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_wspawn)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v0 + = this->in_write_data[0U]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_wspawn) + & (2U == (IData)(this->__PVT__wspawn_state_stall)))) { + this->__Vdlyvval__vx_register_file_master__DOT__registers__v1 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1fU]; + this->__Vdlyvset__vx_register_file_master__DOT__registers__v1 = 1U; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v2 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1eU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v3 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1dU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v4 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1cU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v5 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1bU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v6 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x1aU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v7 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x19U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v8 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x18U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v9 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x17U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v10 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x16U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v11 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x15U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v12 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x14U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v13 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x13U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v14 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x12U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v15 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x11U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v16 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0x10U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v17 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xfU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v18 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xeU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v19 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xdU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v20 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xcU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v21 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xbU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v22 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0xaU]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v23 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [9U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v24 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [8U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v25 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [7U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v26 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [6U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v27 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [5U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v28 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [4U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v29 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [3U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v30 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [2U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v31 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [1U]; + this->__Vdlyvval__vx_register_file_master__DOT__registers__v32 + = this->__Vcellinp__vx_register_file_master__in_wspawn_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[3U]) & (7U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[3U]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone) + & ((3U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (7U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[2U]) & (7U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[2U]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone) + & ((2U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (7U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYS at VX_register_file_slave.v:53 + if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) + & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) + & this->in_valid[1U]) & (7U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = this->in_write_data[1U]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U; + this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 + = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd; + } else { + if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone) + & ((1U == this->__PVT__rd1_register[0U]) + & (1U == (IData)(this->__PVT__clone_state_stall)))) + & (7U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) { + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1fU]; + this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1eU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1dU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1cU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1bU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x1aU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x19U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x18U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x17U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x16U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x15U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x14U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x13U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x12U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x11U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0x10U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xfU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xeU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xdU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xcU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xbU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0xaU]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [9U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [8U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [7U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [6U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [5U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [4U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [3U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [2U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [1U]; + this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32 + = this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs + [0U]; + } + } + // ALWAYSPOST at VX_register_file_master_slave.v:53 + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v0) { + this->__PVT__vx_register_file_master__DOT__registers[this->__Vdlyvdim0__vx_register_file_master__DOT__registers__v0] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v0; + } + if (this->__Vdlyvset__vx_register_file_master__DOT__registers__v1) { + this->__PVT__vx_register_file_master__DOT__registers[0x1fU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v1; + this->__PVT__vx_register_file_master__DOT__registers[0x1eU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v2; + this->__PVT__vx_register_file_master__DOT__registers[0x1dU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v3; + this->__PVT__vx_register_file_master__DOT__registers[0x1cU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v4; + this->__PVT__vx_register_file_master__DOT__registers[0x1bU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v5; + this->__PVT__vx_register_file_master__DOT__registers[0x1aU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v6; + this->__PVT__vx_register_file_master__DOT__registers[0x19U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v7; + this->__PVT__vx_register_file_master__DOT__registers[0x18U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v8; + this->__PVT__vx_register_file_master__DOT__registers[0x17U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v9; + this->__PVT__vx_register_file_master__DOT__registers[0x16U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v10; + this->__PVT__vx_register_file_master__DOT__registers[0x15U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v11; + this->__PVT__vx_register_file_master__DOT__registers[0x14U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v12; + this->__PVT__vx_register_file_master__DOT__registers[0x13U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v13; + this->__PVT__vx_register_file_master__DOT__registers[0x12U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v14; + this->__PVT__vx_register_file_master__DOT__registers[0x11U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v15; + this->__PVT__vx_register_file_master__DOT__registers[0x10U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v16; + this->__PVT__vx_register_file_master__DOT__registers[0xfU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v17; + this->__PVT__vx_register_file_master__DOT__registers[0xeU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v18; + this->__PVT__vx_register_file_master__DOT__registers[0xdU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v19; + this->__PVT__vx_register_file_master__DOT__registers[0xcU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v20; + this->__PVT__vx_register_file_master__DOT__registers[0xbU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v21; + this->__PVT__vx_register_file_master__DOT__registers[0xaU] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v22; + this->__PVT__vx_register_file_master__DOT__registers[9U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v23; + this->__PVT__vx_register_file_master__DOT__registers[8U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v24; + this->__PVT__vx_register_file_master__DOT__registers[7U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v25; + this->__PVT__vx_register_file_master__DOT__registers[6U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v26; + this->__PVT__vx_register_file_master__DOT__registers[5U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v27; + this->__PVT__vx_register_file_master__DOT__registers[4U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v28; + this->__PVT__vx_register_file_master__DOT__registers[3U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v29; + this->__PVT__vx_register_file_master__DOT__registers[2U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v30; + this->__PVT__vx_register_file_master__DOT__registers[1U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v31; + this->__PVT__vx_register_file_master__DOT__registers[0U] + = this->__Vdlyvval__vx_register_file_master__DOT__registers__v32; + } + this->__PVT__wspawn_state_stall = this->__Vdly__wspawn_state_stall; + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + // ALWAYSPOST at VX_register_file_slave.v:56 + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[this->__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0; + } + if (this->__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1) { + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[9U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[8U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[7U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[6U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[5U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[4U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[3U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[2U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[1U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31; + this->__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0U] + = this->__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32; + } + this->__PVT__clone_state_stall = this->__Vdly__clone_state_stall; + this->__Vcellout__vx_register_file_master__out_regs[0x1fU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1fU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1eU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1eU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1dU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1dU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1cU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1cU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1bU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1bU]; + this->__Vcellout__vx_register_file_master__out_regs[0x1aU] + = this->__PVT__vx_register_file_master__DOT__registers + [0x1aU]; + this->__Vcellout__vx_register_file_master__out_regs[0x19U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x19U]; + this->__Vcellout__vx_register_file_master__out_regs[0x18U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x18U]; + this->__Vcellout__vx_register_file_master__out_regs[0x17U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x17U]; + this->__Vcellout__vx_register_file_master__out_regs[0x16U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x16U]; + this->__Vcellout__vx_register_file_master__out_regs[0x15U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x15U]; + this->__Vcellout__vx_register_file_master__out_regs[0x14U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x14U]; + this->__Vcellout__vx_register_file_master__out_regs[0x13U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x13U]; + this->__Vcellout__vx_register_file_master__out_regs[0x12U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x12U]; + this->__Vcellout__vx_register_file_master__out_regs[0x11U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x11U]; + this->__Vcellout__vx_register_file_master__out_regs[0x10U] + = this->__PVT__vx_register_file_master__DOT__registers + [0x10U]; + this->__Vcellout__vx_register_file_master__out_regs[0xfU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xfU]; + this->__Vcellout__vx_register_file_master__out_regs[0xeU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xeU]; + this->__Vcellout__vx_register_file_master__out_regs[0xdU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xdU]; + this->__Vcellout__vx_register_file_master__out_regs[0xcU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xcU]; + this->__Vcellout__vx_register_file_master__out_regs[0xbU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xbU]; + this->__Vcellout__vx_register_file_master__out_regs[0xaU] + = this->__PVT__vx_register_file_master__DOT__registers + [0xaU]; + this->__Vcellout__vx_register_file_master__out_regs[9U] + = this->__PVT__vx_register_file_master__DOT__registers + [9U]; + this->__Vcellout__vx_register_file_master__out_regs[8U] + = this->__PVT__vx_register_file_master__DOT__registers + [8U]; + this->__Vcellout__vx_register_file_master__out_regs[7U] + = this->__PVT__vx_register_file_master__DOT__registers + [7U]; + this->__Vcellout__vx_register_file_master__out_regs[6U] + = this->__PVT__vx_register_file_master__DOT__registers + [6U]; + this->__Vcellout__vx_register_file_master__out_regs[5U] + = this->__PVT__vx_register_file_master__DOT__registers + [5U]; + this->__Vcellout__vx_register_file_master__out_regs[4U] + = this->__PVT__vx_register_file_master__DOT__registers + [4U]; + this->__Vcellout__vx_register_file_master__out_regs[3U] + = this->__PVT__vx_register_file_master__DOT__registers + [3U]; + this->__Vcellout__vx_register_file_master__out_regs[2U] + = this->__PVT__vx_register_file_master__DOT__registers + [2U]; + this->__Vcellout__vx_register_file_master__out_regs[1U] + = this->__PVT__vx_register_file_master__DOT__registers + [1U]; + this->__Vcellout__vx_register_file_master__out_regs[0U] + = this->__PVT__vx_register_file_master__DOT__registers + [0U]; + this->__PVT__clone_regsiters[0x1fU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1fU]; + this->__PVT__clone_regsiters[0x1eU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1eU]; + this->__PVT__clone_regsiters[0x1dU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1dU]; + this->__PVT__clone_regsiters[0x1cU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1cU]; + this->__PVT__clone_regsiters[0x1bU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1bU]; + this->__PVT__clone_regsiters[0x1aU] = this->__Vcellout__vx_register_file_master__out_regs + [0x1aU]; + this->__PVT__clone_regsiters[0x19U] = this->__Vcellout__vx_register_file_master__out_regs + [0x19U]; + this->__PVT__clone_regsiters[0x18U] = this->__Vcellout__vx_register_file_master__out_regs + [0x18U]; + this->__PVT__clone_regsiters[0x17U] = this->__Vcellout__vx_register_file_master__out_regs + [0x17U]; + this->__PVT__clone_regsiters[0x16U] = this->__Vcellout__vx_register_file_master__out_regs + [0x16U]; + this->__PVT__clone_regsiters[0x15U] = this->__Vcellout__vx_register_file_master__out_regs + [0x15U]; + this->__PVT__clone_regsiters[0x14U] = this->__Vcellout__vx_register_file_master__out_regs + [0x14U]; + this->__PVT__clone_regsiters[0x13U] = this->__Vcellout__vx_register_file_master__out_regs + [0x13U]; + this->__PVT__clone_regsiters[0x12U] = this->__Vcellout__vx_register_file_master__out_regs + [0x12U]; + this->__PVT__clone_regsiters[0x11U] = this->__Vcellout__vx_register_file_master__out_regs + [0x11U]; + this->__PVT__clone_regsiters[0x10U] = this->__Vcellout__vx_register_file_master__out_regs + [0x10U]; + this->__PVT__clone_regsiters[0xfU] = this->__Vcellout__vx_register_file_master__out_regs + [0xfU]; + this->__PVT__clone_regsiters[0xeU] = this->__Vcellout__vx_register_file_master__out_regs + [0xeU]; + this->__PVT__clone_regsiters[0xdU] = this->__Vcellout__vx_register_file_master__out_regs + [0xdU]; + this->__PVT__clone_regsiters[0xcU] = this->__Vcellout__vx_register_file_master__out_regs + [0xcU]; + this->__PVT__clone_regsiters[0xbU] = this->__Vcellout__vx_register_file_master__out_regs + [0xbU]; + this->__PVT__clone_regsiters[0xaU] = this->__Vcellout__vx_register_file_master__out_regs + [0xaU]; + this->__PVT__clone_regsiters[9U] = this->__Vcellout__vx_register_file_master__out_regs + [9U]; + this->__PVT__clone_regsiters[8U] = this->__Vcellout__vx_register_file_master__out_regs + [8U]; + this->__PVT__clone_regsiters[7U] = this->__Vcellout__vx_register_file_master__out_regs + [7U]; + this->__PVT__clone_regsiters[6U] = this->__Vcellout__vx_register_file_master__out_regs + [6U]; + this->__PVT__clone_regsiters[5U] = this->__Vcellout__vx_register_file_master__out_regs + [5U]; + this->__PVT__clone_regsiters[4U] = this->__Vcellout__vx_register_file_master__out_regs + [4U]; + this->__PVT__clone_regsiters[3U] = this->__Vcellout__vx_register_file_master__out_regs + [3U]; + this->__PVT__clone_regsiters[2U] = this->__Vcellout__vx_register_file_master__out_regs + [2U]; + this->__PVT__clone_regsiters[1U] = this->__Vcellout__vx_register_file_master__out_regs + [1U]; + this->__PVT__clone_regsiters[0U] = this->__Vcellout__vx_register_file_master__out_regs + [0U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1fU] + = this->__PVT__clone_regsiters[0x1fU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1eU] + = this->__PVT__clone_regsiters[0x1eU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1dU] + = this->__PVT__clone_regsiters[0x1dU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1cU] + = this->__PVT__clone_regsiters[0x1cU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1bU] + = this->__PVT__clone_regsiters[0x1bU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x1aU] + = this->__PVT__clone_regsiters[0x1aU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x19U] + = this->__PVT__clone_regsiters[0x19U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x18U] + = this->__PVT__clone_regsiters[0x18U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x17U] + = this->__PVT__clone_regsiters[0x17U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x16U] + = this->__PVT__clone_regsiters[0x16U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x15U] + = this->__PVT__clone_regsiters[0x15U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x14U] + = this->__PVT__clone_regsiters[0x14U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x13U] + = this->__PVT__clone_regsiters[0x13U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x12U] + = this->__PVT__clone_regsiters[0x12U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x11U] + = this->__PVT__clone_regsiters[0x11U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0x10U] + = this->__PVT__clone_regsiters[0x10U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xfU] + = this->__PVT__clone_regsiters[0xfU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xeU] + = this->__PVT__clone_regsiters[0xeU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xdU] + = this->__PVT__clone_regsiters[0xdU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xcU] + = this->__PVT__clone_regsiters[0xcU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xbU] + = this->__PVT__clone_regsiters[0xbU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0xaU] + = this->__PVT__clone_regsiters[0xaU]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[9U] + = this->__PVT__clone_regsiters[9U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[8U] + = this->__PVT__clone_regsiters[8U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[7U] + = this->__PVT__clone_regsiters[7U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[6U] + = this->__PVT__clone_regsiters[6U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[5U] + = this->__PVT__clone_regsiters[5U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[4U] + = this->__PVT__clone_regsiters[4U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[3U] + = this->__PVT__clone_regsiters[3U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[2U] + = this->__PVT__clone_regsiters[2U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[1U] + = this->__PVT__clone_regsiters[1U]; + this->__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[0U] + = this->__PVT__clone_regsiters[0U]; +} + +void VVortex_VX_context_slave::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_context_slave::_ctor_var_reset\n"); ); + // Body + clk = VL_RAND_RESET_I(1); + in_warp = VL_RAND_RESET_I(1); + in_wb_warp = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + in_valid[__Vi0] = VL_RAND_RESET_I(1); + }} + in_write_register = VL_RAND_RESET_I(1); + in_rd = VL_RAND_RESET_I(5); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + in_write_data[__Vi0] = VL_RAND_RESET_I(32); + }} + in_src1 = VL_RAND_RESET_I(5); + in_src2 = VL_RAND_RESET_I(5); + in_curr_PC = VL_RAND_RESET_I(32); + in_is_clone = VL_RAND_RESET_I(1); + in_is_jal = VL_RAND_RESET_I(1); + in_src1_fwd = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + in_src2_fwd = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + in_wspawn_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + in_wspawn = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32); + }} + out_clone_stall = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + __PVT__rd1_register[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + __PVT__rd2_register[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__clone_regsiters[__Vi0] = VL_RAND_RESET_I(32); + }} + __PVT__clone_state_stall = VL_RAND_RESET_I(6); + __PVT__wspawn_state_stall = VL_RAND_RESET_I(6); + __Vcellout__vx_register_file_master__out_src2_data = VL_RAND_RESET_I(32); + __Vcellout__vx_register_file_master__out_src1_data = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __Vcellout__vx_register_file_master__out_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __Vcellinp__vx_register_file_master__in_wspawn_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + __Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data = VL_RAND_RESET_I(32); + __Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + __Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data = VL_RAND_RESET_I(32); + __Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + __Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data = VL_RAND_RESET_I(32); + __Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data = VL_RAND_RESET_I(32); + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__vx_register_file_master__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<32; ++__Vi0) { + __PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[__Vi0] = VL_RAND_RESET_I(32); + }} + __Vdly__clone_state_stall = VL_RAND_RESET_I(6); + __Vdly__wspawn_state_stall = VL_RAND_RESET_I(6); + __Vdlyvdim0__vx_register_file_master__DOT__registers__v0 = VL_RAND_RESET_I(5); + __Vdlyvval__vx_register_file_master__DOT__registers__v0 = VL_RAND_RESET_I(32); + __Vdlyvset__vx_register_file_master__DOT__registers__v0 = VL_RAND_RESET_I(1); + __Vdlyvval__vx_register_file_master__DOT__registers__v1 = VL_RAND_RESET_I(32); + __Vdlyvset__vx_register_file_master__DOT__registers__v1 = VL_RAND_RESET_I(1); + __Vdlyvval__vx_register_file_master__DOT__registers__v2 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v3 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v4 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v5 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v6 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v7 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v8 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v9 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v10 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v11 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v12 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v13 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v14 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v15 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v16 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v17 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v18 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v19 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v20 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v21 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v22 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v23 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v24 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v25 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v26 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v27 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v28 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v29 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v30 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v31 = VL_RAND_RESET_I(32); + __Vdlyvval__vx_register_file_master__DOT__registers__v32 = VL_RAND_RESET_I(32); + __Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = VL_RAND_RESET_I(5); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = VL_RAND_RESET_I(32); + __Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = VL_RAND_RESET_I(1); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = VL_RAND_RESET_I(32); + __Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = VL_RAND_RESET_I(1); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32 = VL_RAND_RESET_I(32); + __Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = VL_RAND_RESET_I(5); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = VL_RAND_RESET_I(32); + __Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0 = VL_RAND_RESET_I(1); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = VL_RAND_RESET_I(32); + __Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1 = VL_RAND_RESET_I(1); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32 = VL_RAND_RESET_I(32); + __Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = VL_RAND_RESET_I(5); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = VL_RAND_RESET_I(32); + __Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0 = VL_RAND_RESET_I(1); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = VL_RAND_RESET_I(32); + __Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1 = VL_RAND_RESET_I(1); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31 = VL_RAND_RESET_I(32); + __Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32 = VL_RAND_RESET_I(32); +} diff --git a/rtl/obj_dir/VVortex_VX_context_slave.h b/rtl/obj_dir/VVortex_VX_context_slave.h new file mode 100644 index 00000000..b2f32d7b --- /dev/null +++ b/rtl/obj_dir/VVortex_VX_context_slave.h @@ -0,0 +1,257 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design internal header +// See VVortex.h for the primary calling header + +#ifndef _VVortex_VX_context_slave_H_ +#define _VVortex_VX_context_slave_H_ + +#include "verilated.h" + +class VVortex__Syms; + +//---------- + +VL_MODULE(VVortex_VX_context_slave) { + public: + + // PORTS + // Begin mtask footprint all: + VL_IN8(clk,0,0); + VL_IN8(in_warp,0,0); + VL_IN8(in_wb_warp,0,0); + VL_IN8(in_write_register,0,0); + VL_IN8(in_rd,4,0); + VL_IN8(in_src1,4,0); + VL_IN8(in_src2,4,0); + VL_IN8(in_is_clone,0,0); + VL_IN8(in_is_jal,0,0); + VL_IN8(in_src1_fwd,0,0); + VL_IN8(in_src2_fwd,0,0); + VL_IN8(in_wspawn,0,0); + VL_OUT8(out_clone_stall,0,0); + VL_IN(in_curr_PC,31,0); + VL_IN8(in_valid[4],0,0); + VL_IN(in_write_data[4],31,0); + VL_IN(in_src1_fwd_data[4],31,0); + VL_IN(in_src2_fwd_data[4],31,0); + VL_IN(in_wspawn_regs[32],31,0); + VL_OUT(out_a_reg_data[4],31,0); + VL_OUT(out_b_reg_data[4],31,0); + + // LOCAL SIGNALS + // Begin mtask footprint all: + VL_SIG8(__PVT__clone_state_stall,5,0); + VL_SIG8(__PVT__wspawn_state_stall,5,0); + VL_SIG(__PVT__rd1_register[4],31,0); + VL_SIG(__PVT__rd2_register[4],31,0); + VL_SIG(__PVT__clone_regsiters[32],31,0); + VL_SIG(__PVT__vx_register_file_master__DOT__registers[32],31,0); + VL_SIG(__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0); + VL_SIG(__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0); + VL_SIG(__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0); + + // LOCAL VARIABLES + // Anonymous structures to workaround compiler member-count bugs + struct { + // Begin mtask footprint all: + VL_SIG8(__Vdly__clone_state_stall,5,0); + VL_SIG8(__Vdly__wspawn_state_stall,5,0); + VL_SIG8(__Vdlyvdim0__vx_register_file_master__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__vx_register_file_master__DOT__registers__v0,0,0); + VL_SIG8(__Vdlyvset__vx_register_file_master__DOT__registers__v1,0,0); + VL_SIG8(__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0); + VL_SIG8(__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0); + VL_SIG8(__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0); + VL_SIG8(__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0); + VL_SIG8(__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0); + VL_SIG8(__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0); + VL_SIG8(__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0); + VL_SIG(__Vcellout__vx_register_file_master__out_src2_data,31,0); + VL_SIG(__Vcellout__vx_register_file_master__out_src1_data,31,0); + VL_SIG(__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0); + VL_SIG(__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0); + VL_SIG(__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0); + VL_SIG(__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0); + VL_SIG(__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0); + VL_SIG(__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v0,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v1,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v2,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v3,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v4,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v5,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v6,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v7,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v8,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v9,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v10,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v11,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v12,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v13,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v14,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v15,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v16,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v17,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v18,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v19,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v20,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v21,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v22,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v23,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v24,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v25,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v26,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v27,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v28,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v29,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v30,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v31,31,0); + VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v32,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8,31,0); + }; + struct { + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6,31,0); + }; + struct { + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31,31,0); + VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32,31,0); + VL_SIG(__Vcellout__vx_register_file_master__out_regs[32],31,0); + VL_SIG(__Vcellinp__vx_register_file_master__in_wspawn_regs[32],31,0); + VL_SIG(__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0); + VL_SIG(__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[32],31,0); + VL_SIG(__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[32],31,0); + }; + + // INTERNAL VARIABLES + private: + VVortex__Syms* __VlSymsp; // Symbol table + public: + + // PARAMETERS + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(VVortex_VX_context_slave); ///< Copying not allowed + public: + VVortex_VX_context_slave(const char* name="TOP"); + ~VVortex_VX_context_slave(); + + // API METHODS + + // INTERNAL METHODS + void __Vconfigure(VVortex__Syms* symsp, bool first); + void _combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__29(VVortex__Syms* __restrict vlSymsp); + void _combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__36(VVortex__Syms* __restrict vlSymsp); + private: + void _ctor_var_reset(); + public: + void _initial__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__1(VVortex__Syms* __restrict vlSymsp); + void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__15(VVortex__Syms* __restrict vlSymsp); + void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__22(VVortex__Syms* __restrict vlSymsp); + void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one__16(VVortex__Syms* __restrict vlSymsp); + void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one__17(VVortex__Syms* __restrict vlSymsp); + void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one__18(VVortex__Syms* __restrict vlSymsp); + void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one__19(VVortex__Syms* __restrict vlSymsp); + void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one__20(VVortex__Syms* __restrict vlSymsp); + void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one__21(VVortex__Syms* __restrict vlSymsp); + void _settle__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__8(VVortex__Syms* __restrict vlSymsp); +} VL_ATTR_ALIGNED(128); + +#endif // guard diff --git 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a/rtl/obj_dir/VVortex__ALLsup.d b/rtl/obj_dir/VVortex__ALLsup.d new file mode 100644 index 00000000..290c1bbe --- /dev/null +++ b/rtl/obj_dir/VVortex__ALLsup.d @@ -0,0 +1,4 @@ +VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \ + VVortex.h VVortex_VX_context_slave.h diff --git a/rtl/obj_dir/VVortex__ALLsup.o b/rtl/obj_dir/VVortex__ALLsup.o new file mode 100644 index 0000000000000000000000000000000000000000..d79eef463cfe352784cbd0b6d58b174999a79939 GIT binary patch literal 3876 zcmb7HZERCj7(N|iyL@f+6Ht>a$`6coSqF9F4;ggT>&8f7Y%c0@)^(Szv1@17%_5GJ zRLpM5$Vfy^3n zpcq-Al5imB(ZNhQo{UMaTkn$8^U1krl;c(+Zf)qL`UfJ>3?E9q7EktazNJaU65cHn zR<{5)u!J#MgH_AzIde#IZuIe;=}5mJ65RE5(qyBZ5x^#;UL*9Vh`u zzpfYB@q7i3lh;WSHhe>qy7}61ztrhAkQh{j35dl zm!NRQ@=8x=QeVt4K|(5YT4kJ2Qrm>o2}K-JQl}wx%q^9>&z3r@GRBpZUr3EBVpK^T zhSaEAialaWb1Q?zdG>$X$J0zYCk z^}+ z*3KRa>=xqWQsQfEx-da$5GR*I{El8|#lG6))$=znZ`c!suva&mHMKXu7Pi5&*{kpU zOsugTvQIcveO42Bbk~E;ABn@poa_@yHjIZmw`L%9_rp(rBH*Uh7vA%Fv zCmq(P!=mGPCNJo)s%Bf*%JzP-ULN_{S$l0}B9*t#u{)%9M7)Bt(?`S$?r@3Y!{HK# zlfyM@^(;Tmo++!2%4M{I=Amj;LS&C)g2 z!?+cnzg6u#Oeq%!D-KZ+p1)Atb)HQhdEV2=HZr!c;m>krdK&T?`_9vFP-90+nvQDh zuaf3d8vAxp^T!%HUD|wEV+YEvdah_}N_*F{f2rs1C2QnA4#qlCY5Zfa8P4)vBbw?p zYGOvRC-I8^C4W~apBiY&SGn2h(o;BOIG5yl<5RSIFxLd(hUi)I3UuH0ZlJWtyxPBXZ_bToZb?jFWZG ziKBnsxO@0ofVgt_HUlewD}klJG9dnZzr(;)$2SGUjm7t+#Iq8QOMF}69*KPtf5s(C zL*7M+CnfHen3A|%VnE_b;4NiTP^u}m}}y11Bw4ZpzjkP z<-aHSgOcAPc`o^&O`IjZ%Ci$S` zp8#U*eT_hTRavz}x)Wk(WppR3w3bHj4+y*UGJ-1*p!V@kE?f8F{H zaolp8tWkNg4kjYQMw8!4<name(),"Vortex.vx_decode.genblk1[1].VX_Context_one")) + , TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[2].VX_Context_one")) + , TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[3].VX_Context_one")) + , TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[4].VX_Context_one")) + , TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[5].VX_Context_one")) + , TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[6].VX_Context_one")) + , TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[7].VX_Context_one")) +{ + // Pointer to top level + TOPp = topp; + // Setup each module's pointers to their submodules + TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one; + TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one; + TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one; + TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one; + TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one; + TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one; + TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one; + // Setup each module's pointer back to symbol table (for public functions) + TOPp->__Vconfigure(this, true); + TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.__Vconfigure(this, true); + TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.__Vconfigure(this, false); + TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.__Vconfigure(this, false); + TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.__Vconfigure(this, false); + TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.__Vconfigure(this, false); + TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.__Vconfigure(this, false); + TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.__Vconfigure(this, false); +} diff --git a/rtl/obj_dir/VVortex__Syms.h b/rtl/obj_dir/VVortex__Syms.h new file mode 100644 index 00000000..10ad45e9 --- /dev/null +++ b/rtl/obj_dir/VVortex__Syms.h @@ -0,0 +1,42 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table internal header +// +// Internal details; most calling programs do not need this header + +#ifndef _VVortex__Syms_H_ +#define _VVortex__Syms_H_ + +#include "verilated.h" + +// INCLUDE MODULE CLASSES +#include "VVortex.h" +#include "VVortex_VX_context_slave.h" + +// SYMS CLASS +class VVortex__Syms : public VerilatedSyms { + public: + + // LOCAL STATE + const char* __Vm_namep; + bool __Vm_didInit; + + // SUBCELL STATE + VVortex* TOPp; + VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one; + VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one; + VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one; + VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one; + VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one; + VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one; + VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one; + + // CREATORS + VVortex__Syms(VVortex* topp, const char* namep); + ~VVortex__Syms() {} + + // METHODS + inline const char* name() { return __Vm_namep; } + +} VL_ATTR_ALIGNED(64); + +#endif // guard diff --git a/rtl/obj_dir/VVortex__ver.d b/rtl/obj_dir/VVortex__ver.d new file mode 100644 index 00000000..9727d17d --- /dev/null +++ b/rtl/obj_dir/VVortex__ver.d @@ -0,0 +1 @@ +obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_context_slave.cpp obj_dir/VVortex_VX_context_slave.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v diff --git a/rtl/obj_dir/VVortex__verFiles.dat b/rtl/obj_dir/VVortex__verFiles.dat new file mode 100644 index 00000000..10bf5d85 --- /dev/null +++ b/rtl/obj_dir/VVortex__verFiles.dat @@ -0,0 +1,33 @@ +# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. +C "-Wall -cc Vortex.v --exe test_bench.cpp" +S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin" +S 2785 12891069980 1560309956 0 1560309956 0 "VX_alu.v" +S 3553 12891069981 1560309956 0 1560309956 0 "VX_context.v" +S 4995 12891069982 1560309956 0 1560309956 0 "VX_context_slave.v" +S 1699 12891069983 1560311423 0 1560311423 0 "VX_csr_handler.v" +S 5512 12891069984 1560309956 0 1560309956 0 "VX_d_e_reg.v" +S 17808 12891069985 1560309956 0 1560309956 0 "VX_decode.v" +S 1676 12891069987 1560310232 0 1560310232 0 "VX_define.v" +S 4267 12891069988 1560309956 0 1560309956 0 "VX_e_m_reg.v" +S 3692 12891069989 1560309956 0 1560309956 0 "VX_execute.v" +S 1751 12891069990 1560309956 0 1560309956 0 "VX_f_d_reg.v" +S 6204 12891069991 1560310568 0 1560310568 0 "VX_fetch.v" +S 6293 12891069992 1560309956 0 1560309956 0 "VX_forwarding.v" +S 1866 12891069993 1560309956 0 1560309956 0 "VX_m_w_reg.v" +S 4352 12891069994 1560310451 0 1560310451 0 "VX_memory.v" +S 1249 12891069995 1560309956 0 1560309956 0 "VX_register_file.v" +S 1655 12891069996 1560309956 0 1560309956 0 "VX_register_file_master_slave.v" +S 1599 12891069997 1560309956 0 1560309956 0 "VX_register_file_slave.v" +S 1915 12891069999 1560309956 0 1560309956 0 "VX_warp.v" +S 1568 12891070000 1560309956 0 1560309956 0 "VX_writeback.v" +S 18828 12891070001 1560309956 0 1560309956 0 "Vortex.v" +T 937577 12891114882 1560311425 0 1560311425 0 "obj_dir/VVortex.cpp" +T 33907 12891114881 1560311425 0 1560311425 0 "obj_dir/VVortex.h" +T 1800 12891114886 1560311425 0 1560311425 0 "obj_dir/VVortex.mk" +T 597541 12891114884 1560311425 0 1560311425 0 "obj_dir/VVortex_VX_context_slave.cpp" +T 19362 12891114883 1560311425 0 1560311425 0 "obj_dir/VVortex_VX_context_slave.h" +T 3668 12891114880 1560311425 0 1560311425 0 "obj_dir/VVortex__Syms.cpp" +T 1547 12891114879 1560311425 0 1560311425 0 "obj_dir/VVortex__Syms.h" +T 635 12891114889 1560311425 0 1560311425 0 "obj_dir/VVortex__ver.d" +T 0 0 1560311425 0 1560311425 0 "obj_dir/VVortex__verFiles.dat" +T 1187 12891114885 1560311425 0 1560311425 0 "obj_dir/VVortex_classes.mk" diff --git a/rtl/obj_dir/VVortex_classes.mk b/rtl/obj_dir/VVortex_classes.mk new file mode 100644 index 00000000..2fa0955e --- /dev/null +++ b/rtl/obj_dir/VVortex_classes.mk @@ -0,0 +1,39 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Make include file with class lists +# +# This file lists generated Verilated files, for including in higher level makefiles. +# See VVortex.mk for the caller. + +### Switches... +# Coverage output mode? 0/1 (from --coverage) +VM_COVERAGE = 0 +# Threaded output mode? 0/1/N threads (from --threads) +VM_THREADS = 0 +# Tracing output mode? 0/1 (from --trace) +VM_TRACE = 0 + +### Object file lists... +# Generated module classes, fast-path, compile with highest optimization +VM_CLASSES_FAST += \ + VVortex \ + VVortex_VX_context_slave \ + +# Generated module classes, non-fast-path, compile with low/medium optimization +VM_CLASSES_SLOW += \ + +# Generated support classes, fast-path, compile with highest optimization +VM_SUPPORT_FAST += \ + +# Generated support classes, non-fast-path, compile with low/medium optimization +VM_SUPPORT_SLOW += \ + VVortex__Syms \ + +# Global classes, need linked once per executable, fast-path, compile with highest optimization +VM_GLOBAL_FAST += \ + verilated \ + +# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization +VM_GLOBAL_SLOW += \ + + +# Verilated -*- Makefile -*- diff --git a/rtl/obj_dir/test_bench.d b/rtl/obj_dir/test_bench.d new file mode 100644 index 00000000..b918f78f --- /dev/null +++ b/rtl/obj_dir/test_bench.d @@ -0,0 +1,4 @@ +test_bench.o: ../test_bench.cpp ../test_bench.h ../VX_define.h ../ram.h \ + VVortex.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \ + /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h 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a/rtl/ram.h b/rtl/ram.h index d3a0bb30..1614fdc2 100644 --- a/rtl/ram.h +++ b/rtl/ram.h @@ -4,7 +4,8 @@ #define __RAM__ #include "string.h" - +#include +#include class RAM{ public: uint8_t* mem[1 << 12]; diff --git a/rtl/results.txt b/rtl/results.txt index e69de29b..caa523d8 100644 --- a/rtl/results.txt +++ b/rtl/results.txt @@ -0,0 +1,7 @@ +# Dynamic Instructions: 173969 +# of total cycles: 175806 +# of forwarding stalls: 0 +# of branch stalls: 0 +# CPI: 1.01056 +# time to simulate: 6.95312e-310 milliseconds +# GRADE: Failed on test: 4294967295 diff --git a/rtl/test_bench.h b/rtl/test_bench.h index df92dead..22c7314a 100644 --- a/rtl/test_bench.h +++ b/rtl/test_bench.h @@ -189,17 +189,17 @@ bool Vortex::dbus_driver() std::cerr << (char) data_write; } - if ((addr >= 0x810002cc) && (addr < 0x810002d0)) - { - int index = (addr - 0x810002cc) / 4; - std::cerr << GREEN << "1done[" << index << "] = " << data_write << DEFAULT << "\n"; - } + // if ((addr >= 0x810002cc) && (addr < 0x810002d0)) + // { + // int index = (addr - 0x810002cc) / 4; + // // std::cerr << GREEN << "1done[" << index << "] = " << data_write << DEFAULT << "\n"; + // } - if ((addr >= 0x810059f4) && (addr < 0x810059f4)) - { - int index = (addr - 0x810059f4) / 4; - std::cerr << RED << "2done[" << index << "] = " << data_write << DEFAULT << "\n"; - } + // if ((addr >= 0x810059f4) && (addr < 0x810059f4)) + // { + // int index = (addr - 0x810059f4) / 4; + // // std::cerr << RED << "2done[" << index << "] = " << data_write << DEFAULT << "\n"; + // } if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE) { @@ -248,7 +248,7 @@ bool Vortex::dbus_driver() { // printf("Reading mem - Addr: %x = %x\n", addr, data_read); // std::cout << "READING - Addr: " << std::hex << addr << " = " << data_read << "\n"; - std::cout << std::dec; + // std::cout << std::dec; vortex->in_cache_driver_out_data[curr_th] = data_read; } else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ) diff --git a/rtl/worst_case_paths.rpt b/rtl/worst_case_paths.rpt new file mode 100644 index 00000000..98f8d7ef --- /dev/null +++ b/rtl/worst_case_paths.rpt @@ -0,0 +1,215904 @@ +---------------- +; Command Info ; +---------------- +Report Timing: Found 2000 setup paths (2000 violated). Worst case slack is -0.962 + +Tcl Command: + report_timing -setup -multi_corner -file worst_case_paths.rpt -panel_name {Report Timing} -npaths 2000 -detail full_path + +Options: + -setup + -npaths 2000 + -detail full_path + -panel_name {Report Timing} + -file {worst_case_paths.rpt} + -multi_corner + +Snapshot: + final + +Delay Model: + Fast 900mV 100C Model + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Summary of Paths ; ++--------+----------------------------------------------------------------------+--------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+----------------------------------------------------------------------+--------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+ +; -0.962 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.107 ; 2.489 ; +; -0.960 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_three|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.107 ; 2.488 ; +; -0.946 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_one|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.107 ; 2.475 ; +; -0.932 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.482 ; +; -0.932 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.483 ; +; -0.931 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.480 ; +; -0.924 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.512 ; +; -0.913 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.514 ; +; -0.910 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.484 ; +; -0.909 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.459 ; +; -0.898 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.510 ; +; -0.898 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.502 ; +; -0.895 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.367 ; +; -0.893 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.488 ; +; -0.887 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.476 ; +; -0.887 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.476 ; +; -0.886 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.483 ; +; -0.883 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.480 ; +; -0.878 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.452 ; +; -0.875 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.425 ; +; -0.875 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.426 ; +; -0.874 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.423 ; +; -0.870 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.444 ; +; -0.869 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.445 ; +; -0.869 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.444 ; +; -0.867 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.455 ; +; -0.866 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.478 ; +; -0.866 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.455 ; +; -0.865 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.455 ; +; -0.861 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.456 ; +; -0.858 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.470 ; +; -0.855 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.444 ; +; -0.855 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.444 ; +; -0.855 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.444 ; +; -0.854 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.457 ; +; -0.854 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.443 ; +; -0.853 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.448 ; +; -0.852 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.402 ; +; -0.852 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.453 ; +; -0.849 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.399 ; +; -0.849 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.400 ; +; -0.848 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.397 ; +; -0.848 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.119 ; 3.361 ; +; -0.847 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.436 ; +; -0.847 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.436 ; +; -0.846 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.420 ; +; -0.844 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.441 ; +; -0.844 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.418 ; +; -0.844 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.438 ; +; -0.843 ; vx_f_d_reg|instruction[22] ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.141 ; 3.264 ; +; -0.843 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.451 ; +; -0.842 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.393 ; +; -0.842 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.392 ; +; -0.842 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.439 ; +; -0.842 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.437 ; +; -0.841 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.390 ; +; -0.841 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.429 ; +; -0.841 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.451 ; +; -0.841 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.437 ; +; -0.838 ; vx_f_d_reg|instruction[12] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.310 ; +; -0.837 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.441 ; +; -0.837 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.104 ; 2.367 ; +; -0.836 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.433 ; +; -0.836 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.425 ; +; -0.835 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_three|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.104 ; 2.366 ; +; -0.834 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.422 ; +; -0.834 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.423 ; +; -0.834 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.431 ; +; -0.834 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.446 ; +; -0.833 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.423 ; +; -0.833 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.407 ; +; -0.833 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.390 ; +; -0.833 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.390 ; +; -0.832 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.444 ; +; -0.831 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.387 ; +; -0.830 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_two|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.094 ; 2.410 ; +; -0.829 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.424 ; +; -0.828 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.245 ; +; -0.827 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.422 ; +; -0.827 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.245 ; +; -0.826 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.376 ; +; -0.826 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.415 ; +; -0.826 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.427 ; +; -0.826 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.379 ; +; -0.825 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.415 ; +; -0.825 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.400 ; +; -0.824 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.425 ; +; -0.824 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.400 ; +; -0.824 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.426 ; +; -0.823 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.412 ; +; -0.823 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.412 ; +; -0.823 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.419 ; +; -0.822 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.411 ; +; -0.822 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_three|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.113 ; 2.379 ; +; -0.821 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.410 ; +; -0.821 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.410 ; +; -0.821 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.433 ; +; -0.821 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.373 ; +; -0.821 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_one|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.104 ; 2.353 ; +; -0.820 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.371 ; +; -0.820 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.370 ; +; -0.820 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.394 ; +; -0.819 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.369 ; +; -0.819 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.368 ; +; -0.819 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.375 ; +; -0.818 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.426 ; +; -0.817 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.392 ; +; -0.816 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.392 ; +; -0.816 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.411 ; +; -0.815 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.389 ; +; -0.813 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.424 ; +; -0.812 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.400 ; +; -0.812 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.406 ; +; -0.812 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.409 ; +; -0.812 ; vx_f_d_reg|instruction[14] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.284 ; +; -0.812 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.398 ; +; -0.812 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.424 ; +; -0.810 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.405 ; +; -0.810 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.407 ; +; -0.810 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.407 ; +; -0.810 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.399 ; +; -0.810 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.399 ; +; -0.809 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.413 ; +; -0.809 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.405 ; +; -0.809 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.383 ; +; -0.808 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.405 ; +; -0.808 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.420 ; +; -0.806 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.407 ; +; -0.805 ; vx_f_d_reg|instruction[3] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.277 ; +; -0.804 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.398 ; +; -0.804 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.393 ; +; -0.803 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.406 ; +; -0.803 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.398 ; +; -0.803 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.415 ; +; -0.803 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.389 ; +; -0.803 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.393 ; +; -0.803 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.393 ; +; -0.802 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.397 ; +; -0.802 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.391 ; +; -0.802 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.418 ; +; -0.801 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.397 ; +; -0.801 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.391 ; +; -0.801 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.402 ; +; -0.801 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.351 ; +; -0.801 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.352 ; +; -0.800 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.389 ; +; -0.800 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.398 ; +; -0.800 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.356 ; +; -0.800 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.357 ; +; -0.800 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.349 ; +; -0.799 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.389 ; +; -0.799 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.396 ; +; -0.799 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.401 ; +; -0.799 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[4] ; clk ; clk ; 2.500 ; -0.025 ; 3.258 ; +; -0.799 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.354 ; +; -0.799 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.075 ; 3.355 ; +; -0.799 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.266 ; +; -0.799 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[7] ; clk ; clk ; 2.500 ; -0.031 ; 3.266 ; +; -0.798 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.387 ; +; -0.798 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.393 ; +; -0.798 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[24] ; clk ; clk ; 2.500 ; -0.075 ; 3.355 ; +; -0.798 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.401 ; +; -0.797 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.386 ; +; -0.797 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.347 ; +; -0.797 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.394 ; +; -0.797 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.386 ; +; -0.797 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.386 ; +; -0.797 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.409 ; +; -0.797 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.384 ; +; -0.797 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[19] ; clk ; clk ; 2.500 ; -0.075 ; 3.353 ; +; -0.796 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.397 ; +; -0.796 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.385 ; +; -0.796 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.258 ; +; -0.796 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[31] ; clk ; clk ; 2.500 ; -0.075 ; 3.351 ; +; -0.795 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.398 ; +; -0.795 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[10] ; clk ; clk ; 2.500 ; -0.025 ; 3.258 ; +; -0.795 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.380 ; +; -0.794 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.395 ; +; -0.794 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.397 ; +; -0.793 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.368 ; +; -0.793 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.381 ; +; -0.793 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.349 ; +; -0.793 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.350 ; +; -0.792 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.394 ; +; -0.792 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.368 ; +; -0.792 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.381 ; +; -0.792 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.381 ; +; -0.792 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.387 ; +; -0.792 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.386 ; +; -0.792 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.347 ; +; -0.791 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.395 ; +; -0.791 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.387 ; +; -0.791 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.366 ; +; -0.790 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.366 ; +; -0.789 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.393 ; +; -0.789 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.340 ; +; -0.789 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.339 ; +; -0.789 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.378 ; +; -0.788 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.337 ; +; -0.788 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.378 ; +; -0.788 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.374 ; +; -0.787 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.375 ; +; -0.786 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.394 ; +; -0.786 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.387 ; +; -0.786 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.383 ; +; -0.786 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.375 ; +; -0.786 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.375 ; +; -0.785 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.379 ; +; -0.784 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.386 ; +; -0.784 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.381 ; +; -0.783 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.379 ; +; -0.783 ; vx_f_d_reg|instruction[13] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.255 ; +; -0.783 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[11] ; clk ; clk ; 2.500 ; -0.089 ; 3.177 ; +; -0.783 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[1] ; clk ; clk ; 2.500 ; -0.089 ; 3.177 ; +; -0.783 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; clk ; clk ; 2.500 ; -0.089 ; 3.177 ; +; -0.782 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.390 ; +; -0.782 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_two|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.090 ; 2.366 ; +; -0.781 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.369 ; +; -0.781 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.378 ; +; -0.781 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.383 ; +; -0.781 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[1] ; clk ; clk ; 2.500 ; -0.028 ; 3.251 ; +; -0.781 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[0] ; clk ; clk ; 2.500 ; -0.028 ; 3.251 ; +; -0.781 ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.001 ; 3.416 ; +; -0.780 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.390 ; +; -0.780 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.374 ; +; -0.780 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.355 ; +; -0.780 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[10] ; clk ; clk ; 2.500 ; -0.089 ; 3.177 ; +; -0.780 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_one|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.108 ; 2.342 ; +; -0.780 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_two|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.108 ; 2.341 ; +; -0.780 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[3] ; clk ; clk ; 2.500 ; -0.089 ; 3.177 ; +; -0.779 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.367 ; +; -0.779 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.355 ; +; -0.779 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.376 ; +; -0.778 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.363 ; +; -0.778 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.386 ; +; -0.778 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.373 ; +; -0.778 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.372 ; +; -0.778 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.328 ; +; -0.777 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.373 ; +; -0.777 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.351 ; +; -0.777 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.220 ; +; -0.777 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.220 ; +; -0.777 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.220 ; +; -0.777 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.333 ; +; -0.776 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.371 ; +; -0.776 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.365 ; +; -0.776 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[0] ; clk ; clk ; 2.500 ; -0.080 ; 3.220 ; +; -0.776 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[28] ; clk ; clk ; 2.500 ; -0.075 ; 3.332 ; +; -0.776 ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.001 ; 3.408 ; +; -0.775 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.371 ; +; -0.775 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.365 ; +; -0.775 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.372 ; +; -0.775 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.370 ; +; -0.775 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_two|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.090 ; 2.359 ; +; -0.773 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.370 ; +; -0.772 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.361 ; +; -0.772 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.329 ; +; -0.772 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.329 ; +; -0.772 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.361 ; +; -0.771 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.360 ; +; -0.771 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.360 ; +; -0.770 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.371 ; +; -0.770 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.386 ; +; -0.770 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.355 ; +; -0.770 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.326 ; +; -0.770 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.359 ; +; -0.770 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.373 ; +; -0.770 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.360 ; +; -0.770 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.326 ; +; -0.770 ; vx_csr_handler|decode_csr_address[2] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.397 ; +; -0.769 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.370 ; +; -0.769 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.355 ; +; -0.769 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.370 ; +; -0.768 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.366 ; +; -0.768 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.371 ; +; -0.767 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.369 ; +; -0.767 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.361 ; +; -0.767 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.342 ; +; -0.767 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.184 ; +; -0.767 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.371 ; +; -0.766 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.316 ; +; -0.766 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.369 ; +; -0.766 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.342 ; +; -0.766 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.184 ; +; -0.765 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.354 ; +; -0.765 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.318 ; +; -0.765 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.360 ; +; -0.765 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.354 ; +; -0.765 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.039 ; 3.377 ; +; -0.765 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[25] ; clk ; clk ; 2.500 ; -0.077 ; 3.320 ; +; -0.765 ; vx_csr_handler|decode_csr_address[2] ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.389 ; +; -0.764 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.353 ; +; -0.764 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.360 ; +; -0.764 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.354 ; +; -0.764 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.349 ; +; -0.764 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.372 ; +; -0.763 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.366 ; +; -0.763 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.348 ; +; -0.763 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_address[0] ; clk ; clk ; 2.500 ; -0.121 ; 3.277 ; +; -0.763 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.337 ; +; -0.762 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.378 ; +; -0.762 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.363 ; +; -0.762 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.337 ; +; -0.762 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.359 ; +; -0.761 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.362 ; +; -0.761 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.347 ; +; -0.761 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.337 ; +; -0.761 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.362 ; +; -0.761 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.341 ; +; -0.761 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.354 ; +; -0.761 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_three|real_PC[25] ; clk (INVERTED) ; clk ; 1.500 ; -0.113 ; 2.317 ; +; -0.760 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.358 ; +; -0.760 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.312 ; +; -0.760 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.362 ; +; -0.760 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.361 ; +; -0.760 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.355 ; +; -0.760 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; clk (INVERTED) ; clk ; 1.500 ; -0.113 ; 2.317 ; +; -0.759 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.346 ; +; -0.759 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.361 ; +; -0.759 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.355 ; +; -0.759 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.348 ; +; -0.759 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.355 ; +; -0.759 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.374 ; +; -0.759 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.357 ; +; -0.758 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.308 ; +; -0.758 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.309 ; +; -0.758 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.361 ; +; -0.758 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.314 ; +; -0.758 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.360 ; +; -0.758 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[9] ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; +; -0.758 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[14] ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; +; -0.758 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.350 ; +; -0.758 ; vx_f_d_reg|instruction[22] ; vx_csr_handler|decode_csr_address[4] ; clk ; clk ; 2.500 ; -0.141 ; 3.264 ; +; -0.757 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.306 ; +; -0.757 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.308 ; +; -0.757 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.307 ; +; -0.757 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.353 ; +; -0.757 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.360 ; +; -0.757 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[8] ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; +; -0.757 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; +; -0.756 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.305 ; +; -0.756 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.342 ; +; -0.756 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.331 ; +; -0.756 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.339 ; +; -0.756 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.364 ; +; -0.756 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[16] ; clk ; clk ; 2.500 ; -0.078 ; 3.309 ; +; -0.755 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.359 ; +; -0.755 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.358 ; +; -0.755 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.340 ; +; -0.755 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.343 ; +; -0.755 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.331 ; +; -0.755 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[16] ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; +; -0.755 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[17] ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; +; -0.755 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[20] ; clk ; clk ; 2.500 ; -0.021 ; 3.221 ; +; -0.754 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.362 ; +; -0.754 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.362 ; +; -0.754 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.348 ; +; -0.754 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.343 ; +; -0.754 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.343 ; +; -0.754 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.355 ; +; -0.754 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.355 ; +; -0.753 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.341 ; +; -0.753 ; vx_f_d_reg|instruction[23] ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.141 ; 3.174 ; +; -0.753 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.360 ; +; -0.753 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.367 ; +; -0.753 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[17] ; clk ; clk ; 2.500 ; -0.078 ; 3.307 ; +; -0.752 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.363 ; +; -0.752 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.362 ; +; -0.752 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.360 ; +; -0.752 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.347 ; +; -0.752 ; vx_f_d_reg|instruction[4] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.224 ; +; -0.752 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.359 ; +; -0.752 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.355 ; +; -0.751 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.363 ; +; -0.751 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.338 ; +; -0.751 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.347 ; +; -0.751 ; vx_d_e_reg|b_reg_data[1] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.079 ; 3.308 ; +; -0.750 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.338 ; +; -0.750 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.348 ; +; -0.749 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.337 ; +; -0.749 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.351 ; +; -0.749 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.350 ; +; -0.749 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.343 ; +; -0.748 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.334 ; +; -0.748 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.352 ; +; -0.748 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_three|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.098 ; 2.320 ; +; -0.748 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.331 ; +; -0.747 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.349 ; +; -0.747 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.342 ; +; -0.747 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.357 ; +; -0.746 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.336 ; +; -0.746 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.336 ; +; -0.746 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.331 ; +; -0.746 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.342 ; +; -0.746 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.335 ; +; -0.746 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.342 ; +; -0.746 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.352 ; +; -0.745 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[1] ; clk ; clk ; 2.500 ; -0.082 ; 3.295 ; +; -0.744 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.295 ; +; -0.744 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.294 ; +; -0.744 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.329 ; +; -0.744 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.301 ; +; -0.744 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.301 ; +; -0.744 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.347 ; +; -0.744 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.352 ; +; -0.743 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.332 ; +; -0.743 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.292 ; +; -0.743 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.338 ; +; -0.743 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.337 ; +; -0.743 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; clk ; clk ; 2.500 ; -0.055 ; 3.340 ; +; -0.742 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.331 ; +; -0.742 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.330 ; +; -0.742 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.298 ; +; -0.742 ; vx_f_d_reg|instruction[12] ; vx_f_d_reg|curr_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.209 ; +; -0.742 ; vx_f_d_reg|instruction[12] ; vx_f_d_reg|curr_PC[7] ; clk ; clk ; 2.500 ; -0.031 ; 3.209 ; +; -0.742 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.338 ; +; -0.742 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.325 ; +; -0.742 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.349 ; +; -0.741 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.343 ; +; -0.741 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.349 ; +; -0.741 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.336 ; +; -0.741 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.344 ; +; -0.741 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.055 ; 3.338 ; +; -0.741 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.330 ; +; -0.740 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.336 ; +; -0.740 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.350 ; +; -0.740 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.338 ; +; -0.740 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.347 ; +; -0.740 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[3] ; clk ; clk ; 2.500 ; -0.066 ; 3.306 ; +; -0.740 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[2] ; clk ; clk ; 2.500 ; -0.066 ; 3.306 ; +; -0.739 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.156 ; +; -0.739 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.320 ; +; -0.739 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.125 ; 3.246 ; +; -0.739 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.338 ; +; -0.738 ; vx_csr_handler|decode_csr_address[2] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.365 ; +; -0.738 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[4] ; clk ; clk ; 2.500 ; -0.025 ; 3.197 ; +; -0.738 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.345 ; +; -0.738 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.075 ; 3.294 ; +; -0.738 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.354 ; +; -0.738 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.156 ; +; -0.738 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.338 ; +; -0.738 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.343 ; +; -0.738 ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; vx_e_m_reg|alu_result[7] ; clk ; clk ; 2.500 ; -0.083 ; 3.293 ; +; -0.737 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[24] ; clk ; clk ; 2.500 ; -0.075 ; 3.294 ; +; -0.737 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.338 ; +; -0.737 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.323 ; +; -0.737 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.290 ; +; -0.736 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.344 ; +; -0.736 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.324 ; +; -0.736 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[19] ; clk ; clk ; 2.500 ; -0.075 ; 3.292 ; +; -0.736 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.334 ; +; -0.736 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.352 ; +; -0.736 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.337 ; +; -0.736 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_one|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.346 ; +; -0.735 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.285 ; +; -0.735 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.197 ; +; -0.735 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.330 ; +; -0.735 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[31] ; clk ; clk ; 2.500 ; -0.075 ; 3.290 ; +; -0.735 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.337 ; +; -0.735 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.336 ; +; -0.735 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.321 ; +; -0.735 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.324 ; +; -0.734 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.344 ; +; -0.734 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.284 ; +; -0.734 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[10] ; clk ; clk ; 2.500 ; -0.025 ; 3.197 ; +; -0.734 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.341 ; +; -0.734 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.337 ; +; -0.734 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.332 ; +; -0.734 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.336 ; +; -0.734 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.119 ; 3.247 ; +; -0.734 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.332 ; +; -0.734 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.335 ; +; -0.734 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.351 ; +; -0.734 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.335 ; +; -0.734 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.351 ; +; -0.733 ; vx_csr_handler|decode_csr_address[2] ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.357 ; +; -0.733 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.335 ; +; -0.733 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.318 ; +; -0.733 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.329 ; +; -0.733 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.336 ; +; -0.733 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.322 ; +; -0.733 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; clk ; clk ; 2.500 ; -0.040 ; 3.325 ; +; -0.733 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.336 ; +; -0.732 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.317 ; +; -0.732 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.335 ; +; -0.732 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.284 ; +; -0.732 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.322 ; +; -0.732 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.325 ; +; -0.732 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.316 ; +; -0.732 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.330 ; +; -0.732 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.338 ; +; -0.731 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.305 ; +; -0.731 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.316 ; +; -0.731 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.334 ; +; -0.731 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.332 ; +; -0.731 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.348 ; +; -0.730 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.331 ; +; -0.730 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.286 ; +; -0.730 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.330 ; +; -0.730 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.326 ; +; -0.730 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.332 ; +; -0.730 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.343 ; +; -0.730 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; clk ; clk ; 2.500 ; -0.037 ; 3.326 ; +; -0.730 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.342 ; +; -0.729 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.286 ; +; -0.729 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.285 ; +; -0.729 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.309 ; +; -0.729 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.322 ; +; -0.729 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.314 ; +; -0.729 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.332 ; +; -0.729 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.317 ; +; -0.729 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.331 ; +; -0.729 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.330 ; +; -0.729 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.330 ; +; -0.729 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.335 ; +; -0.728 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.283 ; +; -0.728 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.285 ; +; -0.728 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.284 ; +; -0.728 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.336 ; +; -0.728 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.324 ; +; -0.728 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.280 ; +; -0.728 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.347 ; +; -0.728 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.032 ; 3.348 ; +; -0.727 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.342 ; +; -0.727 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.323 ; +; -0.727 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.282 ; +; -0.727 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.314 ; +; -0.727 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.324 ; +; -0.727 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; clk ; clk ; 2.500 ; -0.051 ; 3.327 ; +; -0.726 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.334 ; +; -0.726 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.318 ; +; -0.726 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.283 ; +; -0.726 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.283 ; +; -0.726 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.333 ; +; -0.726 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.334 ; +; -0.725 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.312 ; +; -0.725 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.341 ; +; -0.725 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.326 ; +; -0.725 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.314 ; +; -0.725 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; clk ; clk ; 2.500 ; -0.042 ; 3.314 ; +; -0.724 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.335 ; +; -0.724 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.334 ; +; -0.724 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.307 ; +; -0.724 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.309 ; +; -0.724 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.328 ; +; -0.724 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.310 ; +; -0.724 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.325 ; +; -0.724 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.310 ; +; -0.724 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.312 ; +; -0.724 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.280 ; +; -0.724 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.056 ; 3.299 ; +; -0.724 ; vx_f_d_reg|instruction[12] ; vx_f_d_reg|curr_PC[1] ; clk ; clk ; 2.500 ; -0.028 ; 3.194 ; +; -0.724 ; vx_f_d_reg|instruction[12] ; vx_f_d_reg|curr_PC[0] ; clk ; clk ; 2.500 ; -0.028 ; 3.194 ; +; -0.724 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.332 ; +; -0.724 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.313 ; +; -0.724 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.324 ; +; -0.724 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.340 ; +; -0.724 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.315 ; +; -0.723 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.335 ; +; -0.723 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.333 ; +; -0.723 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.297 ; +; -0.723 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.318 ; +; -0.723 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.321 ; +; -0.723 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.331 ; +; -0.723 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.274 ; +; -0.723 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.325 ; +; -0.723 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.299 ; +; -0.723 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.312 ; +; -0.723 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.074 ; 3.318 ; +; -0.723 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; clk ; clk ; 2.500 ; -0.050 ; 3.308 ; +; -0.723 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[2] ; clk ; clk ; 2.500 ; -0.077 ; 3.169 ; +; -0.723 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.324 ; +; -0.723 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|a_reg_data[5] ; clk ; clk ; 2.500 ; -0.077 ; 3.169 ; +; -0.723 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.315 ; +; -0.722 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.323 ; +; -0.722 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.320 ; +; -0.722 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.323 ; +; -0.722 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.308 ; +; -0.722 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.324 ; +; -0.722 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.318 ; +; -0.722 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[11] ; clk ; clk ; 2.500 ; -0.089 ; 3.116 ; +; -0.722 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[1] ; clk ; clk ; 2.500 ; -0.089 ; 3.116 ; +; -0.722 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; clk ; clk ; 2.500 ; -0.089 ; 3.116 ; +; -0.722 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.074 ; 3.317 ; +; -0.722 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.337 ; +; -0.721 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.315 ; +; -0.721 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.271 ; +; -0.721 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.335 ; +; -0.721 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.314 ; +; -0.721 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.301 ; +; -0.721 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.324 ; +; -0.721 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.138 ; +; -0.721 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.322 ; +; -0.721 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.058 ; 3.300 ; +; -0.721 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|rs1[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.287 ; +; -0.720 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.310 ; +; -0.720 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.310 ; +; -0.720 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.271 ; +; -0.720 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.270 ; +; -0.720 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.323 ; +; -0.720 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.314 ; +; -0.720 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.305 ; +; -0.720 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.138 ; +; -0.720 ; vx_f_d_reg|instruction[5] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.192 ; +; -0.720 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.286 ; +; -0.720 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_address[4] ; clk ; clk ; 2.500 ; -0.122 ; 3.234 ; +; -0.719 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.268 ; +; -0.719 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.329 ; +; -0.719 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.334 ; +; -0.719 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.315 ; +; -0.719 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.272 ; +; -0.719 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[10] ; clk ; clk ; 2.500 ; -0.089 ; 3.116 ; +; -0.719 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[3] ; clk ; clk ; 2.500 ; -0.089 ; 3.116 ; +; -0.719 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.320 ; +; -0.719 ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.087 ; 3.268 ; +; -0.719 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[29] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; +; -0.718 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.316 ; +; -0.718 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.310 ; +; -0.718 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.303 ; +; -0.718 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.321 ; +; -0.718 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.306 ; +; -0.718 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[27] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; +; -0.718 ; vx_d_e_reg|a_reg_data[9] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.082 ; 3.272 ; +; -0.717 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.319 ; +; -0.717 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.325 ; +; -0.717 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[26] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; +; -0.716 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.299 ; +; -0.716 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.320 ; +; -0.716 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.273 ; +; -0.716 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.273 ; +; -0.716 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.159 ; +; -0.716 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.159 ; +; -0.716 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.159 ; +; -0.716 ; vx_f_d_reg|instruction[14] ; vx_f_d_reg|curr_PC[7] ; clk ; clk ; 2.500 ; -0.031 ; 3.183 ; +; -0.716 ; vx_f_d_reg|instruction[14] ; vx_f_d_reg|curr_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.183 ; +; -0.716 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.324 ; +; -0.716 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.074 ; 3.311 ; +; -0.716 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.295 ; +; -0.715 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[28] ; clk ; clk ; 2.500 ; -0.075 ; 3.271 ; +; -0.715 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.317 ; +; -0.715 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.300 ; +; -0.715 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[0] ; clk ; clk ; 2.500 ; -0.080 ; 3.159 ; +; -0.715 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.074 ; 3.310 ; +; -0.715 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.321 ; +; -0.715 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.290 ; +; -0.715 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_address[2] ; clk ; clk ; 2.500 ; -0.122 ; 3.229 ; +; -0.715 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.312 ; +; -0.714 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.320 ; +; -0.714 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.315 ; +; -0.714 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.312 ; +; -0.714 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.301 ; +; -0.714 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.266 ; +; -0.714 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.270 ; +; -0.714 ; vx_csr_handler|decode_csr_address[1] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.013 ; 3.338 ; +; -0.714 ; vx_csr_handler|decode_csr_address[0]~DUPLICATE ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.013 ; 3.338 ; +; -0.714 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.303 ; +; -0.714 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; clk ; clk ; 2.500 ; -0.030 ; 3.320 ; +; -0.713 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.303 ; +; -0.713 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.303 ; +; -0.713 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.327 ; +; -0.713 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.312 ; +; -0.713 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[30] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; +; -0.712 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.301 ; +; -0.712 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.300 ; +; -0.712 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.315 ; +; -0.712 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.319 ; +; -0.712 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.269 ; +; -0.712 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.268 ; +; -0.712 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.328 ; +; -0.712 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.268 ; +; -0.712 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[22] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; +; -0.712 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[23] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; +; -0.712 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[24] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; +; -0.712 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[28] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; +; -0.712 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.295 ; +; -0.712 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[31] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; +; -0.712 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.309 ; +; -0.711 ; vx_d_e_reg|rd[3] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.312 ; +; -0.711 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.300 ; +; -0.711 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.308 ; +; -0.711 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.306 ; +; -0.711 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.297 ; +; -0.711 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.266 ; +; -0.711 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.312 ; +; -0.711 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.297 ; +; -0.711 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; clk ; clk ; 2.500 ; -0.043 ; 3.305 ; +; -0.711 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.128 ; +; -0.711 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.321 ; +; -0.711 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.306 ; +; -0.711 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.295 ; +; -0.711 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[25] ; clk ; clk ; 2.500 ; -0.063 ; 3.140 ; +; -0.711 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.314 ; +; -0.711 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.313 ; +; -0.711 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; clk ; clk ; 2.500 ; -0.082 ; 3.249 ; +; -0.711 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; clk ; clk ; 2.500 ; -0.045 ; 3.299 ; +; -0.710 ; vx_f_d_reg|instruction[5] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.311 ; +; -0.710 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[4] ; clk ; clk ; 2.500 ; -0.025 ; 3.169 ; +; -0.710 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.293 ; +; -0.710 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.317 ; +; -0.710 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.308 ; +; -0.710 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.075 ; 3.266 ; +; -0.710 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.308 ; +; -0.710 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.128 ; +; -0.710 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.306 ; +; -0.709 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.304 ; +; -0.709 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[24] ; clk ; clk ; 2.500 ; -0.075 ; 3.266 ; +; -0.709 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.311 ; +; -0.709 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.294 ; +; -0.709 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; clk ; clk ; 2.500 ; -0.057 ; 3.304 ; +; -0.709 ; vx_f_d_reg|instruction[3] ; vx_f_d_reg|curr_PC[7] ; clk ; clk ; 2.500 ; -0.031 ; 3.176 ; +; -0.709 ; vx_f_d_reg|instruction[3] ; vx_f_d_reg|curr_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.176 ; +; -0.709 ; vx_d_e_reg|rd[4] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.181 ; +; -0.709 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; clk ; clk ; 2.500 ; -0.044 ; 3.302 ; +; -0.709 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.302 ; +; -0.709 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.310 ; +; -0.708 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.306 ; +; -0.708 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[19] ; clk ; clk ; 2.500 ; -0.075 ; 3.264 ; +; -0.708 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.311 ; +; -0.708 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.057 ; 3.304 ; +; -0.708 ; vx_f_d_reg|instruction[23] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.020 ; 3.186 ; +; -0.708 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.308 ; +; -0.708 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.321 ; +; -0.708 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.298 ; +; -0.708 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[14] ; clk ; clk ; 2.500 ; -0.078 ; 3.261 ; +; -0.707 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.169 ; +; -0.707 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[31] ; clk ; clk ; 2.500 ; -0.075 ; 3.262 ; +; -0.707 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.323 ; +; -0.707 ; vx_f_d_reg|instruction[1] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.179 ; +; -0.707 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.306 ; +; -0.707 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.303 ; +; -0.706 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.262 ; +; -0.706 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.318 ; +; -0.706 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.317 ; +; -0.706 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[10] ; clk ; clk ; 2.500 ; -0.025 ; 3.169 ; +; -0.706 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.311 ; +; -0.706 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.314 ; +; -0.706 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.312 ; +; -0.706 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_address[0] ; clk ; clk ; 2.500 ; -0.121 ; 3.220 ; +; -0.706 ; vx_csr_handler|decode_csr_address[3] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.333 ; +; -0.706 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.307 ; +; -0.706 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.292 ; +; -0.706 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.306 ; +; -0.706 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.323 ; +; -0.706 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_one|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.093 ; 2.283 ; +; -0.706 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_two|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.093 ; 2.282 ; +; -0.705 ; vx_d_e_reg|rd[3] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.309 ; +; -0.705 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.317 ; +; -0.705 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.261 ; +; -0.705 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.262 ; +; -0.705 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.261 ; +; -0.705 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.290 ; +; -0.705 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.308 ; +; -0.705 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.303 ; +; -0.705 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.295 ; +; -0.705 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[5] ; clk ; clk ; 2.500 ; -0.029 ; 3.162 ; +; -0.705 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[7] ; clk ; clk ; 2.500 ; -0.029 ; 3.162 ; +; -0.705 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[11] ; clk ; clk ; 2.500 ; -0.024 ; 3.168 ; +; -0.705 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; vx_fetch|VX_Warp_one|real_PC[0] ; clk (INVERTED) ; clk ; 1.500 ; -0.110 ; 2.227 ; +; -0.705 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.307 ; +; -0.704 ; vx_f_d_reg|instruction[5] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.308 ; +; -0.704 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[25] ; clk ; clk ; 2.500 ; -0.077 ; 3.259 ; +; -0.704 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.306 ; +; -0.704 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.259 ; +; -0.704 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.306 ; +; -0.704 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; clk ; clk ; 2.500 ; -0.046 ; 3.293 ; +; -0.704 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.162 ; +; -0.703 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.311 ; +; -0.703 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.300 ; +; -0.703 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.306 ; +; -0.703 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; clk ; clk ; 2.500 ; -0.057 ; 3.292 ; +; -0.703 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[6] ; clk ; clk ; 2.500 ; -0.029 ; 3.162 ; +; -0.703 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.305 ; +; -0.703 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.309 ; +; -0.702 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.309 ; +; -0.702 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.285 ; +; -0.702 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.258 ; +; -0.702 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.300 ; +; -0.702 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.319 ; +; -0.702 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.303 ; +; -0.702 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.319 ; +; -0.702 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.298 ; +; -0.702 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.259 ; +; -0.702 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.258 ; +; -0.702 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.308 ; +; -0.702 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_address[5] ; clk ; clk ; 2.500 ; -0.116 ; 3.220 ; +; -0.702 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_one|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.095 ; 2.278 ; +; -0.701 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.304 ; +; -0.701 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.284 ; +; -0.701 ; vx_csr_handler|decode_csr_address[3] ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.325 ; +; -0.701 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.288 ; +; -0.701 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.317 ; +; -0.701 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.304 ; +; -0.701 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.256 ; +; -0.701 ; vx_f_d_reg|instruction[22] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.020 ; 3.179 ; +; -0.701 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.305 ; +; -0.701 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; clk ; clk ; 2.500 ; -0.034 ; 3.300 ; +; -0.701 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.290 ; +; -0.701 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.296 ; +; -0.701 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[26] ; clk ; clk ; 2.500 ; -0.082 ; 3.249 ; +; -0.701 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_two|real_PC[25] ; clk (INVERTED) ; clk ; 1.500 ; -0.107 ; 2.262 ; +; -0.701 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.297 ; +; -0.700 ; vx_d_e_reg|a_reg_data[9] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.082 ; 3.254 ; +; -0.700 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.308 ; +; -0.700 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.284 ; +; -0.700 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.293 ; +; -0.700 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.307 ; +; -0.700 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.298 ; +; -0.700 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.285 ; +; -0.700 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.285 ; +; -0.700 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.303 ; +; -0.700 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.301 ; +; -0.700 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.286 ; +; -0.700 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.306 ; +; -0.700 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.307 ; +; -0.699 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.273 ; +; -0.699 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.297 ; +; -0.699 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.316 ; +; -0.699 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.298 ; +; -0.698 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.308 ; +; -0.698 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.298 ; +; -0.698 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.294 ; +; -0.698 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.311 ; +; -0.698 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.310 ; +; -0.698 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.300 ; +; -0.698 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.303 ; +; -0.698 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.306 ; +; -0.698 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.283 ; +; -0.698 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.299 ; +; -0.698 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.293 ; +; -0.698 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.284 ; +; -0.698 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.300 ; +; -0.698 ; vx_f_d_reg|instruction[14] ; vx_f_d_reg|curr_PC[0] ; clk ; clk ; 2.500 ; -0.028 ; 3.168 ; +; -0.698 ; vx_f_d_reg|instruction[14] ; vx_f_d_reg|curr_PC[1] ; clk ; clk ; 2.500 ; -0.028 ; 3.168 ; +; -0.698 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.298 ; +; -0.698 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.287 ; +; -0.698 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.300 ; +; -0.697 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.254 ; +; -0.697 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.253 ; +; -0.697 ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.087 ; 3.246 ; +; -0.697 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.308 ; +; -0.697 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.247 ; +; -0.697 ; vx_f_d_reg|instruction[1] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.298 ; +; -0.697 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[14] ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; +; -0.697 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[9] ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; +; -0.697 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.298 ; +; -0.697 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.307 ; +; -0.697 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.290 ; +; -0.697 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.277 ; +; -0.697 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.271 ; +; -0.697 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.291 ; +; -0.697 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.300 ; +; -0.697 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.303 ; +; -0.697 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.298 ; +; -0.697 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.303 ; +; -0.697 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; vx_fetch|VX_Warp_two|real_PC[0] ; clk (INVERTED) ; clk ; 1.500 ; -0.110 ; 2.219 ; +; -0.696 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.251 ; +; -0.696 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; +; -0.696 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[8] ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; +; -0.696 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.315 ; +; -0.696 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.032 ; 3.316 ; +; -0.696 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.297 ; +; -0.696 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.283 ; +; -0.696 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.297 ; +; -0.696 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[13] ; clk ; clk ; 2.500 ; -0.024 ; 3.168 ; +; -0.696 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.298 ; +; -0.695 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.302 ; +; -0.695 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; clk ; clk ; 2.500 ; -0.051 ; 3.295 ; +; -0.695 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.293 ; +; -0.695 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[16] ; clk ; clk ; 2.500 ; -0.078 ; 3.248 ; +; -0.695 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.310 ; +; -0.695 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.291 ; +; -0.695 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.288 ; +; -0.695 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.275 ; +; -0.695 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.292 ; +; -0.695 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.296 ; +; -0.695 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[19] ; clk ; clk ; 2.500 ; -0.024 ; 3.168 ; +; -0.694 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[16] ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; +; -0.694 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[17] ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; +; -0.694 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[20] ; clk ; clk ; 2.500 ; -0.021 ; 3.160 ; +; -0.694 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.302 ; +; -0.694 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.286 ; +; -0.694 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.279 ; +; -0.694 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.297 ; +; -0.694 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; clk ; clk ; 2.500 ; -0.089 ; 3.088 ; +; -0.694 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[1] ; clk ; clk ; 2.500 ; -0.089 ; 3.088 ; +; -0.694 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[11] ; clk ; clk ; 2.500 ; -0.089 ; 3.088 ; +; -0.694 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.311 ; +; -0.694 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.295 ; +; -0.694 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.311 ; +; -0.694 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.292 ; +; -0.693 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.282 ; +; -0.693 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; clk ; clk ; 2.500 ; -0.042 ; 3.282 ; +; -0.693 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.296 ; +; -0.693 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.276 ; +; -0.693 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.300 ; +; -0.693 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.308 ; +; -0.693 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.289 ; +; -0.693 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.279 ; +; -0.693 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.294 ; +; -0.693 ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; vx_e_m_reg|alu_result[7] ; clk ; clk ; 2.500 ; -0.083 ; 3.248 ; +; -0.693 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.047 ; 3.278 ; +; -0.693 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; vx_fetch|VX_Warp_three|real_PC[0] ; clk (INVERTED) ; clk ; 1.500 ; -0.110 ; 2.214 ; +; -0.692 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[4] ; clk ; clk ; 2.500 ; -0.025 ; 3.151 ; +; -0.692 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.283 ; +; -0.692 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.308 ; +; -0.692 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; clk ; clk ; 2.500 ; -0.037 ; 3.288 ; +; -0.692 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.276 ; +; -0.692 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.285 ; +; -0.692 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.299 ; +; -0.692 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[17] ; clk ; clk ; 2.500 ; -0.078 ; 3.246 ; +; -0.692 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.275 ; +; -0.692 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.284 ; +; -0.692 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.296 ; +; -0.692 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.075 ; 3.248 ; +; -0.692 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.249 ; +; -0.692 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.248 ; +; -0.692 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.298 ; +; -0.692 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.300 ; +; -0.692 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.277 ; +; -0.692 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.284 ; +; -0.691 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.281 ; +; -0.691 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.281 ; +; -0.691 ; vx_f_d_reg|instruction[1] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.295 ; +; -0.691 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.292 ; +; -0.691 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.283 ; +; -0.691 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; clk ; clk ; 2.500 ; -0.050 ; 3.276 ; +; -0.691 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.293 ; +; -0.691 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[24] ; clk ; clk ; 2.500 ; -0.075 ; 3.248 ; +; -0.691 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.246 ; +; -0.691 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; clk ; clk ; 2.500 ; -0.049 ; 3.293 ; +; -0.691 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[10] ; clk ; clk ; 2.500 ; -0.089 ; 3.088 ; +; -0.691 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[3] ; clk ; clk ; 2.500 ; -0.089 ; 3.088 ; +; -0.691 ; vx_f_d_reg|instruction[3] ; vx_f_d_reg|curr_PC[0] ; clk ; clk ; 2.500 ; -0.028 ; 3.161 ; +; -0.691 ; vx_f_d_reg|instruction[3] ; vx_f_d_reg|curr_PC[1] ; clk ; clk ; 2.500 ; -0.028 ; 3.161 ; +; -0.691 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.308 ; +; -0.691 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[21] ; clk ; clk ; 2.500 ; -0.023 ; 3.152 ; +; -0.691 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[3] ; clk ; clk ; 2.500 ; -0.023 ; 3.152 ; +; -0.691 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.292 ; +; -0.691 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.305 ; +; -0.691 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.297 ; +; -0.691 ; vx_d_e_reg|a_reg_data[0] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.082 ; 3.245 ; +; -0.690 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.305 ; +; -0.690 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.302 ; +; -0.690 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.303 ; +; -0.690 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.292 ; +; -0.690 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.290 ; +; -0.690 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.286 ; +; -0.690 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.291 ; +; -0.690 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.273 ; +; -0.690 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.288 ; +; -0.690 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.294 ; +; -0.690 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.246 ; +; -0.690 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[19] ; clk ; clk ; 2.500 ; -0.075 ; 3.246 ; +; -0.690 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.277 ; +; -0.690 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.039 ; 3.286 ; +; -0.690 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.247 ; +; -0.690 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.247 ; +; -0.690 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.298 ; +; -0.690 ; vx_csr_handler|decode_csr_address[1] ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; 0.005 ; 3.329 ; +; -0.690 ; vx_csr_handler|decode_csr_address[0]~DUPLICATE ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; 0.005 ; 3.329 ; +; -0.690 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.285 ; +; -0.690 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.274 ; +; -0.690 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.030 ; 3.294 ; +; -0.690 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_three|real_PC[25] ; clk (INVERTED) ; clk ; 1.500 ; -0.113 ; 2.246 ; +; -0.690 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[31] ; clk ; clk ; 2.500 ; -0.023 ; 3.165 ; +; -0.690 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[28] ; clk ; clk ; 2.500 ; -0.023 ; 3.165 ; +; -0.690 ; vx_d_e_reg|b_reg_data[1] ; vx_e_m_reg|alu_result[5] ; clk ; clk ; 2.500 ; -0.079 ; 3.247 ; +; -0.690 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.274 ; +; -0.690 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.310 ; +; -0.689 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.283 ; +; -0.689 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.151 ; +; -0.689 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.058 ; 3.268 ; +; -0.689 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.290 ; +; -0.689 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.291 ; +; -0.689 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.270 ; +; -0.689 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.303 ; +; -0.689 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[31] ; clk ; clk ; 2.500 ; -0.075 ; 3.244 ; +; -0.689 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.295 ; +; -0.689 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[15] ; clk ; clk ; 2.500 ; -0.023 ; 3.152 ; +; -0.689 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; clk ; clk ; 2.500 ; -0.030 ; 3.294 ; +; -0.689 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; clk (INVERTED) ; clk ; 1.500 ; -0.113 ; 2.246 ; +; -0.689 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.283 ; +; -0.688 ; vx_f_d_reg|instruction[0] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.239 ; +; -0.688 ; vx_f_d_reg|instruction[0] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.238 ; +; -0.688 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[10] ; clk ; clk ; 2.500 ; -0.025 ; 3.151 ; +; -0.688 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.286 ; +; -0.688 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.032 ; 3.308 ; +; -0.688 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.307 ; +; -0.688 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.291 ; +; -0.688 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.289 ; +; -0.688 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[28] ; clk ; clk ; 2.500 ; -0.075 ; 3.243 ; +; -0.688 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.244 ; +; -0.688 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.131 ; +; -0.688 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.131 ; +; -0.688 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.131 ; +; -0.688 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.312 ; +; -0.687 ; vx_f_d_reg|instruction[0] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.236 ; +; -0.687 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.288 ; +; -0.687 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; clk ; clk ; 2.500 ; -0.051 ; 3.287 ; +; -0.687 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.285 ; +; -0.687 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.301 ; +; -0.687 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.272 ; +; -0.687 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.273 ; +; -0.687 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|a_reg_data[0] ; clk ; clk ; 2.500 ; -0.080 ; 3.131 ; +; -0.687 ; vx_f_d_reg|instruction[13] ; vx_f_d_reg|curr_PC[7] ; clk ; clk ; 2.500 ; -0.031 ; 3.154 ; +; -0.687 ; vx_f_d_reg|instruction[13] ; vx_f_d_reg|curr_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.154 ; +; -0.687 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.284 ; +; -0.687 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[18] ; clk ; clk ; 2.500 ; -0.023 ; 3.152 ; +; -0.687 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; clk ; clk ; 2.500 ; -0.041 ; 3.278 ; +; -0.687 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.278 ; +; -0.687 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[2] ; clk ; clk ; 2.500 ; -0.023 ; 3.152 ; +; -0.687 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.239 ; +; -0.686 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.294 ; +; -0.686 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.284 ; +; -0.686 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.289 ; +; -0.686 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.260 ; +; -0.686 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.288 ; +; -0.686 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.047 ; 3.274 ; +; -0.686 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; clk ; clk ; 2.500 ; -0.076 ; 3.242 ; +; -0.686 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.276 ; +; -0.686 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.281 ; +; -0.686 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.113 ; 3.244 ; +; -0.685 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; clk ; clk ; 2.500 ; -0.042 ; 3.274 ; +; -0.685 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.274 ; +; -0.685 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.286 ; +; -0.685 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.280 ; +; -0.685 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.293 ; +; -0.685 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.102 ; +; -0.685 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; clk ; clk ; 2.500 ; -0.048 ; 3.269 ; +; -0.685 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|warp_num[4] ; clk ; clk ; 2.500 ; -0.080 ; 3.240 ; +; -0.685 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.292 ; +; -0.684 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.263 ; +; -0.684 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.275 ; +; -0.684 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.300 ; +; -0.684 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; clk ; clk ; 2.500 ; -0.037 ; 3.280 ; +; -0.684 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[1] ; clk ; clk ; 2.500 ; -0.082 ; 3.234 ; +; -0.684 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.282 ; +; -0.684 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.277 ; +; -0.684 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.264 ; +; -0.684 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.278 ; +; -0.684 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.102 ; +; -0.684 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.285 ; +; -0.684 ; vx_f_d_reg|instruction[24] ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.126 ; 3.120 ; +; -0.684 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.275 ; +; -0.684 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.286 ; +; -0.684 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.285 ; +; -0.683 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.234 ; +; -0.683 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.233 ; +; -0.683 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.289 ; +; -0.683 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.258 ; +; -0.683 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.284 ; +; -0.683 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.275 ; +; -0.683 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; clk ; clk ; 2.500 ; -0.050 ; 3.268 ; +; -0.683 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.236 ; +; -0.683 ; vx_f_d_reg|instruction[6] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.155 ; +; -0.683 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.280 ; +; -0.683 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.285 ; +; -0.683 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; clk ; clk ; 2.500 ; -0.031 ; 3.289 ; +; -0.682 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.231 ; +; -0.682 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[4] ; clk ; clk ; 2.500 ; -0.025 ; 3.161 ; +; -0.682 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.297 ; +; -0.682 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; clk ; clk ; 2.500 ; -0.040 ; 3.274 ; +; -0.682 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.125 ; 3.189 ; +; -0.682 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.288 ; +; -0.682 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.297 ; +; -0.682 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.278 ; +; -0.682 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.238 ; +; -0.682 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.075 ; 3.238 ; +; -0.682 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.296 ; +; -0.682 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.273 ; +; -0.682 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.233 ; +; -0.682 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_three|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.291 ; +; -0.682 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.284 ; +; -0.682 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.049 ; 3.285 ; +; -0.681 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.270 ; +; -0.681 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.288 ; +; -0.681 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.161 ; +; -0.681 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.058 ; 3.260 ; +; -0.681 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.283 ; +; -0.681 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.262 ; +; -0.681 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.273 ; +; -0.681 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[28] ; clk ; clk ; 2.500 ; -0.075 ; 3.236 ; +; -0.681 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[24] ; clk ; clk ; 2.500 ; -0.075 ; 3.238 ; +; -0.681 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.280 ; +; -0.681 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.113 ; 3.238 ; +; -0.681 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.045 ; 3.273 ; +; -0.681 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.262 ; +; -0.680 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.269 ; +; -0.680 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.290 ; +; -0.680 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.269 ; +; -0.680 ; vx_f_d_reg|instruction[0] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.268 ; +; -0.680 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[10] ; clk ; clk ; 2.500 ; -0.025 ; 3.161 ; +; -0.680 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.263 ; +; -0.680 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; clk ; clk ; 2.500 ; -0.030 ; 3.286 ; +; -0.680 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.286 ; +; -0.680 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_address[0] ; clk ; clk ; 2.500 ; -0.121 ; 3.194 ; +; -0.680 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.275 ; +; -0.680 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.282 ; +; -0.680 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[19] ; clk ; clk ; 2.500 ; -0.075 ; 3.236 ; +; -0.680 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.277 ; +; -0.680 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.019 ; 3.296 ; +; -0.680 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|b_reg_data[15] ; clk ; clk ; 2.500 ; -0.080 ; 3.240 ; +; -0.680 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.073 ; 3.090 ; +; -0.679 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.268 ; +; -0.679 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.282 ; +; -0.679 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.281 ; +; -0.679 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.280 ; +; -0.679 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.279 ; +; -0.679 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.276 ; +; -0.679 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[3] ; clk ; clk ; 2.500 ; -0.066 ; 3.245 ; +; -0.679 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[2] ; clk ; clk ; 2.500 ; -0.066 ; 3.245 ; +; -0.679 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.262 ; +; -0.679 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.283 ; +; -0.679 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[31] ; clk ; clk ; 2.500 ; -0.075 ; 3.234 ; +; -0.679 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.287 ; +; -0.679 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.235 ; +; -0.679 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.282 ; +; -0.679 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.113 ; 3.237 ; +; -0.679 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.073 ; 3.090 ; +; -0.679 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; clk ; clk ; 2.500 ; -0.029 ; 3.287 ; +; -0.679 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.277 ; +; -0.678 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.285 ; +; -0.678 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.261 ; +; -0.678 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.288 ; +; -0.678 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.119 ; 3.230 ; +; -0.678 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.274 ; +; -0.678 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.282 ; +; -0.678 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|rs1[2] ; clk ; clk ; 2.500 ; -0.084 ; 3.226 ; +; -0.678 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.285 ; +; -0.678 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.282 ; +; -0.678 ; vx_csr_handler|decode_csr_address[7] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.031 ; 3.284 ; +; -0.677 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.284 ; +; -0.677 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.275 ; +; -0.677 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; clk ; clk ; 2.500 ; -0.044 ; 3.270 ; +; -0.677 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.270 ; +; -0.677 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.266 ; +; -0.677 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.278 ; +; -0.677 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.274 ; +; -0.677 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.262 ; +; -0.677 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.284 ; +; -0.677 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.053 ; 3.256 ; +; -0.677 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; clk ; clk ; 2.500 ; -0.033 ; 3.278 ; +; -0.677 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; clk ; clk ; 2.500 ; -0.029 ; 3.283 ; +; -0.676 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.266 ; +; -0.676 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.289 ; +; -0.676 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.277 ; +; -0.676 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.255 ; +; -0.676 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.274 ; +; -0.676 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.283 ; +; -0.676 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.259 ; +; -0.676 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.290 ; +; -0.676 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[25] ; clk ; clk ; 2.500 ; -0.077 ; 3.231 ; +; -0.676 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.232 ; +; -0.676 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; clk ; clk ; 2.500 ; -0.089 ; 3.070 ; +; -0.676 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[1] ; clk ; clk ; 2.500 ; -0.089 ; 3.070 ; +; -0.676 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[11] ; clk ; clk ; 2.500 ; -0.089 ; 3.070 ; +; -0.676 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.272 ; +; -0.675 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.263 ; +; -0.675 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_one|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.285 ; +; -0.675 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.283 ; +; -0.675 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.281 ; +; -0.675 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.250 ; +; -0.675 ; vx_d_e_reg|b_reg_data[28] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.087 ; 3.224 ; +; -0.675 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.278 ; +; -0.675 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.272 ; +; -0.675 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.274 ; +; -0.675 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; clk ; clk ; 2.500 ; -0.026 ; 3.295 ; +; -0.675 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; clk ; clk ; 2.500 ; -0.026 ; 3.295 ; +; -0.674 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.230 ; +; -0.674 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.281 ; +; -0.674 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.275 ; +; -0.674 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.274 ; +; -0.674 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.279 ; +; -0.674 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.272 ; +; -0.674 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.282 ; +; -0.674 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.259 ; +; -0.674 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.269 ; +; -0.674 ; vx_csr_handler|decode_csr_address[5]~DUPLICATE ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.001 ; 3.309 ; +; -0.674 ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; vx_e_m_reg|alu_result[7] ; clk ; clk ; 2.500 ; -0.083 ; 3.229 ; +; -0.674 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.274 ; +; -0.674 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.264 ; +; -0.674 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.113 ; 3.231 ; +; -0.674 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.265 ; +; -0.673 ; vx_f_d_reg|instruction[6] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.274 ; +; -0.673 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.275 ; +; -0.673 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.263 ; +; -0.673 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.271 ; +; -0.673 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_address[0] ; clk ; clk ; 2.500 ; -0.121 ; 3.187 ; +; -0.673 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.247 ; +; -0.673 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[3] ; clk ; clk ; 2.500 ; -0.089 ; 3.070 ; +; -0.673 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[10] ; clk ; clk ; 2.500 ; -0.089 ; 3.070 ; +; -0.673 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.272 ; +; -0.673 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.272 ; +; -0.672 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; clk ; clk ; 2.500 ; -0.046 ; 3.261 ; +; -0.672 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.255 ; +; -0.672 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; clk ; clk ; 2.500 ; -0.030 ; 3.278 ; +; -0.672 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; clk ; clk ; 2.500 ; -0.040 ; 3.264 ; +; -0.672 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.277 ; +; -0.672 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.280 ; +; -0.672 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.273 ; +; -0.672 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.269 ; +; -0.672 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.272 ; +; -0.672 ; vx_f_d_reg|instruction[24] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.104 ; 3.200 ; +; -0.672 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.262 ; +; -0.672 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.262 ; +; -0.672 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.069 ; 3.235 ; +; -0.672 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.295 ; +; -0.672 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.069 ; 3.235 ; +; -0.672 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_one|real_PC[25] ; clk (INVERTED) ; clk ; 1.500 ; -0.108 ; 2.233 ; +; -0.672 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.295 ; +; -0.671 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.273 ; +; -0.671 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.273 ; +; -0.671 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.274 ; +; -0.671 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; +; -0.671 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.264 ; +; -0.671 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.251 ; +; -0.671 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.272 ; +; -0.671 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.074 ; 3.267 ; +; -0.671 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.074 ; 3.267 ; +; -0.671 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.255 ; +; -0.671 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.273 ; +; -0.671 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24] ; clk ; clk ; 2.500 ; -0.034 ; 3.274 ; +; -0.671 ; vx_d_e_reg|b_reg_data[1] ; vx_e_m_reg|alu_result[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.190 ; +; -0.671 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.268 ; +; -0.671 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.273 ; +; -0.670 ; vx_csr_handler|decode_csr_address[3] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.297 ; +; -0.670 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.281 ; +; -0.670 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.113 ; +; -0.670 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.113 ; +; -0.670 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.113 ; +; -0.670 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.287 ; +; -0.670 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; +; -0.670 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.287 ; +; -0.670 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.268 ; +; -0.670 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.262 ; +; -0.670 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.069 ; 3.232 ; +; -0.670 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25] ; clk ; clk ; 2.500 ; -0.032 ; 3.290 ; +; -0.669 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.281 ; +; -0.669 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[14] ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; +; -0.669 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[9] ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; +; -0.669 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.258 ; +; -0.669 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.265 ; +; -0.669 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.258 ; +; -0.669 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.264 ; +; -0.669 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.262 ; +; -0.669 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; clk ; clk ; 2.500 ; -0.044 ; 3.262 ; +; -0.669 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.272 ; +; -0.669 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.275 ; +; -0.669 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.252 ; +; -0.669 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.284 ; +; -0.669 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.265 ; +; -0.669 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.254 ; +; -0.669 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[28] ; clk ; clk ; 2.500 ; -0.075 ; 3.225 ; +; -0.669 ; vx_csr_handler|decode_csr_address[5]~DUPLICATE ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.001 ; 3.301 ; +; -0.669 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.225 ; +; -0.669 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.029 ; 3.285 ; +; -0.669 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|a_reg_data[0] ; clk ; clk ; 2.500 ; -0.080 ; 3.113 ; +; -0.669 ; vx_f_d_reg|instruction[13] ; vx_f_d_reg|curr_PC[0] ; clk ; clk ; 2.500 ; -0.028 ; 3.139 ; +; -0.669 ; vx_f_d_reg|instruction[13] ; vx_f_d_reg|curr_PC[1] ; clk ; clk ; 2.500 ; -0.028 ; 3.139 ; +; -0.669 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.283 ; +; -0.669 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.270 ; +; -0.668 ; vx_d_e_reg|b_reg_data[4] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.083 ; 3.221 ; +; -0.668 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; +; -0.668 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[8] ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; +; -0.668 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.282 ; +; -0.668 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.275 ; +; -0.668 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.274 ; +; -0.668 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.264 ; +; -0.668 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.258 ; +; -0.668 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.281 ; +; -0.668 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.269 ; +; -0.668 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.252 ; +; -0.668 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.261 ; +; -0.668 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.275 ; +; -0.668 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.260 ; +; -0.668 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.242 ; +; -0.668 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.269 ; +; -0.668 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.049 ; 3.254 ; +; -0.668 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.274 ; +; -0.668 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.285 ; +; -0.668 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.269 ; +; -0.668 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.285 ; +; -0.668 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.266 ; +; -0.668 ; vx_f_d_reg|instruction[23] ; vx_csr_handler|decode_csr_address[4] ; clk ; clk ; 2.500 ; -0.141 ; 3.174 ; +; -0.668 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13] ; clk ; clk ; 2.500 ; -0.046 ; 3.268 ; +; -0.668 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.292 ; +; -0.668 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[22] ; vx_fetch|VX_Warp_three|real_PC[22] ; clk (INVERTED) ; clk ; 1.500 ; -0.101 ; 2.237 ; +; -0.667 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.268 ; +; -0.667 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.256 ; +; -0.667 ; vx_f_d_reg|instruction[6] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.271 ; +; -0.667 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.273 ; +; -0.667 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.270 ; +; -0.667 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.250 ; +; -0.667 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[16] ; clk ; clk ; 2.500 ; -0.078 ; 3.220 ; +; -0.667 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.268 ; +; -0.667 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.265 ; +; -0.667 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.284 ; +; -0.667 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.275 ; +; -0.667 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.252 ; +; -0.666 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.276 ; +; -0.666 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.273 ; +; -0.666 ; vx_f_d_reg|instruction[1] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.255 ; +; -0.666 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[20] ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; +; -0.666 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[17] ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; +; -0.666 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_zero|real_PC[16] ; clk ; clk ; 2.500 ; -0.021 ; 3.132 ; +; -0.666 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.019 ; 3.282 ; +; -0.666 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.255 ; +; -0.666 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.270 ; +; -0.666 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.283 ; +; -0.666 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.266 ; +; -0.666 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.278 ; +; -0.666 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.279 ; +; -0.666 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.268 ; +; -0.666 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.266 ; +; -0.666 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.262 ; +; -0.666 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.250 ; +; -0.666 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.259 ; +; -0.666 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.273 ; +; -0.666 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.249 ; +; -0.666 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.259 ; +; -0.666 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.246 ; +; -0.666 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.263 ; +; -0.666 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.270 ; +; -0.666 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; clk ; clk ; 2.500 ; -0.032 ; 3.268 ; +; -0.666 ; vx_d_e_reg|rd[3] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.138 ; +; -0.666 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; clk ; clk ; 2.500 ; -0.089 ; 3.060 ; +; -0.666 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[1] ; clk ; clk ; 2.500 ; -0.089 ; 3.060 ; +; -0.666 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[11] ; clk ; clk ; 2.500 ; -0.089 ; 3.060 ; +; -0.666 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.272 ; +; -0.666 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.274 ; +; -0.666 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.267 ; +; -0.666 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.073 ; 3.076 ; +; -0.666 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.280 ; +; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.254 ; +; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.251 ; +; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24] ; clk ; clk ; 2.500 ; -0.034 ; 3.268 ; +; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.272 ; +; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.270 ; +; -0.666 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|warp_num[2] ; clk ; clk ; 2.500 ; -0.080 ; 3.221 ; +; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11] ; clk ; clk ; 2.500 ; -0.033 ; 3.268 ; +; -0.666 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.268 ; +; -0.665 ; vx_csr_handler|decode_csr_address[3] ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.289 ; +; -0.665 ; vx_f_d_reg|instruction[0] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.215 ; +; -0.665 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; +; -0.665 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.267 ; +; -0.665 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.255 ; +; -0.665 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.266 ; +; -0.665 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.272 ; +; -0.665 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.248 ; +; -0.665 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.268 ; +; -0.665 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; +; -0.665 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.282 ; +; -0.665 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.261 ; +; -0.665 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.073 ; 3.076 ; +; -0.665 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.277 ; +; -0.665 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.275 ; +; -0.665 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.266 ; +; -0.665 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; +; -0.665 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13] ; clk ; clk ; 2.500 ; -0.046 ; 3.265 ; +; -0.665 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1] ; clk ; clk ; 2.500 ; -0.029 ; 3.281 ; +; -0.665 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.075 ; 3.222 ; +; -0.665 ; vx_d_e_reg|a_reg_data[0] ; vx_e_m_reg|alu_result[5] ; clk ; clk ; 2.500 ; -0.082 ; 3.220 ; +; -0.665 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19] ; clk ; clk ; 2.500 ; -0.034 ; 3.266 ; +; -0.665 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8] ; clk ; clk ; 2.500 ; -0.053 ; 3.246 ; +; -0.664 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.220 ; +; -0.664 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.221 ; +; -0.664 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.278 ; +; -0.664 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; clk ; clk ; 2.500 ; -0.046 ; 3.253 ; +; -0.664 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.032 ; 3.284 ; +; -0.664 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.283 ; +; -0.664 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.276 ; +; -0.664 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.277 ; +; -0.664 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.266 ; +; -0.664 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.264 ; +; -0.664 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.260 ; +; -0.664 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[17] ; clk ; clk ; 2.500 ; -0.078 ; 3.218 ; +; -0.664 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.265 ; +; -0.664 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.262 ; +; -0.664 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.279 ; +; -0.664 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.260 ; +; -0.664 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.282 ; +; -0.664 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.019 ; 3.280 ; +; -0.664 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.074 ; 3.260 ; +; -0.664 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.074 ; 3.260 ; +; -0.664 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.258 ; +; -0.664 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.252 ; +; -0.664 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[11] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.664 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.265 ; +; -0.664 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[7] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.664 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|rs1[3] ; clk ; clk ; 2.500 ; -0.066 ; 3.229 ; +; -0.664 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[5] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.664 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.069 ; 3.227 ; +; -0.664 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.075 ; 3.220 ; +; -0.664 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.262 ; +; -0.663 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.218 ; +; -0.663 ; vx_csr_handler|decode_csr_address[6] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.031 ; 3.268 ; +; -0.663 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.266 ; +; -0.663 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.265 ; +; -0.663 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_address[4] ; clk ; clk ; 2.500 ; -0.122 ; 3.177 ; +; -0.663 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; clk ; clk ; 2.500 ; -0.051 ; 3.263 ; +; -0.663 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.264 ; +; -0.663 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.261 ; +; -0.663 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.261 ; +; -0.663 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.277 ; +; -0.663 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.255 ; +; -0.663 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.248 ; +; -0.663 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[3] ; clk ; clk ; 2.500 ; -0.089 ; 3.060 ; +; -0.663 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[10] ; clk ; clk ; 2.500 ; -0.089 ; 3.060 ; +; -0.663 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.260 ; +; -0.663 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.269 ; +; -0.663 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[23] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; +; -0.663 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25] ; clk ; clk ; 2.500 ; -0.029 ; 3.270 ; +; -0.663 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.279 ; +; -0.663 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.264 ; +; -0.663 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10] ; clk ; clk ; 2.500 ; -0.011 ; 3.285 ; +; -0.663 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.069 ; 3.225 ; +; -0.663 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; +; -0.663 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.265 ; +; -0.662 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.257 ; +; -0.662 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.272 ; +; -0.662 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.019 ; 3.278 ; +; -0.662 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; clk ; clk ; 2.500 ; -0.045 ; 3.250 ; +; -0.662 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.270 ; +; -0.662 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.032 ; 3.282 ; +; -0.662 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.281 ; +; -0.662 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.265 ; +; -0.662 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.236 ; +; -0.662 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.247 ; +; -0.662 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.265 ; +; -0.662 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[5] ; clk ; clk ; 2.500 ; -0.077 ; 3.108 ; +; -0.662 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|a_reg_data[2] ; clk ; clk ; 2.500 ; -0.077 ; 3.108 ; +; -0.662 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.261 ; +; -0.662 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.073 ; 3.072 ; +; -0.662 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.263 ; +; -0.662 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[28] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; +; -0.662 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20] ; clk ; clk ; 2.500 ; -0.033 ; 3.266 ; +; -0.662 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25] ; clk ; clk ; 2.500 ; -0.029 ; 3.270 ; +; -0.662 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[8] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.662 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.227 ; +; -0.662 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[4] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.662 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[2] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.661 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.047 ; 3.246 ; +; -0.661 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.257 ; +; -0.661 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.256 ; +; -0.661 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.250 ; +; -0.661 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; clk ; clk ; 2.500 ; -0.042 ; 3.250 ; +; -0.661 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.250 ; +; -0.661 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; clk ; clk ; 2.500 ; -0.051 ; 3.261 ; +; -0.661 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.259 ; +; -0.661 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.266 ; +; -0.661 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.269 ; +; -0.661 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.244 ; +; -0.661 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.262 ; +; -0.661 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.265 ; +; -0.661 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.258 ; +; -0.661 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.261 ; +; -0.661 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.269 ; +; -0.661 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.073 ; 3.072 ; +; -0.661 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22] ; clk ; clk ; 2.500 ; -0.038 ; 3.268 ; +; -0.661 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[22] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; +; -0.661 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.245 ; +; -0.661 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31] ; clk ; clk ; 2.500 ; -0.034 ; 3.261 ; +; -0.661 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0] ; clk ; clk ; 2.500 ; -0.043 ; 3.253 ; +; -0.660 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.210 ; +; -0.660 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.210 ; +; -0.660 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.211 ; +; -0.660 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.261 ; +; -0.660 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.267 ; +; -0.660 ; vx_d_e_reg|b_reg_data[4] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.083 ; 3.213 ; +; -0.660 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_mask[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.250 ; +; -0.660 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|csr_mask[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.250 ; +; -0.660 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.245 ; +; -0.660 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.262 ; +; -0.660 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.267 ; +; -0.660 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.266 ; +; -0.660 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.256 ; +; -0.660 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.244 ; +; -0.660 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|rs1[1] ; clk ; clk ; 2.500 ; -0.066 ; 3.226 ; +; -0.660 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.251 ; +; -0.660 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.276 ; +; -0.660 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.268 ; +; -0.660 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; clk ; clk ; 2.500 ; -0.037 ; 3.256 ; +; -0.660 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; clk ; clk ; 2.500 ; -0.044 ; 3.253 ; +; -0.660 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.240 ; +; -0.660 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|b_reg_data[25] ; clk ; clk ; 2.500 ; -0.077 ; 3.215 ; +; -0.660 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.258 ; +; -0.660 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[8] ; clk ; clk ; 2.500 ; -0.080 ; 3.103 ; +; -0.660 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.103 ; +; -0.660 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[6] ; clk ; clk ; 2.500 ; -0.080 ; 3.103 ; +; -0.660 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.261 ; +; -0.660 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22] ; clk ; clk ; 2.500 ; -0.038 ; 3.255 ; +; -0.660 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.256 ; +; -0.660 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[18] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.660 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[14] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.660 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[12] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.660 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.275 ; +; -0.660 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; clk (INVERTED) ; clk ; 1.500 ; -0.111 ; 2.219 ; +; -0.660 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.075 ; 3.216 ; +; -0.660 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25] ; vx_fetch|VX_Warp_three|real_PC[25] ; clk (INVERTED) ; clk ; 1.500 ; -0.111 ; 2.219 ; +; -0.660 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.266 ; +; -0.659 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.208 ; +; -0.659 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.254 ; +; -0.659 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.269 ; +; -0.659 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.263 ; +; -0.659 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.260 ; +; -0.659 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.273 ; +; -0.659 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.265 ; +; -0.659 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_mask[0] ; clk ; clk ; 2.500 ; -0.066 ; 3.225 ; +; -0.659 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.251 ; +; -0.659 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.260 ; +; -0.659 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; clk ; clk ; 2.500 ; -0.050 ; 3.244 ; +; -0.659 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; clk ; clk ; 2.500 ; -0.042 ; 3.248 ; +; -0.659 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.248 ; +; -0.659 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.260 ; +; -0.659 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.257 ; +; -0.659 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|a_reg_data[0] ; clk ; clk ; 2.500 ; -0.080 ; 3.103 ; +; -0.659 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.265 ; +; -0.659 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25] ; clk ; clk ; 2.500 ; -0.029 ; 3.275 ; +; -0.659 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.069 ; 3.221 ; +; -0.659 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.050 ; 3.245 ; +; -0.659 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.275 ; +; -0.659 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.276 ; +; -0.658 ; vx_d_e_reg|b_reg_data[28] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.087 ; 3.207 ; +; -0.658 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.214 ; +; -0.658 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.215 ; +; -0.658 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.242 ; +; -0.658 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.278 ; +; -0.658 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.253 ; +; -0.658 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.242 ; +; -0.658 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.030 ; 3.262 ; +; -0.658 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.247 ; +; -0.658 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.262 ; +; -0.658 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.275 ; +; -0.658 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|csr_address[2] ; clk ; clk ; 2.500 ; -0.122 ; 3.172 ; +; -0.658 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.273 ; +; -0.658 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.249 ; +; -0.658 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.274 ; +; -0.658 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; clk ; clk ; 2.500 ; -0.037 ; 3.254 ; +; -0.658 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.272 ; +; -0.658 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.273 ; +; -0.658 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.254 ; +; -0.658 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[25] ; clk ; clk ; 2.500 ; -0.077 ; 3.213 ; +; -0.658 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; clk ; clk ; 2.500 ; -0.049 ; 3.245 ; +; -0.658 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[29] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; +; -0.658 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.069 ; 3.221 ; +; -0.658 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.069 ; 3.221 ; +; -0.658 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[30] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; +; -0.658 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17] ; clk ; clk ; 2.500 ; -0.052 ; 3.243 ; +; -0.658 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[10] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.658 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22] ; clk ; clk ; 2.500 ; -0.034 ; 3.261 ; +; -0.658 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.069 ; 3.220 ; +; -0.658 ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; vx_e_m_reg|alu_result[5] ; clk ; clk ; 2.500 ; -0.087 ; 3.207 ; +; -0.658 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26] ; clk ; clk ; 2.500 ; -0.036 ; 3.258 ; +; -0.657 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.212 ; +; -0.657 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.265 ; +; -0.657 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; clk ; clk ; 2.500 ; -0.030 ; 3.262 ; +; -0.657 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.251 ; +; -0.657 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.263 ; +; -0.657 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; clk ; clk ; 2.500 ; -0.034 ; 3.256 ; +; -0.657 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.058 ; 3.236 ; +; -0.657 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.249 ; +; -0.657 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.258 ; +; -0.657 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; clk ; clk ; 2.500 ; -0.050 ; 3.242 ; +; -0.657 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.259 ; +; -0.657 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.238 ; +; -0.657 ; vx_d_e_reg|b_reg_data[16] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.083 ; 3.210 ; +; -0.657 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.260 ; +; -0.657 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.249 ; +; -0.657 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[27] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; +; -0.657 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.274 ; +; -0.657 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.258 ; +; -0.657 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.274 ; +; -0.657 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.255 ; +; -0.657 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_one|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.275 ; +; -0.657 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[26] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; +; -0.657 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[31] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; +; -0.657 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19] ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; +; -0.657 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[9] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.657 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[6] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.657 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[3] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.657 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; +; -0.657 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.073 ; 3.067 ; +; -0.657 ; vx_d_e_reg|a_reg_data[9] ; vx_e_m_reg|alu_result[5] ; clk ; clk ; 2.500 ; -0.082 ; 3.211 ; +; -0.657 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.250 ; +; -0.656 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.250 ; +; -0.656 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.206 ; +; -0.656 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.207 ; +; -0.656 ; vx_f_d_reg|instruction[24] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.060 ; 3.228 ; +; -0.656 ; vx_f_d_reg|instruction[24] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.060 ; 3.227 ; +; -0.656 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_zero|real_PC[4] ; clk ; clk ; 2.500 ; -0.025 ; 3.115 ; +; -0.656 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.280 ; +; -0.656 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.257 ; +; -0.656 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.271 ; +; -0.656 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.259 ; +; -0.656 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.125 ; 3.163 ; +; -0.656 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|b_reg_data[1] ; clk ; clk ; 2.500 ; -0.082 ; 3.206 ; +; -0.656 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.262 ; +; -0.656 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.239 ; +; -0.656 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.075 ; 3.212 ; +; -0.656 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[26] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; +; -0.656 ; vx_f_d_reg|instruction[4] ; vx_f_d_reg|curr_PC[7] ; clk ; clk ; 2.500 ; -0.031 ; 3.123 ; +; -0.656 ; vx_f_d_reg|instruction[4] ; vx_f_d_reg|curr_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.123 ; +; -0.656 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.069 ; 3.218 ; +; -0.656 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.270 ; +; -0.656 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.267 ; +; -0.656 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[25] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; +; -0.656 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[27] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; +; -0.656 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[29] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; +; -0.656 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.271 ; +; -0.656 ; vx_f_d_reg|instruction[2] ; vx_fetch|VX_Warp_zero|real_PC[24] ; clk ; clk ; 2.500 ; -0.025 ; 3.124 ; +; -0.656 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[16] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.656 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.270 ; +; -0.656 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24] ; clk ; clk ; 2.500 ; -0.034 ; 3.256 ; +; -0.656 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.079 ; 3.076 ; +; -0.656 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.073 ; 3.067 ; +; -0.656 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.079 ; 3.076 ; +; -0.656 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.244 ; +; -0.656 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8] ; clk ; clk ; 2.500 ; -0.049 ; 3.244 ; +; -0.656 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.052 ; 3.250 ; +; -0.655 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.204 ; +; -0.655 ; vx_f_d_reg|instruction[24] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.060 ; 3.225 ; +; -0.655 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; clk ; clk ; 2.500 ; -0.041 ; 3.246 ; +; -0.655 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.258 ; +; -0.655 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.256 ; +; -0.655 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.058 ; 3.234 ; +; -0.655 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.239 ; +; -0.655 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.248 ; +; -0.655 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.257 ; +; -0.655 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.236 ; +; -0.655 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.262 ; +; -0.655 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.253 ; +; -0.655 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.238 ; +; -0.655 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; clk ; clk ; 2.500 ; -0.042 ; 3.259 ; +; -0.655 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.241 ; +; -0.655 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[24] ; clk ; clk ; 2.500 ; -0.075 ; 3.212 ; +; -0.655 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.246 ; +; -0.655 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.261 ; +; -0.655 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.263 ; +; -0.655 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.272 ; +; -0.655 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[17] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.655 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2] ; clk ; clk ; 2.500 ; -0.034 ; 3.258 ; +; -0.655 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18] ; clk ; clk ; 2.500 ; -0.026 ; 3.275 ; +; -0.655 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE ; clk ; clk ; 2.500 ; -0.030 ; 3.257 ; +; -0.654 ; vx_d_e_reg|rd[1] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.255 ; +; -0.654 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; +; -0.654 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[14] ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; +; -0.654 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[9] ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; +; -0.654 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; clk ; clk ; 2.500 ; -0.076 ; 3.210 ; +; -0.654 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.244 ; +; -0.654 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; clk ; clk ; 2.500 ; -0.045 ; 3.242 ; +; -0.654 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[19] ; clk ; clk ; 2.500 ; -0.075 ; 3.210 ; +; -0.654 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.069 ; 3.217 ; +; -0.654 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.069 ; 3.217 ; +; -0.654 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; clk ; clk ; 2.500 ; -0.019 ; 3.270 ; +; -0.654 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.271 ; +; -0.654 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|PC_next_out[0] ; clk ; clk ; 2.500 ; -0.073 ; 3.064 ; +; -0.654 ; vx_csr_handler|decode_csr_address[7] ; vx_e_m_reg|alu_result[4] ; clk ; clk ; 2.500 ; -0.013 ; 3.275 ; +; -0.654 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[21] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.654 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5] ; clk ; clk ; 2.500 ; -0.038 ; 3.268 ; +; -0.654 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[20] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.654 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[19] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.654 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[15] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.654 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|PC_next_out[13] ; clk ; clk ; 2.500 ; -0.082 ; 3.106 ; +; -0.654 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_one|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.091 ; 2.234 ; +; -0.654 ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_three|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.095 ; 2.229 ; +; -0.654 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[14] ; vx_fetch|VX_Warp_one|real_PC[14] ; clk (INVERTED) ; clk ; 1.500 ; -0.095 ; 2.235 ; +; -0.653 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.209 ; +; -0.653 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.210 ; +; -0.653 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[20] ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; +; -0.653 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[17] ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; +; -0.653 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[16] ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; +; -0.653 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_zero|real_PC[8] ; clk ; clk ; 2.500 ; -0.021 ; 3.138 ; +; -0.653 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_zero|real_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.115 ; +; -0.653 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.260 ; +; -0.653 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; clk ; clk ; 2.500 ; -0.048 ; 3.237 ; +; -0.653 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; clk ; clk ; 2.500 ; -0.047 ; 3.238 ; +; -0.653 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.254 ; +; -0.653 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.265 ; +; -0.653 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.266 ; +; -0.653 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.255 ; +; -0.653 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.249 ; +; -0.653 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.253 ; +; -0.653 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.034 ; 3.254 ; +; -0.653 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.251 ; +; -0.653 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.250 ; +; -0.653 ; vx_f_d_reg|instruction[4] ; vx_d_e_reg|b_reg_data[31] ; clk ; clk ; 2.500 ; -0.075 ; 3.208 ; +; -0.653 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|PC_next_out[1] ; clk ; clk ; 2.500 ; -0.073 ; 3.064 ; +; -0.653 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.250 ; +; -0.653 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.257 ; +; -0.653 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|warp_num[1]~DUPLICATE ; clk ; clk ; 2.500 ; -0.080 ; 3.208 ; +; -0.652 ; vx_f_d_reg|instruction[18] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.259 ; +; -0.652 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.207 ; +; -0.652 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.241 ; +; -0.652 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.256 ; +; -0.652 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.074 ; 3.247 ; +; -0.652 ; vx_f_d_reg|instruction[4] ; vx_fetch|VX_Warp_zero|real_PC[10] ; clk ; clk ; 2.500 ; -0.025 ; 3.115 ; +; -0.652 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.253 ; +; -0.652 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.237 ; +; -0.652 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.254 ; +; -0.652 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.231 ; +; -0.652 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.074 ; 3.247 ; +; -0.652 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.253 ; +; -0.652 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.259 ; +; -0.652 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.235 ; +; -0.652 ; vx_d_e_reg|b_reg_data[14] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.083 ; 3.205 ; +; -0.652 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.266 ; +; -0.652 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[30] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; +; -0.652 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.069 ; 3.214 ; +; -0.652 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.243 ; +; -0.652 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.254 ; +; -0.652 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.258 ; +; -0.652 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.248 ; +; -0.652 ; vx_f_d_reg|instruction[22] ; vx_fetch|VX_Warp_two|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.269 ; +; -0.652 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.249 ; +; -0.652 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.244 ; +; -0.652 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10] ; clk ; clk ; 2.500 ; -0.028 ; 3.269 ; +; -0.652 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.258 ; +; -0.652 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|warp_num[1] ; clk ; clk ; 2.500 ; -0.080 ; 3.208 ; +; -0.652 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.249 ; +; -0.652 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.262 ; +; -0.651 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.201 ; +; -0.651 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.202 ; +; -0.651 ; vx_f_d_reg|instruction[23] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.261 ; +; -0.651 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.074 ; 3.246 ; +; -0.651 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[14] ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; +; -0.651 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[9] ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; +; -0.651 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; clk ; clk ; 2.500 ; -0.031 ; 3.257 ; +; -0.651 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.252 ; +; -0.651 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.257 ; +; -0.651 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.265 ; +; -0.651 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.235 ; +; -0.651 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.226 ; +; -0.651 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.257 ; +; -0.651 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.074 ; 3.246 ; +; -0.651 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; clk ; clk ; 2.500 ; -0.032 ; 3.271 ; +; -0.651 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.270 ; +; -0.651 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[2] ; clk ; clk ; 2.500 ; -0.066 ; 3.217 ; +; -0.651 ; vx_f_d_reg|instruction[14] ; vx_d_e_reg|csr_mask[3] ; clk ; clk ; 2.500 ; -0.066 ; 3.217 ; +; -0.651 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.257 ; +; -0.651 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.034 ; 3.254 ; +; -0.651 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|csr_address[0] ; clk ; clk ; 2.500 ; -0.121 ; 3.165 ; +; -0.651 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[31] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; +; -0.651 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[28] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; +; -0.651 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[23] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; +; -0.651 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[24] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; +; -0.651 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[22] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; +; -0.651 ; vx_f_d_reg|instruction[0] ; vx_f_d_reg|curr_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.123 ; +; -0.651 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.113 ; 3.210 ; +; -0.651 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.253 ; +; -0.651 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.248 ; +; -0.651 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.250 ; +; -0.651 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.237 ; +; -0.651 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11] ; clk ; clk ; 2.500 ; -0.034 ; 3.252 ; +; -0.651 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17] ; clk ; clk ; 2.500 ; -0.049 ; 3.237 ; +; -0.651 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25] ; clk ; clk ; 2.500 ; -0.029 ; 3.256 ; +; -0.651 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|rs1[0] ; clk ; clk ; 2.500 ; -0.081 ; 3.205 ; +; -0.650 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.199 ; +; -0.650 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.207 ; +; -0.650 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.206 ; +; -0.650 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; +; -0.650 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[8] ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; +; -0.650 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.252 ; +; -0.650 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.241 ; +; -0.650 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.234 ; +; -0.650 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.270 ; +; -0.650 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.245 ; +; -0.650 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.030 ; 3.254 ; +; -0.650 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.234 ; +; -0.650 ; vx_d_e_reg|a_reg_data[5] ; vx_e_m_reg|alu_result[7] ; clk ; clk ; 2.500 ; -0.084 ; 3.204 ; +; -0.650 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; clk ; clk ; 2.500 ; -0.082 ; 3.188 ; +; -0.650 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.229 ; +; -0.650 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.074 ; 3.245 ; +; -0.650 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; clk ; clk ; 2.500 ; -0.051 ; 3.250 ; +; -0.650 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.248 ; +; -0.650 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.248 ; +; -0.650 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|PC_next_out[25] ; clk ; clk ; 2.500 ; -0.063 ; 3.079 ; +; -0.650 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.247 ; +; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.270 ; +; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.249 ; +; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.265 ; +; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.257 ; +; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.031 ; 3.255 ; +; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5] ; clk ; clk ; 2.500 ; -0.041 ; 3.243 ; +; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE ; clk ; clk ; 2.500 ; -0.049 ; 3.237 ; +; -0.650 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.256 ; +; -0.649 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.204 ; +; -0.649 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.049 ; 3.251 ; +; -0.649 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; clk ; clk ; 2.500 ; -0.045 ; 3.241 ; +; -0.649 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; clk ; clk ; 2.500 ; -0.030 ; 3.254 ; +; -0.649 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.043 ; 3.243 ; +; -0.649 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; clk ; clk ; 2.500 ; -0.034 ; 3.248 ; +; -0.649 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.255 ; +; -0.649 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; clk ; clk ; 2.500 ; -0.056 ; 3.224 ; +; -0.649 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.257 ; +; -0.649 ; vx_f_d_reg|instruction[3] ; vx_d_e_reg|csr_address[1] ; clk ; clk ; 2.500 ; -0.125 ; 3.156 ; +; -0.649 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; clk ; clk ; 2.500 ; -0.036 ; 3.247 ; +; -0.649 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[16] ; clk ; clk ; 2.500 ; -0.078 ; 3.202 ; +; -0.649 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.246 ; +; -0.649 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.248 ; +; -0.649 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.246 ; +; -0.649 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.248 ; +; -0.649 ; vx_d_e_reg|b_reg_data[1] ; vx_e_m_reg|alu_result[3] ; clk ; clk ; 2.500 ; -0.081 ; 3.168 ; +; -0.649 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26] ; clk ; clk ; 2.500 ; -0.039 ; 3.245 ; +; -0.649 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25] ; clk ; clk ; 2.500 ; -0.030 ; 3.256 ; +; -0.649 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE ; clk ; clk ; 2.500 ; -0.023 ; 3.262 ; +; -0.649 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[21] ; clk ; clk ; 2.500 ; -0.034 ; 3.112 ; +; -0.649 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[3] ; clk ; clk ; 2.500 ; -0.034 ; 3.112 ; +; -0.649 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22] ; clk ; clk ; 2.500 ; -0.032 ; 3.264 ; +; -0.649 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.257 ; +; -0.648 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.205 ; +; -0.648 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.204 ; +; -0.648 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.236 ; +; -0.648 ; vx_f_d_reg|instruction[24] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.060 ; 3.257 ; +; -0.648 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[20] ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; +; -0.648 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[17] ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; +; -0.648 ; vx_f_d_reg|instruction[13] ; vx_fetch|VX_Warp_zero|real_PC[16] ; clk ; clk ; 2.500 ; -0.021 ; 3.114 ; +; -0.648 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; clk ; clk ; 2.500 ; -0.030 ; 3.254 ; +; -0.648 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; clk ; clk ; 2.500 ; -0.037 ; 3.243 ; +; -0.648 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; clk ; clk ; 2.500 ; -0.027 ; 3.272 ; +; -0.648 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.249 ; +; -0.648 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.231 ; +; -0.648 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; clk ; clk ; 2.500 ; -0.042 ; 3.237 ; +; -0.648 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; clk ; clk ; 2.500 ; -0.042 ; 3.237 ; +; -0.648 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; clk ; clk ; 2.500 ; -0.040 ; 3.240 ; +; -0.648 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.253 ; +; -0.648 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.256 ; +; -0.648 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.250 ; +; -0.648 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.245 ; +; -0.648 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.248 ; +; -0.648 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.107 ; 2.175 ; +; -0.648 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21] ; clk ; clk ; 2.500 ; -0.025 ; 3.258 ; +; -0.648 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13] ; clk ; clk ; 2.500 ; -0.061 ; 3.217 ; +; -0.648 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.075 ; 3.203 ; +; -0.648 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[19] ; clk ; clk ; 2.500 ; -0.025 ; 3.119 ; +; -0.648 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[12] ; clk ; clk ; 2.500 ; -0.025 ; 3.119 ; +; -0.648 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[2] ; clk ; clk ; 2.500 ; -0.025 ; 3.119 ; +; -0.648 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.252 ; +; -0.648 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18] ; clk ; clk ; 2.500 ; -0.023 ; 3.259 ; +; -0.647 ; vx_f_d_reg|instruction[18] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.202 ; +; -0.647 ; vx_f_d_reg|instruction[14] ; vx_fetch|VX_Warp_one|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.257 ; +; -0.647 ; vx_f_d_reg|instruction[3] ; vx_fetch|VX_Warp_two|real_PC[10] ; clk ; clk ; 2.500 ; -0.026 ; 3.255 ; +; -0.647 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.254 ; +; -0.647 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; clk ; clk ; 2.500 ; -0.029 ; 3.255 ; +; -0.647 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; clk ; clk ; 2.500 ; -0.038 ; 3.245 ; +; -0.647 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; clk ; clk ; 2.500 ; -0.031 ; 3.250 ; +; -0.647 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; clk ; clk ; 2.500 ; -0.041 ; 3.238 ; +; -0.647 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.239 ; +; -0.647 ; vx_f_d_reg|instruction[12] ; vx_d_e_reg|b_reg_data[14] ; clk ; clk ; 2.500 ; -0.078 ; 3.200 ; +; -0.647 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.249 ; +; -0.647 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.250 ; +; -0.647 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.074 ; 3.243 ; +; -0.647 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; clk ; clk ; 2.500 ; -0.044 ; 3.238 ; +; -0.647 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.263 ; +; -0.647 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.247 ; +; -0.647 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; clk ; clk ; 2.500 ; -0.037 ; 3.243 ; +; -0.647 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.230 ; +; -0.647 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.113 ; 3.206 ; +; -0.647 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.238 ; +; -0.647 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.246 ; +; -0.647 ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; vx_e_m_reg|alu_result[7] ; clk ; clk ; 2.500 ; -0.083 ; 3.202 ; +; -0.647 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.243 ; +; -0.647 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.267 ; +; -0.647 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18] ; clk ; clk ; 2.500 ; -0.025 ; 3.274 ; +; -0.647 ; vx_f_d_reg|instruction[2] ; vx_d_e_reg|csr_mask[22] ; clk ; clk ; 2.500 ; -0.036 ; 3.243 ; +; -0.647 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.069 ; 3.208 ; +; -0.647 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.252 ; +; -0.647 ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19] ; vx_fetch|VX_Warp_one|real_PC[19] ; clk (INVERTED) ; clk ; 1.500 ; -0.091 ; 2.227 ; +; -0.647 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2] ; clk ; clk ; 2.500 ; -0.031 ; 3.262 ; +; -0.646 ; vx_csr_handler|decode_csr_address[7] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.031 ; 3.252 ; +; -0.646 ; vx_d_e_reg|wb[0] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.197 ; +; -0.646 ; vx_d_e_reg|wb[0] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.196 ; +; -0.646 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.253 ; +; -0.646 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.250 ; +; -0.646 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.250 ; +; -0.646 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; clk ; clk ; 2.500 ; -0.076 ; 3.202 ; +; -0.646 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.236 ; +; -0.646 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.229 ; +; -0.646 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; clk ; clk ; 2.500 ; -0.030 ; 3.252 ; +; -0.646 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; clk ; clk ; 2.500 ; -0.044 ; 3.238 ; +; -0.646 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; clk ; clk ; 2.500 ; -0.031 ; 3.247 ; +; -0.646 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; clk ; clk ; 2.500 ; -0.050 ; 3.231 ; +; -0.646 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; clk ; clk ; 2.500 ; -0.040 ; 3.238 ; +; -0.646 ; vx_f_d_reg|instruction[13] ; vx_d_e_reg|b_reg_data[17] ; clk ; clk ; 2.500 ; -0.078 ; 3.200 ; +; -0.646 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.113 ; 3.204 ; +; -0.646 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; clk ; clk ; 2.500 ; -0.038 ; 3.243 ; +; -0.646 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[22] ; clk ; clk ; 2.500 ; -0.069 ; 3.209 ; +; -0.646 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[20] ; clk ; clk ; 2.500 ; -0.069 ; 3.209 ; +; -0.646 ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10] ; vx_fetch|VX_Warp_three|real_PC[10] ; clk (INVERTED) ; clk ; 1.500 ; -0.107 ; 2.174 ; +; -0.646 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17] ; clk ; clk ; 2.500 ; -0.076 ; 3.203 ; +; -0.646 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8] ; clk ; clk ; 2.500 ; -0.043 ; 3.239 ; +; -0.646 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7] ; clk ; clk ; 2.500 ; -0.011 ; 3.270 ; +; -0.646 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5] ; clk ; clk ; 2.500 ; -0.039 ; 3.259 ; +; -0.645 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.240 ; +; -0.645 ; vx_d_e_reg|rd[4] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.081 ; 3.234 ; +; -0.645 ; vx_d_e_reg|rd[4] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.249 ; +; -0.645 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_three|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.255 ; +; -0.645 ; vx_d_e_reg|a_reg_data[3] ; vx_e_m_reg|alu_result[2] ; clk ; clk ; 2.500 ; -0.072 ; 3.209 ; +; -0.645 ; vx_d_e_reg|wb[0] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.194 ; +; -0.645 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; clk ; clk ; 2.500 ; -0.053 ; 3.224 ; +; -0.645 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; clk ; clk ; 2.500 ; -0.029 ; 3.251 ; +; -0.645 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.252 ; +; -0.645 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.252 ; +; -0.645 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; clk ; clk ; 2.500 ; -0.048 ; 3.229 ; +; -0.645 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.238 ; +; -0.645 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; clk ; clk ; 2.500 ; -0.044 ; 3.238 ; +; -0.645 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.247 ; +; -0.645 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; clk ; clk ; 2.500 ; -0.034 ; 3.248 ; +; -0.645 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.234 ; +; -0.645 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; clk ; clk ; 2.500 ; -0.031 ; 3.260 ; +; -0.645 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; clk ; clk ; 2.500 ; -0.032 ; 3.245 ; +; -0.645 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; clk ; clk ; 2.500 ; -0.039 ; 3.243 ; +; -0.645 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.251 ; +; -0.645 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.243 ; +; -0.645 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9] ; clk ; clk ; 2.500 ; -0.052 ; 3.227 ; +; -0.645 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6] ; clk ; clk ; 2.500 ; -0.040 ; 3.257 ; +; -0.645 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[9] ; clk ; clk ; 2.500 ; -0.025 ; 3.116 ; +; -0.645 ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; vx_e_m_reg|alu_result[5] ; clk ; clk ; 2.500 ; -0.083 ; 3.199 ; +; -0.644 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.200 ; +; -0.644 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.201 ; +; -0.644 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.200 ; +; -0.644 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.201 ; +; -0.644 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[11] ; clk ; clk ; 2.500 ; -0.024 ; 3.107 ; +; -0.644 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[7] ; clk ; clk ; 2.500 ; -0.029 ; 3.101 ; +; -0.644 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[5] ; clk ; clk ; 2.500 ; -0.029 ; 3.101 ; +; -0.644 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.245 ; +; -0.644 ; vx_d_e_reg|rd[3] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.196 ; +; -0.644 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.234 ; +; -0.644 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.257 ; +; -0.644 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.245 ; +; -0.644 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; clk ; clk ; 2.500 ; -0.058 ; 3.223 ; +; -0.644 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; clk ; clk ; 2.500 ; -0.030 ; 3.246 ; +; -0.644 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.225 ; +; -0.644 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|b_reg_data[30] ; clk ; clk ; 2.500 ; -0.069 ; 3.206 ; +; -0.644 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; clk ; clk ; 2.500 ; -0.031 ; 3.246 ; +; -0.644 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; clk ; clk ; 2.500 ; -0.047 ; 3.235 ; +; -0.644 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; clk ; clk ; 2.500 ; -0.029 ; 3.261 ; +; -0.644 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.245 ; +; -0.644 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.261 ; +; -0.644 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; clk ; clk ; 2.500 ; -0.038 ; 3.242 ; +; -0.644 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; clk ; clk ; 2.500 ; -0.038 ; 3.243 ; +; -0.644 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|b_reg_data[21] ; clk ; clk ; 2.500 ; -0.069 ; 3.206 ; +; -0.644 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.238 ; +; -0.644 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4] ; clk ; clk ; 2.500 ; -0.038 ; 3.241 ; +; -0.643 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.198 ; +; -0.643 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.075 ; 3.200 ; +; -0.643 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.075 ; 3.199 ; +; -0.643 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.198 ; +; -0.643 ; vx_d_e_reg|rd[1] ; vx_d_e_reg|upper_immed[6] ; clk ; clk ; 2.500 ; -0.081 ; 3.193 ; +; -0.643 ; vx_d_e_reg|rd[1] ; vx_d_e_reg|upper_immed[5] ; clk ; clk ; 2.500 ; -0.081 ; 3.194 ; +; -0.643 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|csr_mask[10] ; clk ; clk ; 2.500 ; -0.080 ; 3.232 ; +; -0.643 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; clk ; clk ; 2.500 ; -0.029 ; 3.101 ; +; -0.643 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; clk ; clk ; 2.500 ; -0.026 ; 3.263 ; +; -0.643 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; clk ; clk ; 2.500 ; -0.033 ; 3.244 ; +; -0.643 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; clk ; clk ; 2.500 ; -0.026 ; 3.263 ; +; -0.643 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; clk ; clk ; 2.500 ; -0.031 ; 3.249 ; +; -0.643 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; clk ; clk ; 2.500 ; -0.031 ; 3.249 ; +; -0.643 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; clk ; clk ; 2.500 ; -0.045 ; 3.236 ; +; -0.643 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; clk ; clk ; 2.500 ; -0.044 ; 3.236 ; +; -0.643 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.232 ; +; -0.643 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; clk ; clk ; 2.500 ; -0.031 ; 3.246 ; +; -0.643 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; clk ; clk ; 2.500 ; -0.048 ; 3.248 ; +; -0.643 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; clk ; clk ; 2.500 ; -0.030 ; 3.251 ; +; -0.643 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; clk ; clk ; 2.500 ; -0.050 ; 3.226 ; +; -0.643 ; vx_f_d_reg|instruction[5] ; vx_d_e_reg|csr_address[7] ; clk ; clk ; 2.500 ; -0.119 ; 3.195 ; +; -0.643 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; clk ; clk ; 2.500 ; -0.031 ; 3.245 ; +; -0.643 ; vx_f_d_reg|instruction[13] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.243 ; +; -0.643 ; vx_csr_handler|decode_csr_address[2] ; vx_e_m_reg|csr_result[4] ; clk ; clk ; 2.500 ; -0.009 ; 3.271 ; +; -0.643 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25] ; clk ; clk ; 2.500 ; -0.030 ; 3.250 ; +; -0.642 ; vx_f_d_reg|instruction[17] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.075 ; 3.197 ; +; -0.642 ; vx_d_e_reg|rd[1] ; vx_d_e_reg|upper_immed[4] ; clk ; clk ; 2.500 ; -0.081 ; 3.191 ; +; -0.642 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.249 ; +; -0.642 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|csr_mask[11] ; clk ; clk ; 2.500 ; -0.075 ; 3.236 ; +; -0.642 ; vx_f_d_reg|instruction[6] ; vx_d_e_reg|csr_mask[9] ; clk ; clk ; 2.500 ; -0.080 ; 3.231 ; +; -0.642 ; vx_f_d_reg|instruction[12] ; vx_fetch|VX_Warp_zero|real_PC[6] ; clk ; clk ; 2.500 ; -0.029 ; 3.101 ; +; -0.642 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.233 ; +; -0.642 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; clk ; clk ; 2.500 ; -0.041 ; 3.232 ; +; -0.642 ; vx_f_d_reg|instruction[4] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; clk ; clk ; 2.500 ; -0.054 ; 3.223 ; +; -0.642 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.244 ; +; -0.642 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; clk ; clk ; 2.500 ; -0.045 ; 3.233 ; +; -0.642 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_three|real_PC[9] ; clk ; clk ; 2.500 ; -0.019 ; 3.256 ; +; -0.642 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.044 ; 3.232 ; +; -0.642 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; clk ; clk ; 2.500 ; -0.022 ; 3.255 ; +; -0.642 ; vx_f_d_reg|instruction[5] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; clk ; clk ; 2.500 ; -0.032 ; 3.242 ; +; -0.642 ; vx_f_d_reg|instruction[14] ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.243 ; +; -0.642 ; vx_f_d_reg|instruction[1] ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; clk ; clk ; 2.500 ; -0.032 ; 3.243 ; +; -0.642 ; vx_f_d_reg|instruction[6] ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.239 ; +; -0.642 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; clk ; clk ; 2.500 ; -0.052 ; 3.226 ; +; -0.642 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; clk ; clk ; 2.500 ; -0.044 ; 3.235 ; +; -0.642 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; clk ; clk ; 2.500 ; -0.030 ; 3.249 ; +; -0.642 ; vx_f_d_reg|instruction[0] ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; clk ; clk ; 2.500 ; -0.040 ; 3.237 ; +; -0.642 ; vx_f_d_reg|instruction[22] ; vx_d_e_reg|csr_address[6] ; clk ; clk ; 2.500 ; -0.113 ; 3.200 ; +; -0.642 ; vx_f_d_reg|instruction[3] ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; clk ; clk ; 2.500 ; -0.032 ; 3.248 ; +; -0.642 ; vx_f_d_reg|instruction[2] ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11] ; clk ; clk ; 2.500 ; -0.030 ; 3.258 ; +; -0.642 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[14] ; clk ; clk ; 2.500 ; -0.027 ; 3.112 ; +; -0.642 ; vx_f_d_reg|instruction[2] ; vx_f_d_reg|curr_PC[8] ; clk ; clk ; 2.500 ; -0.027 ; 3.112 ; +; -0.641 ; vx_f_d_reg|instruction[23] ; vx_d_e_reg|upper_immed[3] ; clk ; clk ; 2.500 ; -0.075 ; 3.197 ; +; -0.641 ; vx_f_d_reg|instruction[17] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.025 ; 3.248 ; +; -0.641 ; vx_d_e_reg|rd[3] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.242 ; +; -0.641 ; vx_f_d_reg|instruction[0] ; vx_fetch|VX_Warp_one|real_PC[11] ; clk ; clk ; 2.500 ; -0.031 ; 3.242 ; +; -0.641 ; vx_f_d_reg|instruction[12] ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; clk ; clk ; 2.500 ; -0.049 ; 3.243 ; ++--------+----------------------------------------------------------------------+--------------------------------------------------------------------------------+----------------+-------------+--------------+------------+------------+ + +Path #1: Setup slack is -0.962 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.562 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.962 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.107 ; ; ; ; ; ; +; Data Delay ; 2.489 ; ; ; ; ; ; +; Number of Logic Levels ; ; 2 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 2 ; 2.221 ; 89 ; 1.092 ; 1.129 ; +; Cell ; ; 6 ; 0.135 ; 5 ; 0.000 ; 0.069 ; +; uTco ; ; 1 ; 0.133 ; 5 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]|clk ; +; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; +; 6.562 ; 2.489 ; ; ; ; ; ; data path ; +; 4.206 ; 0.133 ; FF ; uTco ; 1 ; FF_X102_Y155_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]|q ; +; 4.275 ; 0.069 ; FF ; CELL ; 2 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[11] ; +; 5.367 ; 1.092 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|dataf ; +; 5.398 ; 0.031 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; +; 5.404 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; +; 6.533 ; 1.129 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|dataf ; +; 6.562 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; +; 6.562 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; +; 6.562 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; +; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #2: Setup slack is -0.960 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[10] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.561 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.960 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.107 ; ; ; ; ; ; +; Data Delay ; 2.488 ; ; ; ; ; ; +; Number of Logic Levels ; ; 2 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 2 ; 2.220 ; 89 ; 1.092 ; 1.128 ; +; Cell ; ; 6 ; 0.135 ; 5 ; 0.000 ; 0.069 ; +; uTco ; ; 1 ; 0.133 ; 5 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]|clk ; +; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; +; 6.561 ; 2.488 ; ; ; ; ; ; data path ; +; 4.206 ; 0.133 ; FF ; uTco ; 1 ; FF_X102_Y155_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]|q ; +; 4.275 ; 0.069 ; FF ; CELL ; 2 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[11] ; +; 5.367 ; 1.092 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|dataf ; +; 5.398 ; 0.031 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; +; 5.404 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; +; 6.532 ; 1.128 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|dataf ; +; 6.561 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|combout ; +; 6.561 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|d ; +; 6.561 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; +; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y158_N49 ; ; vx_fetch|VX_Warp_three|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #3: Setup slack is -0.946 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[10] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.548 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.946 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.107 ; ; ; ; ; ; +; Data Delay ; 2.475 ; ; ; ; ; ; +; Number of Logic Levels ; ; 2 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 2 ; 2.209 ; 89 ; 1.092 ; 1.117 ; +; Cell ; ; 6 ; 0.133 ; 5 ; 0.000 ; 0.069 ; +; uTco ; ; 1 ; 0.133 ; 5 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]|clk ; +; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10] ; +; 6.548 ; 2.475 ; ; ; ; ; ; data path ; +; 4.206 ; 0.133 ; FF ; uTco ; 1 ; FF_X102_Y155_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]|q ; +; 4.275 ; 0.069 ; FF ; CELL ; 2 ; FF_X102_Y155_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[11] ; +; 5.367 ; 1.092 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|dataf ; +; 5.398 ; 0.031 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; +; 5.404 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; +; 6.521 ; 1.117 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|dataf ; +; 6.548 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|combout ; +; 6.548 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|d ; +; 6.548 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; +; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y158_N25 ; ; vx_fetch|VX_Warp_one|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #4: Setup slack is -0.932 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.480 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.932 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.482 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.963 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.398 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.480 ; 3.482 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.786 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.814 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.818 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.452 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.480 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.480 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.480 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #5: Setup slack is -0.932 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.481 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.932 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.483 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.964 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.398 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.481 ; 3.483 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.786 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.814 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.818 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.453 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.481 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.481 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.481 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #6: Setup slack is -0.931 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.478 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.931 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.480 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.961 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.398 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.478 ; 3.480 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.786 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.814 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.818 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.450 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.478 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.478 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.478 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #7: Setup slack is -0.924 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.510 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.924 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.512 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.959 ; 84 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.432 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.510 ; 3.512 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.704 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.730 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.736 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.448 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.510 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.510 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.510 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #8: Setup slack is -0.913 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.512 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.913 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.514 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.934 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 14 ; 0.459 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.512 ; 3.514 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.123 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 6.151 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 6.157 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.437 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.512 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.512 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.512 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #9: Setup slack is -0.910 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.482 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.910 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.484 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 3.025 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.482 ; 3.484 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.599 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.455 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; +; 6.482 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; +; 6.482 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; +; 6.482 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #10: Setup slack is -0.909 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.457 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.909 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.459 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.941 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.397 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.457 ; 3.459 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.786 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.814 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.818 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.430 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.457 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.457 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.457 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #11: Setup slack is -0.898 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.508 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.898 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.510 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 3.051 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.508 ; 3.510 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.482 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; +; 6.508 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; +; 6.508 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; +; 6.508 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #12: Setup slack is -0.898 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.500 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.898 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.502 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.920 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 14 ; 0.461 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.500 ; 3.502 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.129 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 6.159 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 6.165 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.425 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.500 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.500 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.500 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #13: Setup slack is -0.895 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.365 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.895 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.367 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.907 ; 86 ; 0.119 ; 1.398 ; +; Cell ; ; 10 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.365 ; 3.367 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.365 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.365 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #14: Setup slack is -0.893 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.486 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.893 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.488 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.972 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.395 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.486 ; 3.488 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.404 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; +; 6.486 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; +; 6.486 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; +; 6.486 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #15: Setup slack is -0.887 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.474 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.887 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.476 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 3.016 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.474 ; 3.476 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.546 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.446 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.474 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.474 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; +; 6.474 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #16: Setup slack is -0.887 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.474 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.887 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.476 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 3.016 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.474 ; 3.476 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.546 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.446 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.474 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.474 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; +; 6.474 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #17: Setup slack is -0.886 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.481 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.886 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.483 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.866 ; 82 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.496 ; 14 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.481 ; 3.483 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.389 ; 0.472 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.463 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.467 ; 0.004 ; FF ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.361 ; 0.894 ; FF ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; +; 6.481 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; +; 6.481 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; +; 6.481 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #18: Setup slack is -0.883 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.478 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.883 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.480 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.866 ; 82 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.493 ; 14 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.121 ; 3 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.478 ; 3.480 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.389 ; 0.472 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.463 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.467 ; 0.004 ; FF ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.361 ; 0.894 ; FF ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; +; 6.478 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; +; 6.478 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; +; 6.478 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #19: Setup slack is -0.878 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.450 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.878 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.452 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 3.046 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.284 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.450 ; 3.452 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.535 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.562 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.567 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.423 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; +; 6.450 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; +; 6.450 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; +; 6.450 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #20: Setup slack is -0.875 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.423 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.875 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.425 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.909 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.423 ; 3.425 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.729 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.757 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.761 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.395 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.423 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.423 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.423 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #21: Setup slack is -0.875 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.424 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.875 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.426 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.910 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.424 ; 3.426 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.729 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.757 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.761 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.396 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.424 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.424 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.424 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #22: Setup slack is -0.874 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.421 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.874 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.423 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.907 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.421 ; 3.423 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.729 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.757 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.761 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.393 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.421 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #23: Setup slack is -0.870 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.442 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.870 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.444 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.988 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.442 ; 3.444 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.527 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.554 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.559 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.415 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; +; 6.442 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; +; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; +; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #24: Setup slack is -0.869 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.443 ; +; Data Required Time ; 5.574 ; +; Slack ; -0.869 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.445 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.967 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.357 ; 10 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.443 ; 3.445 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.400 ; 0.483 ; RR ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.428 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.432 ; 0.004 ; FF ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.416 ; 0.984 ; FF ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.443 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.443 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; +; 6.443 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #25: Setup slack is -0.869 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.442 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.869 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.444 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.967 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.356 ; 10 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.442 ; 3.444 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.400 ; 0.483 ; RR ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.428 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.432 ; 0.004 ; FF ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.416 ; 0.984 ; FF ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.442 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; +; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #26: Setup slack is -0.867 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.453 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.867 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.455 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.905 ; 84 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.428 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.453 ; 3.455 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.647 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.673 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.679 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.391 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.453 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.453 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.453 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #27: Setup slack is -0.866 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.476 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.866 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.478 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 3.072 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.284 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.476 ; 3.478 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.450 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; +; 6.476 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; +; 6.476 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; +; 6.476 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #28: Setup slack is -0.866 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.453 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.866 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.455 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.994 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.453 ; 3.455 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.426 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.453 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.453 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; +; 6.453 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #29: Setup slack is -0.865 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.453 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.865 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.455 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.994 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.453 ; 3.455 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.426 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.453 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.453 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; +; 6.453 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #30: Setup slack is -0.861 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.454 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.861 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.456 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.993 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.454 ; 3.456 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.372 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; +; 6.454 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; +; 6.454 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; +; 6.454 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #31: Setup slack is -0.858 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.468 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.858 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.470 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 3.014 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.468 ; 3.470 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.442 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; +; 6.468 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; +; 6.468 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; +; 6.468 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #32: Setup slack is -0.855 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.442 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.855 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.444 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 3.037 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.442 ; 3.444 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.514 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.414 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.442 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; +; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #33: Setup slack is -0.855 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.442 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.855 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.444 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 3.037 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.442 ; 3.444 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.514 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.414 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.442 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; +; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #34: Setup slack is -0.855 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.442 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.855 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.444 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.846 ; 83 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.477 ; 14 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.442 ; 3.444 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.704 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.730 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.736 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.335 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.442 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #35: Setup slack is -0.854 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.455 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.854 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.457 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.918 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.418 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.455 ; 3.457 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.322 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.368 ; 1.014 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; +; 6.455 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; +; 6.455 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; +; 6.455 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #36: Setup slack is -0.854 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.441 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.854 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.443 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.846 ; 83 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.476 ; 14 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.441 ; 3.443 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.704 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.730 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.736 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.335 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.441 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.441 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.441 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #37: Setup slack is -0.853 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.446 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.853 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.448 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.935 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.391 ; 11 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.446 ; 3.448 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.364 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; +; 6.446 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; +; 6.446 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; +; 6.446 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #38: Setup slack is -0.852 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.400 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.852 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.402 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.887 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.400 ; 3.402 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.729 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.757 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.761 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.373 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.400 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.400 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.400 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #39: Setup slack is -0.852 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.451 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.852 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.453 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.871 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.460 ; 13 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.451 ; 3.453 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.062 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 6.090 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 6.096 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.376 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.451 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.451 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.451 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #40: Setup slack is -0.849 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.397 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.849 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.399 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.894 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.384 ; 11 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.397 ; 3.399 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.703 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.731 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.735 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.369 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.397 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.397 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.397 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #41: Setup slack is -0.849 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.398 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.849 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.400 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.895 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.384 ; 11 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.398 ; 3.400 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.703 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.731 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.735 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.370 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.398 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #42: Setup slack is -0.848 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.395 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.848 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.397 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.892 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.384 ; 11 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.395 ; 3.397 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.703 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.731 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.735 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.367 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.395 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.395 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.395 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #43: Setup slack is -0.848 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_address[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.353 ; +; Data Required Time ; 5.505 ; +; Slack ; -0.848 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.361 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 4 ; 2.900 ; 86 ; 0.590 ; 0.986 ; +; Cell ; ; 10 ; 0.336 ; 10 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.353 ; 3.361 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.873 ; 0.688 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|dataa ; +; 3.993 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; +; 3.999 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; +; 4.635 ; 0.636 ; RR ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; +; 4.662 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; +; 4.666 ; 0.004 ; FF ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; +; 5.652 ; 0.986 ; FF ; IC ; 1 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1|dataf ; +; 5.679 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1|combout ; +; 5.684 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1~la_lab/laboutt[3] ; +; 6.274 ; 0.590 ; FF ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datac ; +; 6.353 ; 0.079 ; FF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; +; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; +; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; +; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #44: Setup slack is -0.847 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.434 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.847 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.436 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.979 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.434 ; 3.436 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.506 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.406 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.434 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.434 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; +; 6.434 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #45: Setup slack is -0.847 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.434 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.847 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.436 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.979 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.434 ; 3.436 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.506 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.406 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.434 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.434 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; +; 6.434 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #46: Setup slack is -0.846 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.418 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.846 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.420 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.954 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.418 ; 3.420 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.503 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.530 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.535 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.391 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; +; 6.418 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; +; 6.418 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; +; 6.418 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #47: Setup slack is -0.844 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.439 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.844 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.441 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.885 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.434 ; 13 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.439 ; 3.441 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.376 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.456 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.460 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.314 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; +; 6.439 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; +; 6.439 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; +; 6.439 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #48: Setup slack is -0.844 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.416 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.844 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.418 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.973 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.324 ; 9 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.416 ; 3.418 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.501 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.528 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.533 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.389 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; +; 6.416 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; +; 6.416 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; +; 6.416 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #49: Setup slack is -0.844 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.436 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.844 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.438 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.926 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.391 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.436 ; 3.438 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.357 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; +; 6.436 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; +; 6.436 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; +; 6.436 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #50: Setup slack is -0.843 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.413 ; +; Slack ; -0.843 (VIOLATED) ; ++--------------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.141 ; ; ; ; ; ; +; Data Delay ; 3.264 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 4 ; 2.872 ; 88 ; 0.666 ; 0.817 ; +; Cell ; ; 8 ; 0.267 ; 8 ; 0.000 ; 0.112 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.158 ; 79 ; 0.000 ; 2.158 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.256 ; 3.264 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.868 ; 0.666 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|dataa ; +; 3.980 ; 0.112 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; +; 3.986 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; +; 4.663 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; +; 4.690 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; +; 4.694 ; 0.004 ; RR ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; +; 5.406 ; 0.712 ; RR ; IC ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|dataf ; +; 5.434 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|combout ; +; 5.439 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4~la_lab/laboutb[19] ; +; 6.256 ; 0.817 ; FF ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|d ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.351 ; 2.851 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.223 ; 2.158 ; RR ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|clk ; +; 5.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; +; 5.351 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.321 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.413 ; 0.092 ; ; uTsu ; 1 ; FF_X38_Y157_N16 ; ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #51: Setup slack is -0.843 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.449 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.843 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.451 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.872 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 14 ; 0.458 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.449 ; 3.451 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.169 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.196 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.373 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.449 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.449 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; +; 6.449 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #52: Setup slack is -0.842 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.391 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.842 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.393 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.924 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.349 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.391 ; 3.393 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.696 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.724 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.728 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.363 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.391 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #53: Setup slack is -0.842 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.390 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.842 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.392 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.923 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.349 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.390 ; 3.392 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.696 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.724 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.728 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.362 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.390 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.390 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.390 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #54: Setup slack is -0.842 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.437 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.842 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.439 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.885 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.432 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.437 ; 3.439 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.376 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.456 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.460 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.314 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; +; 6.437 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; +; 6.437 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; +; 6.437 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #55: Setup slack is -0.842 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.435 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.842 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.437 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.977 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.435 ; 3.437 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.409 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.435 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.435 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; +; 6.435 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #56: Setup slack is -0.841 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.388 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.841 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.390 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.921 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.349 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.388 ; 3.390 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.696 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.724 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.728 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.360 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.388 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.388 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.388 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #57: Setup slack is -0.841 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.427 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.841 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.429 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.890 ; 84 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.418 ; 12 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.427 ; 3.429 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.621 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.647 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.653 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.365 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.427 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.427 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.427 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #58: Setup slack is -0.841 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.449 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.841 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.451 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.872 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 14 ; 0.458 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.449 ; 3.451 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.169 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.196 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.373 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.449 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.449 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; +; 6.449 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #59: Setup slack is -0.841 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.435 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.841 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.437 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.977 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.435 ; 3.437 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.409 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.435 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.435 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; +; 6.435 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #60: Setup slack is -0.838 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.308 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.838 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.310 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.853 ; 86 ; 0.119 ; 1.398 ; +; Cell ; ; 10 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.308 ; 3.310 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.877 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.905 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.910 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.308 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #61: Setup slack is -0.837 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.439 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.837 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.441 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.857 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.462 ; 13 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.439 ; 3.441 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.068 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 6.098 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 6.104 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.364 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.439 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.439 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.439 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #62: Setup slack is -0.837 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.437 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.837 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.104 ; ; ; ; ; ; +; Data Delay ; 2.367 ; ; ; ; ; ; +; Number of Logic Levels ; ; 2 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.327 ; 76 ; 0.000 ; 2.327 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 2 ; 2.094 ; 88 ; 0.965 ; 1.129 ; +; Cell ; ; 6 ; 0.141 ; 6 ; 0.000 ; 0.062 ; +; uTco ; ; 1 ; 0.132 ; 6 ; 0.132 ; 0.132 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.070 ; 3.070 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.070 ; 2.327 ; FF ; IC ; 1 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]|clk ; +; 4.070 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; +; 6.437 ; 2.367 ; ; ; ; ; ; data path ; +; 4.202 ; 0.132 ; FF ; uTco ; 1 ; FF_X108_Y155_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]|q ; +; 4.246 ; 0.044 ; FF ; CELL ; 2 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[13] ; +; 5.211 ; 0.965 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|datae ; +; 5.273 ; 0.062 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; +; 5.279 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; +; 6.408 ; 1.129 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|dataf ; +; 6.437 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; +; 6.437 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; +; 6.437 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; +; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #63: Setup slack is -0.836 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.431 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.836 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.433 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.827 ; 82 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.484 ; 14 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.431 ; 3.433 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.368 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.448 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.452 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.306 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; +; 6.431 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; +; 6.431 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; +; 6.431 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #64: Setup slack is -0.836 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.423 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.836 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.425 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.965 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.423 ; 3.425 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.397 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; +; 6.423 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; +; 6.423 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; +; 6.423 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #65: Setup slack is -0.835 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[10] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.436 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.835 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.104 ; ; ; ; ; ; +; Data Delay ; 2.366 ; ; ; ; ; ; +; Number of Logic Levels ; ; 2 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.327 ; 76 ; 0.000 ; 2.327 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 2 ; 2.093 ; 88 ; 0.965 ; 1.128 ; +; Cell ; ; 6 ; 0.141 ; 6 ; 0.000 ; 0.062 ; +; uTco ; ; 1 ; 0.132 ; 6 ; 0.132 ; 0.132 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.070 ; 3.070 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.070 ; 2.327 ; FF ; IC ; 1 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]|clk ; +; 4.070 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; +; 6.436 ; 2.366 ; ; ; ; ; ; data path ; +; 4.202 ; 0.132 ; FF ; uTco ; 1 ; FF_X108_Y155_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]|q ; +; 4.246 ; 0.044 ; FF ; CELL ; 2 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[13] ; +; 5.211 ; 0.965 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|datae ; +; 5.273 ; 0.062 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; +; 5.279 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; +; 6.407 ; 1.128 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|dataf ; +; 6.436 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|combout ; +; 6.436 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|d ; +; 6.436 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; +; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y158_N49 ; ; vx_fetch|VX_Warp_three|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #66: Setup slack is -0.834 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.420 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.834 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.422 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.919 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.383 ; 11 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.420 ; 3.422 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.614 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.640 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.646 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.358 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.420 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.420 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.420 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #67: Setup slack is -0.834 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.421 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.834 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.423 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 3.015 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.421 ; 3.423 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.394 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.421 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; +; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #68: Setup slack is -0.834 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.429 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.834 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.431 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.827 ; 82 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.482 ; 14 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.429 ; 3.431 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.368 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.448 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.452 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.306 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; +; 6.429 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; +; 6.429 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; +; 6.429 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #69: Setup slack is -0.834 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.444 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.834 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.446 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.980 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.444 ; 3.446 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.418 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; +; 6.444 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; +; 6.444 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; +; 6.444 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #70: Setup slack is -0.833 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.421 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.833 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.423 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 3.015 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.421 ; 3.423 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.394 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.421 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; +; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #71: Setup slack is -0.833 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.405 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.833 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.407 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.944 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.405 ; 3.407 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.490 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.517 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.522 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.378 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; +; 6.405 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; +; 6.405 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; +; 6.405 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #72: Setup slack is -0.833 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.388 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.833 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.390 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.890 ; 85 ; 0.108 ; 0.944 ; +; Cell ; ; 12 ; 0.379 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.388 ; 3.390 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.359 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; +; 6.388 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; +; 6.388 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; +; 6.388 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #73: Setup slack is -0.833 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.388 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.833 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.390 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.889 ; 85 ; 0.108 ; 0.943 ; +; Cell ; ; 12 ; 0.380 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.388 ; 3.390 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.358 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; +; 6.388 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; +; 6.388 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; +; 6.388 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #74: Setup slack is -0.832 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.442 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.832 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.444 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.999 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.324 ; 9 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.442 ; 3.444 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.416 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; +; 6.442 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; +; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; +; 6.442 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #75: Setup slack is -0.831 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.385 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.831 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.387 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.886 ; 85 ; 0.108 ; 0.940 ; +; Cell ; ; 12 ; 0.380 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.385 ; 3.387 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.355 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; +; 6.385 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; +; 6.385 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; +; 6.385 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #76: Setup slack is -0.830 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[19] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.469 ; +; Data Required Time ; 5.639 ; +; Slack ; -0.830 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.094 ; ; ; ; ; ; +; Data Delay ; 2.410 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.316 ; 76 ; 0.000 ; 2.316 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.045 ; 85 ; 0.551 ; 0.786 ; +; Cell ; ; 8 ; 0.226 ; 9 ; 0.000 ; 0.069 ; +; uTco ; ; 1 ; 0.139 ; 6 ; 0.139 ; 0.139 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.059 ; 3.059 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.059 ; 2.316 ; FF ; IC ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]|clk ; +; 4.059 ; 0.000 ; FR ; CELL ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; +; 6.469 ; 2.410 ; ; ; ; ; ; data path ; +; 4.198 ; 0.139 ; FF ; uTco ; 1 ; FF_X90_Y146_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]|q ; +; 4.267 ; 0.069 ; FF ; CELL ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]~la_mlab/laboutt[15] ; +; 4.975 ; 0.708 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|datae ; +; 5.037 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; +; 5.042 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; +; 5.828 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; +; 5.854 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; +; 5.859 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; +; 6.410 ; 0.551 ; FF ; IC ; 1 ; MLABCELL_X74_Y160_N30 ; High Speed ; vx_fetch|VX_Warp_two|i199~16|datae ; +; 6.469 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X74_Y160_N30 ; High Speed ; vx_fetch|VX_Warp_two|i199~16|combout ; +; 6.469 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19]|d ; +; 6.469 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19] ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19] ; +; 5.465 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.639 ; 0.204 ; ; uTsu ; 1 ; FF_X74_Y160_N32 ; ; vx_fetch|VX_Warp_two|real_PC[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #77: Setup slack is -0.829 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.422 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.829 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.424 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.901 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.422 ; 3.424 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.340 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; +; 6.422 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; +; 6.422 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; +; 6.422 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #78: Setup slack is -0.828 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.415 ; +; Slack ; -0.828 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.775 ; 86 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.349 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.243 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.415 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #79: Setup slack is -0.827 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.420 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.827 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.422 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.920 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.381 ; 11 ; 0.000 ; 0.082 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.420 ; 3.422 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.338 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; +; 6.420 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; +; 6.420 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; +; 6.420 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #80: Setup slack is -0.827 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.416 ; +; Slack ; -0.827 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.775 ; 86 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.349 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.243 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.416 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #81: Setup slack is -0.826 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.374 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.826 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.376 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.872 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.383 ; 11 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.374 ; 3.376 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.703 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.731 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.735 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.347 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.374 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.374 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.374 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #82: Setup slack is -0.826 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.413 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.826 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.415 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.957 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.413 ; 3.415 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.386 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.413 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; +; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #83: Setup slack is -0.826 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.425 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.826 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.427 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.967 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.425 ; 3.427 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.399 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; +; 6.425 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; +; 6.425 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; +; 6.425 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #84: Setup slack is -0.826 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_address[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.377 ; +; Data Required Time ; 5.551 ; +; Slack ; -0.826 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.379 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.881 ; 85 ; 0.108 ; 0.935 ; +; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.377 ; 3.379 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.349 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; +; 6.377 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; +; 6.377 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; +; 6.377 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #85: Setup slack is -0.825 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.413 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.825 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.415 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.957 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.413 ; 3.415 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.386 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.413 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; +; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #86: Setup slack is -0.825 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.398 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.825 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.400 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.995 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.283 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.398 ; 3.400 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.406 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.410 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.371 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.398 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; +; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #87: Setup slack is -0.824 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.423 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.824 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.425 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.855 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.449 ; 13 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.423 ; 3.425 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.034 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 6.062 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 6.068 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.348 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.423 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.423 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.423 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #88: Setup slack is -0.824 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.398 ; +; Data Required Time ; 5.574 ; +; Slack ; -0.824 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.400 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.995 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.283 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.398 ; 3.400 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.406 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.410 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.371 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.398 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; +; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #89: Setup slack is -0.824 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.424 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.824 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.426 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.901 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.424 ; 3.426 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.568 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.594 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.331 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; +; 6.424 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; +; 6.424 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; +; 6.424 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #90: Setup slack is -0.823 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.410 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.823 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.412 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.945 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.410 ; 3.412 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.450 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.477 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.482 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.382 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.410 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.410 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; +; 6.410 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #91: Setup slack is -0.823 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.410 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.823 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.412 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.945 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.410 ; 3.412 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.450 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.477 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.482 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.382 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.410 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.410 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; +; 6.410 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #92: Setup slack is -0.823 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.417 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.823 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.419 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.957 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.417 ; 3.419 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.389 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; +; 6.417 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; +; 6.417 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; +; 6.417 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #93: Setup slack is -0.822 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.409 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.822 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.411 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.932 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.358 ; 10 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.409 ; 3.411 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.382 ; 0.859 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; +; 6.409 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; +; 6.409 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; +; 6.409 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.166 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #94: Setup slack is -0.822 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[22] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.451 ; +; Data Required Time ; 5.629 ; +; Slack ; -0.822 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.113 ; ; ; ; ; ; +; Data Delay ; 2.379 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.046 ; 86 ; 0.403 ; 0.979 ; +; Cell ; ; 8 ; 0.194 ; 8 ; 0.000 ; 0.069 ; +; uTco ; ; 1 ; 0.139 ; 6 ; 0.139 ; 0.139 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]|clk ; +; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; +; 6.451 ; 2.379 ; ; ; ; ; ; data path ; +; 4.211 ; 0.139 ; FF ; uTco ; 1 ; FF_X96_Y141_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]|q ; +; 4.280 ; 0.069 ; FF ; CELL ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[11] ; +; 5.259 ; 0.979 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|dataf ; +; 5.286 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; +; 5.292 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; +; 5.956 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; +; 5.984 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; +; 5.989 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[12] ; +; 6.392 ; 0.403 ; FF ; IC ; 1 ; MLABCELL_X76_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~19|datae ; +; 6.451 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X76_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~19|combout ; +; 6.451 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22]|d ; +; 6.451 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22] ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22]|clk ; +; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22] ; +; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X76_Y158_N14 ; ; vx_fetch|VX_Warp_three|real_PC[22] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #95: Setup slack is -0.821 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.408 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.821 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.410 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.964 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.408 ; 3.410 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.448 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.475 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.480 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.380 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.408 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.408 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; +; 6.408 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #96: Setup slack is -0.821 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.408 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.821 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.410 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.964 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.408 ; 3.410 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.448 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.475 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.480 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.380 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.408 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.408 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; +; 6.408 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #97: Setup slack is -0.821 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.431 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.821 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.433 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.970 ; 87 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.431 ; 3.433 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.405 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; +; 6.431 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; +; 6.431 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; +; 6.431 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #98: Setup slack is -0.821 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_address[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.371 ; +; Data Required Time ; 5.550 ; +; Slack ; -0.821 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.373 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.876 ; 85 ; 0.108 ; 0.930 ; +; Cell ; ; 12 ; 0.376 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.371 ; 3.373 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.344 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; +; 6.371 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; +; 6.371 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; +; 6.371 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #99: Setup slack is -0.821 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[10] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.423 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.821 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.104 ; ; ; ; ; ; +; Data Delay ; 2.353 ; ; ; ; ; ; +; Number of Logic Levels ; ; 2 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.327 ; 76 ; 0.000 ; 2.327 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 2 ; 2.082 ; 88 ; 0.965 ; 1.117 ; +; Cell ; ; 6 ; 0.139 ; 6 ; 0.000 ; 0.062 ; +; uTco ; ; 1 ; 0.132 ; 6 ; 0.132 ; 0.132 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.070 ; 3.070 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.070 ; 2.327 ; FF ; IC ; 1 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]|clk ; +; 4.070 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10] ; +; 6.423 ; 2.353 ; ; ; ; ; ; data path ; +; 4.202 ; 0.132 ; FF ; uTco ; 1 ; FF_X108_Y155_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]|q ; +; 4.246 ; 0.044 ; FF ; CELL ; 2 ; FF_X108_Y155_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[13] ; +; 5.211 ; 0.965 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|datae ; +; 5.273 ; 0.062 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; +; 5.279 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; +; 6.396 ; 1.117 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|dataf ; +; 6.423 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|combout ; +; 6.423 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|d ; +; 6.423 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; +; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y158_N25 ; ; vx_fetch|VX_Warp_one|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #100: Setup slack is -0.820 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.369 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.820 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.371 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.888 ; 86 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.369 ; 3.371 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.674 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.702 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.706 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.341 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.369 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.369 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.369 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #101: Setup slack is -0.820 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.368 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.820 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.370 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.887 ; 86 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.368 ; 3.370 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.674 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.702 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.706 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.340 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.368 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.368 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.368 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #102: Setup slack is -0.820 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.392 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.820 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.394 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.985 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.392 ; 3.394 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.477 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.509 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.365 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; +; 6.392 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; +; 6.392 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; +; 6.392 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #103: Setup slack is -0.819 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.367 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.819 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.369 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.901 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.348 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.367 ; 3.369 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.696 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.724 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.728 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.340 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.367 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #104: Setup slack is -0.819 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.366 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.819 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.368 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.885 ; 86 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.366 ; 3.368 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.674 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.702 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.706 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.338 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.366 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.366 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.366 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #105: Setup slack is -0.819 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.373 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.819 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.375 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.875 ; 85 ; 0.108 ; 0.929 ; +; Cell ; ; 12 ; 0.379 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.373 ; 3.375 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.344 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; +; 6.373 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; +; 6.373 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; +; 6.373 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #106: Setup slack is -0.818 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.424 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.818 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.426 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.964 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.424 ; 3.426 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.396 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; +; 6.424 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; +; 6.424 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; +; 6.424 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #107: Setup slack is -0.817 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.390 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.817 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.392 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.937 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.333 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.390 ; 3.392 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.371 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.398 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.402 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.363 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.390 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.390 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; +; 6.390 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #108: Setup slack is -0.816 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.390 ; +; Data Required Time ; 5.574 ; +; Slack ; -0.816 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.392 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.937 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.333 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.390 ; 3.392 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.371 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.398 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.402 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.363 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.390 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.390 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; +; 6.390 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #109: Setup slack is -0.816 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.409 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.816 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.411 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.891 ; 85 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.409 ; 3.411 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.327 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; +; 6.409 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; +; 6.409 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; +; 6.409 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #110: Setup slack is -0.815 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.387 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.815 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.389 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.966 ; 88 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.301 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.387 ; 3.389 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.472 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.499 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.504 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.360 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; +; 6.387 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; +; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; +; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #111: Setup slack is -0.813 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.422 ; +; Data Required Time ; 5.609 ; +; Slack ; -0.813 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.424 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.843 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 14 ; 0.460 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.422 ; 3.424 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.183 ; 0.769 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; +; 6.212 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; +; 6.218 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; +; 6.346 ; 0.128 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; +; 6.422 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; +; 6.422 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; +; 6.422 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #112: Setup slack is -0.812 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.398 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.812 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.400 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.883 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.398 ; 3.400 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.592 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.618 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.624 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.336 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.398 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.398 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #113: Setup slack is -0.812 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.404 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.812 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.406 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.947 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.404 ; 3.406 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.325 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; +; 6.404 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; +; 6.404 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; +; 6.404 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #114: Setup slack is -0.812 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.407 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.812 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.409 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.793 ; 82 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.494 ; 14 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.407 ; 3.409 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.344 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.424 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.428 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.282 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; +; 6.407 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; +; 6.407 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; +; 6.407 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #115: Setup slack is -0.812 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.812 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.838 ; 86 ; 0.119 ; 1.398 ; +; Cell ; ; 10 ; 0.325 ; 10 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.517 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.851 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.879 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.884 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.282 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #116: Setup slack is -0.812 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.396 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.812 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.398 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.917 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.360 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.396 ; 3.398 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.367 ; 0.844 ; FF ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; +; 6.396 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; +; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; +; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #117: Setup slack is -0.812 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.422 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.812 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.424 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.843 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 14 ; 0.460 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.422 ; 3.424 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.173 ; 0.759 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; +; 6.200 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; +; 6.206 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; +; 6.344 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; +; 6.422 ; 0.078 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; +; 6.422 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; +; 6.422 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #118: Setup slack is -0.810 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.403 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.810 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.405 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.998 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.403 ; 3.405 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.377 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.403 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.403 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; +; 6.403 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #119: Setup slack is -0.810 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.405 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.810 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.407 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.812 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.474 ; 14 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.405 ; 3.407 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.342 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.422 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.426 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.280 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; +; 6.405 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; +; 6.405 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; +; 6.405 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #120: Setup slack is -0.810 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.405 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.810 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.407 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.793 ; 82 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.492 ; 14 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.405 ; 3.407 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.344 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.424 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.428 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.282 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; +; 6.405 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; +; 6.405 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; +; 6.405 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #121: Setup slack is -0.810 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.397 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.810 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.399 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.935 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.397 ; 3.399 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.437 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.464 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.469 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.369 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.397 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.397 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; +; 6.397 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #122: Setup slack is -0.810 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.397 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.810 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.399 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.935 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.397 ; 3.399 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.437 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.464 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.469 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.369 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.397 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.397 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; +; 6.397 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #123: Setup slack is -0.809 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.411 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.809 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.413 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.841 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.451 ; 13 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.411 ; 3.413 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.040 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 6.070 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 6.076 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.336 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.411 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.411 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.411 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #124: Setup slack is -0.809 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.403 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.809 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.405 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.998 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.403 ; 3.405 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.377 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.403 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.403 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; +; 6.403 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #125: Setup slack is -0.809 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.381 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.809 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.383 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.950 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.312 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.381 ; 3.383 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.466 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.493 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.498 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.354 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; +; 6.381 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; +; 6.381 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; +; 6.381 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #126: Setup slack is -0.808 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.403 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.808 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.405 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.812 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.472 ; 14 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.403 ; 3.405 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.342 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.422 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.426 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.280 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; +; 6.403 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; +; 6.403 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; +; 6.403 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #127: Setup slack is -0.808 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.418 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.808 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.420 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 3.011 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.289 ; 8 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.418 ; 3.420 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.610 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.392 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; +; 6.418 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; +; 6.418 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; +; 6.418 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #128: Setup slack is -0.806 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.405 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.806 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.407 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.856 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.429 ; 13 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.405 ; 3.407 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.016 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 6.044 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 6.050 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.330 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.405 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.405 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.405 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #129: Setup slack is -0.805 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.805 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.277 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.867 ; 87 ; 0.119 ; 1.398 ; +; Cell ; ; 10 ; 0.290 ; 9 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.275 ; 3.277 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.510 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.844 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.872 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.275 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #130: Setup slack is -0.804 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.396 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.804 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.398 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.889 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.387 ; 11 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.396 ; 3.398 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.317 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; +; 6.396 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; +; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; +; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #131: Setup slack is -0.804 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.391 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.804 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.393 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.986 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.391 ; 3.393 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.365 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; +; 6.391 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; +; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; +; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #132: Setup slack is -0.803 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.404 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.803 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.406 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.927 ; 86 ; 0.119 ; 1.046 ; +; Cell ; ; 14 ; 0.357 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.404 ; 3.406 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.604 ; 0.119 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.631 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.636 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.682 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.708 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.712 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.837 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.861 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.867 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.271 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.297 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.303 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.317 ; 1.014 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; +; 6.404 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; +; 6.404 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; +; 6.404 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #133: Setup slack is -0.803 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.396 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.803 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.398 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.932 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 10 ; 0.000 ; 0.082 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.396 ; 3.398 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.314 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; +; 6.396 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; +; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; +; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #134: Setup slack is -0.803 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.413 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.803 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.415 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.992 ; 88 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.301 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.413 ; 3.415 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.605 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.387 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; +; 6.413 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; +; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; +; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #135: Setup slack is -0.803 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.387 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.803 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.389 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.845 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.423 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.387 ; 3.389 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.460 ; 0.534 ; RR ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.488 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.492 ; 0.004 ; FF ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.295 ; 0.803 ; FF ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; +; 6.387 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; +; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; +; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #136: Setup slack is -0.803 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_mask[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.391 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.803 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.393 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.874 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.391 ; 3.393 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.704 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.730 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.736 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.363 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; +; 6.391 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; +; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; +; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #137: Setup slack is -0.803 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_mask[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.391 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.803 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.393 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.874 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.391 ; 3.393 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.704 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.730 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.736 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.363 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; +; 6.391 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; +; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; +; 6.391 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #138: Setup slack is -0.802 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.395 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.802 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.397 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.940 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.395 ; 3.397 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.369 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.395 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.395 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; +; 6.395 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #139: Setup slack is -0.802 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.389 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.802 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.391 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.923 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.389 ; 3.391 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.534 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.362 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.389 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; +; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #140: Setup slack is -0.802 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.416 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.802 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.418 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.958 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.416 ; 3.418 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.390 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; +; 6.416 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; +; 6.416 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; +; 6.416 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #141: Setup slack is -0.801 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.395 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.801 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.397 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.940 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.395 ; 3.397 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.369 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.395 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.395 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; +; 6.395 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #142: Setup slack is -0.801 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.389 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.801 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.391 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.923 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.389 ; 3.391 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.534 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.362 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.389 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; +; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #143: Setup slack is -0.801 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.400 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.801 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.402 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.832 ; 83 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.449 ; 13 ; 0.000 ; 0.134 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.400 ; 3.402 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.546 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.266 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; +; 6.400 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; +; 6.400 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; +; 6.400 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #144: Setup slack is -0.801 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.349 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.801 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.351 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.721 ; 81 ; 0.192 ; 0.667 ; +; Cell ; ; 14 ; 0.509 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.349 ; 3.351 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.655 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.683 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.687 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.321 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.349 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.349 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.349 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #145: Setup slack is -0.801 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.350 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.801 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.352 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.722 ; 81 ; 0.192 ; 0.667 ; +; Cell ; ; 14 ; 0.509 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.350 ; 3.352 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.655 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.683 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.687 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.322 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.350 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.350 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.350 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #146: Setup slack is -0.800 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.387 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.800 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.389 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.942 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.387 ; 3.389 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.532 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.360 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.387 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; +; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #147: Setup slack is -0.800 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.396 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.800 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.398 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.872 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.405 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.396 ; 3.398 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.363 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; +; 5.392 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; +; 5.396 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; +; 6.304 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; +; 6.396 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #148: Setup slack is -0.800 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.348 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.800 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.356 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.736 ; 82 ; 0.192 ; 0.682 ; +; Cell ; ; 14 ; 0.493 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.348 ; 3.356 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.654 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.682 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.686 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.320 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.348 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.348 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.348 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #149: Setup slack is -0.800 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.349 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.800 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.357 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.737 ; 82 ; 0.192 ; 0.682 ; +; Cell ; ; 14 ; 0.493 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.349 ; 3.357 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.654 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.682 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.686 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.321 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.349 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.349 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.349 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #150: Setup slack is -0.800 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.347 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.800 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.349 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.719 ; 81 ; 0.192 ; 0.667 ; +; Cell ; ; 14 ; 0.509 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.347 ; 3.349 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.655 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.683 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.687 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.319 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.347 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #151: Setup slack is -0.799 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.387 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.799 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.389 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.942 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.387 ; 3.389 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.532 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.360 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.387 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; +; 6.387 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #152: Setup slack is -0.799 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.394 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.799 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.396 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.783 ; 82 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.492 ; 14 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.394 ; 3.396 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.331 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.411 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.415 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.269 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; +; 6.394 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; +; 6.394 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; +; 6.394 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #153: Setup slack is -0.799 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.399 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.799 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.401 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.941 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.399 ; 3.401 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.372 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.399 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.399 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; +; 6.399 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #154: Setup slack is -0.799 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.457 ; +; Slack ; -0.799 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.754 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.256 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|sload ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.457 ; 0.014 ; ; uTsu ; 1 ; FF_X73_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #155: Setup slack is -0.799 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.346 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.799 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.354 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.734 ; 82 ; 0.192 ; 0.682 ; +; Cell ; ; 14 ; 0.493 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.346 ; 3.354 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.654 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.682 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.686 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.318 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.346 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #156: Setup slack is -0.799 (VIOLATED) +=============================================================================== ++----------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.353 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.799 (VIOLATED) ; ++--------------------+-------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.355 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.856 ; 85 ; 0.108 ; 0.910 ; +; Cell ; ; 12 ; 0.378 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.353 ; 3.355 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.325 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; +; 6.353 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|d ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #157: Setup slack is -0.799 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.799 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.806 ; 86 ; 0.119 ; 1.297 ; +; Cell ; ; 10 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.264 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|ena ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N32 ; ; vx_f_d_reg|curr_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #158: Setup slack is -0.799 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.799 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.806 ; 86 ; 0.119 ; 1.297 ; +; Cell ; ; 10 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.264 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|ena ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N38 ; ; vx_f_d_reg|curr_PC[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #159: Setup slack is -0.798 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.385 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.798 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.387 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.792 ; 82 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.473 ; 14 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.385 ; 3.387 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.647 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.673 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.679 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.278 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.385 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.385 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.385 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #160: Setup slack is -0.798 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.391 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.798 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.393 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.913 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.082 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.391 ; 3.393 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.309 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; +; 6.391 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; +; 6.391 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; +; 6.391 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #161: Setup slack is -0.798 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.353 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.798 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.355 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.856 ; 85 ; 0.108 ; 0.910 ; +; Cell ; ; 12 ; 0.378 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.353 ; 3.355 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.325 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; +; 6.353 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|d ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N17 ; ; vx_d_e_reg|b_reg_data[24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #162: Setup slack is -0.798 (VIOLATED) +=============================================================================== ++--------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.399 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.798 (VIOLATED) ; ++--------------------+-----------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.401 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.941 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.399 ; 3.401 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.372 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.399 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.399 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; +; 6.399 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #163: Setup slack is -0.797 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.384 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.797 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.386 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.792 ; 82 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.472 ; 14 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.384 ; 3.386 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.647 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.673 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.679 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.278 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.384 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #164: Setup slack is -0.797 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.345 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.797 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.347 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.865 ; 86 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.360 ; 11 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.345 ; 3.347 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.674 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.702 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.706 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.318 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.345 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #165: Setup slack is -0.797 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.392 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.797 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.394 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.783 ; 82 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.490 ; 14 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.392 ; 3.394 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.331 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.411 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.415 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.269 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; +; 6.392 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; +; 6.392 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; +; 6.392 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #166: Setup slack is -0.797 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.384 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.797 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.386 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.976 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.384 ; 3.386 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.424 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.451 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.456 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.356 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.384 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; +; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #167: Setup slack is -0.797 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.384 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.797 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.386 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.976 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.384 ; 3.386 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.424 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.451 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.456 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.356 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.384 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; +; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #168: Setup slack is -0.797 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.407 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.797 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.409 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.976 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.312 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.407 ; 3.409 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.599 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.381 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; +; 6.407 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; +; 6.407 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; +; 6.407 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #169: Setup slack is -0.797 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.382 ; +; Data Required Time ; 5.585 ; +; Slack ; -0.797 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.384 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.839 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.424 ; 13 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.382 ; 3.384 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.460 ; 0.534 ; RR ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.488 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.492 ; 0.004 ; FF ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.289 ; 0.797 ; FF ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; +; 6.382 ; 0.093 ; FF ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; +; 6.382 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; +; 6.382 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #170: Setup slack is -0.797 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[19] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.351 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.797 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.353 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.854 ; 85 ; 0.108 ; 0.908 ; +; Cell ; ; 12 ; 0.378 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.351 ; 3.353 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.323 ; 0.908 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|dataf ; +; 6.351 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|combout ; +; 6.351 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|d ; +; 6.351 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N22 ; ; vx_d_e_reg|b_reg_data[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #171: Setup slack is -0.796 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.395 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.796 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.397 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.899 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 14 ; 0.378 ; 11 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.395 ; 3.397 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.006 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 6.034 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 6.040 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.320 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.395 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.395 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.395 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #172: Setup slack is -0.796 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.383 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.796 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.385 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.928 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.383 ; 3.385 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.357 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; +; 6.383 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; +; 6.383 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; +; 6.383 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #173: Setup slack is -0.796 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[12] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.460 ; +; Slack ; -0.796 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.754 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.256 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|sload ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.460 ; 0.017 ; ; uTsu ; 1 ; FF_X73_Y161_N46 ; ; vx_fetch|VX_Warp_zero|real_PC[12] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #174: Setup slack is -0.796 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.349 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.796 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.351 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.851 ; 85 ; 0.108 ; 0.905 ; +; Cell ; ; 12 ; 0.379 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.349 ; 3.351 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.320 ; 0.905 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|dataf ; +; 6.349 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|combout ; +; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|d ; +; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N25 ; ; vx_d_e_reg|b_reg_data[31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #175: Setup slack is -0.795 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.396 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.795 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.398 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.832 ; 83 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.445 ; 13 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.396 ; 3.398 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.546 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.266 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; +; 6.396 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; +; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; +; 6.396 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #176: Setup slack is -0.795 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.795 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.754 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.256 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|sload ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.018 ; ; uTsu ; 1 ; FF_X73_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #177: Setup slack is -0.795 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.378 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.795 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.380 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.920 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.378 ; 3.380 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.599 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.350 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; +; 6.378 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; +; 6.378 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; +; 6.378 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #178: Setup slack is -0.794 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.393 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.794 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.395 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.988 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.393 ; 3.395 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.367 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; +; 6.393 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; +; 6.393 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; +; 6.393 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #179: Setup slack is -0.794 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.395 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.794 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.397 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.879 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.395 ; 3.397 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.296 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.323 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.329 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.308 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; +; 6.395 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; +; 6.395 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; +; 6.395 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #180: Setup slack is -0.793 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.366 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.793 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.368 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.903 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.366 ; 3.368 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.347 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.374 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.378 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.339 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.366 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.366 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; +; 6.366 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #181: Setup slack is -0.793 (VIOLATED) +=============================================================================== ++----------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------+ +; Property ; Value ; ++--------------------+-------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.379 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.793 (VIOLATED) ; ++--------------------+-------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.381 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.717 ; 80 ; 0.192 ; 0.712 ; +; Cell ; ; 14 ; 0.543 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.379 ; 3.381 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.573 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.599 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.605 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.317 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.379 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #182: Setup slack is -0.793 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.341 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.793 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.349 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.722 ; 81 ; 0.138 ; 0.722 ; +; Cell ; ; 14 ; 0.502 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.341 ; 3.349 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.647 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.675 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.679 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.313 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.341 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #183: Setup slack is -0.793 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.342 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.793 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.350 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.723 ; 81 ; 0.138 ; 0.722 ; +; Cell ; ; 14 ; 0.502 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.342 ; 3.350 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.647 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.675 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.679 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.314 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.342 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.342 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.342 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #184: Setup slack is -0.792 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.392 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.792 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.394 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.922 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.350 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.392 ; 3.394 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.536 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.562 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.568 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.299 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; +; 6.392 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; +; 6.392 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; +; 6.392 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #185: Setup slack is -0.792 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.366 ; +; Data Required Time ; 5.574 ; +; Slack ; -0.792 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.368 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.903 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.366 ; 3.368 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.347 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.374 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.378 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.339 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.366 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.366 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; +; 6.366 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #186: Setup slack is -0.792 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.379 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.792 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.381 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.957 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.379 ; 3.381 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.419 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.446 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.451 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.351 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.379 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; +; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #187: Setup slack is -0.792 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.379 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.792 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.381 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.957 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.379 ; 3.381 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.419 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.446 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.451 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.351 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.379 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; +; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #188: Setup slack is -0.792 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.385 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.792 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.387 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.897 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.369 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.385 ; 3.387 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.303 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; +; 6.385 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; +; 6.385 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; +; 6.385 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #189: Setup slack is -0.792 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.378 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.792 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.386 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.732 ; 81 ; 0.192 ; 0.712 ; +; Cell ; ; 14 ; 0.527 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.378 ; 3.386 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.572 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.598 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.604 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.316 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.378 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.378 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.378 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #190: Setup slack is -0.792 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.339 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.792 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.347 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.720 ; 81 ; 0.138 ; 0.722 ; +; Cell ; ; 14 ; 0.502 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.339 ; 3.347 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.647 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.675 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.679 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.311 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.339 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #191: Setup slack is -0.791 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.393 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.791 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.395 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.842 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.431 ; 13 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.393 ; 3.395 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.022 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 6.052 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 6.058 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.318 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.393 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.393 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.393 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #192: Setup slack is -0.791 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.385 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.791 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.387 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.978 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.385 ; 3.387 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.357 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; +; 6.385 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; +; 6.385 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; +; 6.385 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #193: Setup slack is -0.791 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.364 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.791 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.366 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.922 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.323 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.364 ; 3.366 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.345 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.372 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.376 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.337 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.364 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.364 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; +; 6.364 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #194: Setup slack is -0.790 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.364 ; +; Data Required Time ; 5.574 ; +; Slack ; -0.790 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.366 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.922 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.323 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.364 ; 3.366 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.345 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.372 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.376 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.337 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.364 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.364 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; +; 6.364 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #195: Setup slack is -0.789 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.391 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.789 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.393 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.876 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.391 ; 3.393 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.020 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 6.049 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 6.055 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.318 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.391 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.391 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.391 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #196: Setup slack is -0.789 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.338 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.789 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.340 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.884 ; 86 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.338 ; 3.340 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.643 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.671 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.675 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.310 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.338 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.338 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.338 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #197: Setup slack is -0.789 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.337 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.789 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.339 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.883 ; 86 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.337 ; 3.339 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.643 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.671 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.675 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.309 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.337 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.337 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.337 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #198: Setup slack is -0.789 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.376 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.789 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.378 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.913 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.376 ; 3.378 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.521 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.349 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.376 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.376 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; +; 6.376 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #199: Setup slack is -0.788 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.335 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.788 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.337 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.881 ; 86 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.335 ; 3.337 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.643 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.671 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.675 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.307 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.335 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #200: Setup slack is -0.788 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.376 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.788 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.378 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.913 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.376 ; 3.378 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.521 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.349 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.376 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.376 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; +; 6.376 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #201: Setup slack is -0.788 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.372 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.788 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.374 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.913 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.372 ; 3.374 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.344 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; +; 6.372 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; +; 6.372 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; +; 6.372 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #202: Setup slack is -0.787 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.373 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.787 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.375 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.969 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.284 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.373 ; 3.375 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.479 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.506 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.512 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.347 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; +; 6.373 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; +; 6.373 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; +; 6.373 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #203: Setup slack is -0.786 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.392 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.786 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.394 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.985 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.392 ; 3.394 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.364 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; +; 6.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; +; 6.392 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; +; 6.392 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #204: Setup slack is -0.786 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.385 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.786 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.387 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.930 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.385 ; 3.387 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.359 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; +; 6.385 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; +; 6.385 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; +; 6.385 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #205: Setup slack is -0.786 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.381 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.786 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.383 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.824 ; 83 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.439 ; 13 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.381 ; 3.383 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.318 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.398 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.402 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.256 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; +; 6.381 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; +; 6.381 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; +; 6.381 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #206: Setup slack is -0.786 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.373 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.786 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.375 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.941 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.373 ; 3.375 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.413 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.440 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.445 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.345 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.373 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.373 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; +; 6.373 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #207: Setup slack is -0.786 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.373 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.786 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.375 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.941 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.373 ; 3.375 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.413 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.440 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.445 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.345 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.373 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.373 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; +; 6.373 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #208: Setup slack is -0.785 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.371 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.785 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.379 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.718 ; 80 ; 0.138 ; 0.722 ; +; Cell ; ; 14 ; 0.536 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.371 ; 3.379 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.565 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.591 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.597 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.309 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.371 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #209: Setup slack is -0.784 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.384 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.784 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.386 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.864 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.384 ; 3.386 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.528 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.554 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.560 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.291 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; +; 6.384 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; +; 6.384 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; +; 6.384 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #210: Setup slack is -0.784 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.379 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.784 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.381 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.824 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.437 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.379 ; 3.381 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.318 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.398 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.402 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.256 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; +; 6.379 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; +; 6.379 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; +; 6.379 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #211: Setup slack is -0.783 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.377 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.783 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.379 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.920 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.377 ; 3.379 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.349 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; +; 6.377 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; +; 6.377 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; +; 6.377 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #212: Setup slack is -0.783 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.783 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.831 ; 87 ; 0.119 ; 1.398 ; +; Cell ; ; 10 ; 0.302 ; 9 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.488 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.822 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.850 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.855 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.253 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #213: Setup slack is -0.783 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|a_reg_data[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.175 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.783 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.177 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.706 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.175 ; 3.177 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.175 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|sclr ; +; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N16 ; ; vx_d_e_reg|a_reg_data[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #214: Setup slack is -0.783 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|a_reg_data[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.175 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.783 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.177 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.706 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.175 ; 3.177 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.175 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|sclr ; +; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N26 ; ; vx_d_e_reg|a_reg_data[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #215: Setup slack is -0.783 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.175 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.783 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.177 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.706 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.175 ; 3.177 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.175 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|sclr ; +; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N25 ; ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #216: Setup slack is -0.782 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.388 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.782 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.390 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.809 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.459 ; 14 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.388 ; 3.390 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.108 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.135 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.141 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.312 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.388 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.388 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; +; 6.388 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #217: Setup slack is -0.782 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[19] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.421 ; +; Data Required Time ; 5.639 ; +; Slack ; -0.782 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.090 ; ; ; ; ; ; +; Data Delay ; 2.366 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.312 ; 76 ; 0.000 ; 2.312 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.018 ; 85 ; 0.551 ; 0.786 ; +; Cell ; ; 8 ; 0.216 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.132 ; 6 ; 0.132 ; 0.132 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.055 ; 3.055 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.055 ; 2.312 ; FF ; IC ; 1 ; FF_X90_Y148_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19]|clk ; +; 4.055 ; 0.000 ; FR ; CELL ; 1 ; FF_X90_Y148_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19] ; +; 6.421 ; 2.366 ; ; ; ; ; ; data path ; +; 4.187 ; 0.132 ; FF ; uTco ; 1 ; FF_X90_Y148_N56 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19]|q ; +; 4.230 ; 0.043 ; FF ; CELL ; 1 ; FF_X90_Y148_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19]~la_mlab/laboutb[17] ; +; 4.911 ; 0.681 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|datad ; +; 4.989 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; +; 4.994 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; +; 5.780 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; +; 5.806 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; +; 5.811 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; +; 6.362 ; 0.551 ; FF ; IC ; 1 ; MLABCELL_X74_Y160_N30 ; High Speed ; vx_fetch|VX_Warp_two|i199~16|datae ; +; 6.421 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X74_Y160_N30 ; High Speed ; vx_fetch|VX_Warp_two|i199~16|combout ; +; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19]|d ; +; 6.421 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19] ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19] ; +; 5.465 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.639 ; 0.204 ; ; uTsu ; 1 ; FF_X74_Y160_N32 ; ; vx_fetch|VX_Warp_two|real_PC[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #218: Setup slack is -0.781 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.367 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.781 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.369 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.879 ; 85 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.368 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.367 ; 3.369 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.561 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.587 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.593 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.305 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.367 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #219: Setup slack is -0.781 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.376 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.781 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.378 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.805 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.451 ; 13 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.376 ; 3.378 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.313 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.393 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.397 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.251 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; +; 6.376 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; +; 6.376 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; +; 6.376 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #220: Setup slack is -0.781 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.381 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.781 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.383 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.866 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.381 ; 3.383 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.298 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; +; 6.381 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; +; 6.381 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; +; 6.381 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #221: Setup slack is -0.781 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.249 ; +; Data Required Time ; 5.468 ; +; Slack ; -0.781 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.028 ; ; ; ; ; ; +; Data Delay ; 3.251 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.791 ; 86 ; 0.119 ; 1.282 ; +; Cell ; ; 10 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.249 ; 3.251 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.249 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|ena ; +; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; +; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N25 ; ; vx_f_d_reg|curr_PC[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #222: Setup slack is -0.781 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.249 ; +; Data Required Time ; 5.468 ; +; Slack ; -0.781 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.028 ; ; ; ; ; ; +; Data Delay ; 3.251 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.791 ; 86 ; 0.119 ; 1.282 ; +; Cell ; ; 10 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.249 ; 3.251 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.249 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|ena ; +; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; +; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N44 ; ; vx_f_d_reg|curr_PC[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #223: Setup slack is -0.781 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; +; To Node ; vx_e_m_reg|csr_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.379 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.781 (VIOLATED) ; ++--------------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.001 ; ; ; ; ; ; +; Data Delay ; 3.416 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.336 ; 79 ; 0.000 ; 2.336 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.895 ; 85 ; 0.122 ; 0.959 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.963 ; 2.963 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.963 ; 2.336 ; RR ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|clk ; +; 2.963 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; +; 6.379 ; 3.416 ; ; ; ; ; ; data path ; +; 3.090 ; 0.127 ; RR ; uTco ; 1 ; FF_X38_Y157_N16 ; ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|q ; +; 3.150 ; 0.060 ; RR ; CELL ; 648 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE~la_lab/laboutt[10] ; +; 4.109 ; 0.959 ; RR ; IC ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|datad ; +; 4.189 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|combout ; +; 4.193 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89~la_lab/laboutb[6] ; +; 4.454 ; 0.261 ; FF ; IC ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|dataf ; +; 4.482 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|combout ; +; 4.487 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105~la_lab/laboutt[15] ; +; 5.142 ; 0.655 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datac ; +; 5.228 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; +; 5.234 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; +; 5.357 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; +; 5.420 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.424 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.199 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.226 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.231 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.353 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; +; 6.379 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; +; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; +; 6.379 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; +; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #224: Setup slack is -0.780 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.388 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.780 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.390 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.809 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.459 ; 14 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.388 ; 3.390 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.108 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.135 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.141 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.312 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.388 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.388 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; +; 6.388 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #225: Setup slack is -0.780 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.372 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.780 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.374 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.855 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.372 ; 3.374 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.293 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; +; 6.372 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; +; 6.372 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; +; 6.372 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #226: Setup slack is -0.780 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.353 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.780 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.355 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.893 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.353 ; 3.355 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.334 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.361 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.365 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.326 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.353 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; +; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #227: Setup slack is -0.780 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|a_reg_data[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.175 ; +; Data Required Time ; 5.395 ; +; Slack ; -0.780 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.177 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.706 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.175 ; 3.177 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.175 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|sclr ; +; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N38 ; ; vx_d_e_reg|a_reg_data[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #228: Setup slack is -0.780 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[22] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.414 ; +; Data Required Time ; 5.634 ; +; Slack ; -0.780 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.108 ; ; ; ; ; ; +; Data Delay ; 2.342 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.004 ; 86 ; 0.361 ; 0.979 ; +; Cell ; ; 8 ; 0.199 ; 8 ; 0.000 ; 0.069 ; +; uTco ; ; 1 ; 0.139 ; 6 ; 0.139 ; 0.139 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]|clk ; +; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; +; 6.414 ; 2.342 ; ; ; ; ; ; data path ; +; 4.211 ; 0.139 ; FF ; uTco ; 1 ; FF_X96_Y141_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]|q ; +; 4.280 ; 0.069 ; FF ; CELL ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[11] ; +; 5.259 ; 0.979 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|dataf ; +; 5.286 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; +; 5.292 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; +; 5.956 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; +; 5.984 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; +; 5.990 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[13] ; +; 6.351 ; 0.361 ; FF ; IC ; 1 ; LABCELL_X75_Y157_N36 ; High Speed ; vx_fetch|VX_Warp_one|i199~17|datae ; +; 6.414 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X75_Y157_N36 ; High Speed ; vx_fetch|VX_Warp_one|i199~17|combout ; +; 6.414 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22]|d ; +; 6.414 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22] ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22] ; +; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.634 ; 0.200 ; ; uTsu ; 1 ; FF_X75_Y157_N37 ; ; vx_fetch|VX_Warp_one|real_PC[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #229: Setup slack is -0.780 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[22] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.413 ; +; Data Required Time ; 5.633 ; +; Slack ; -0.780 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.108 ; ; ; ; ; ; +; Data Delay ; 2.341 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.003 ; 86 ; 0.360 ; 0.979 ; +; Cell ; ; 8 ; 0.199 ; 9 ; 0.000 ; 0.069 ; +; uTco ; ; 1 ; 0.139 ; 6 ; 0.139 ; 0.139 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]|clk ; +; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22] ; +; 6.413 ; 2.341 ; ; ; ; ; ; data path ; +; 4.211 ; 0.139 ; FF ; uTco ; 1 ; FF_X96_Y141_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]|q ; +; 4.280 ; 0.069 ; FF ; CELL ; 1 ; FF_X96_Y141_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[11] ; +; 5.259 ; 0.979 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|dataf ; +; 5.286 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; +; 5.292 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; +; 5.956 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; +; 5.984 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; +; 5.990 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[13] ; +; 6.350 ; 0.360 ; FF ; IC ; 1 ; LABCELL_X75_Y157_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~19|datae ; +; 6.413 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X75_Y157_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~19|combout ; +; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22]|d ; +; 6.413 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22] ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22] ; +; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.633 ; 0.199 ; ; uTsu ; 1 ; FF_X75_Y157_N43 ; ; vx_fetch|VX_Warp_two|real_PC[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #230: Setup slack is -0.780 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|a_reg_data[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.175 ; +; Data Required Time ; 5.395 ; +; Slack ; -0.780 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.177 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.706 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.175 ; 3.177 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.175 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|sclr ; +; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N32 ; ; vx_d_e_reg|a_reg_data[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #231: Setup slack is -0.779 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.365 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.779 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.367 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.911 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.365 ; 3.367 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.471 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.498 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.504 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.339 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; +; 6.365 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; +; 6.365 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; +; 6.365 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #232: Setup slack is -0.779 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.353 ; +; Data Required Time ; 5.574 ; +; Slack ; -0.779 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.355 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.893 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.353 ; 3.355 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.334 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.361 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.365 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.326 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.353 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; +; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #233: Setup slack is -0.779 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.374 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.779 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.376 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.805 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.449 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.374 ; 3.376 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.313 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.393 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.397 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.251 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; +; 6.374 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; +; 6.374 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; +; 6.374 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #234: Setup slack is -0.778 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.361 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.778 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.363 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.956 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.361 ; 3.363 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.479 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.506 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.512 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.334 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; +; 6.361 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; +; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; +; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #235: Setup slack is -0.778 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.384 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.778 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.386 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.927 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.384 ; 3.386 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.356 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; +; 6.384 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; +; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; +; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #236: Setup slack is -0.778 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.371 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.778 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.373 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.906 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.371 ; 3.373 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.345 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.371 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; +; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #237: Setup slack is -0.778 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.370 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.778 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.372 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.874 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.377 ; 11 ; 0.000 ; 0.079 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.370 ; 3.372 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.291 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; +; 6.370 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; +; 6.370 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; +; 6.370 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #238: Setup slack is -0.778 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.326 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.778 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.328 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.699 ; 81 ; 0.192 ; 0.667 ; +; Cell ; ; 14 ; 0.508 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.326 ; 3.328 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.655 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.683 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.687 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.299 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.326 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.326 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.326 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #239: Setup slack is -0.777 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.371 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.777 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.373 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.906 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.371 ; 3.373 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.345 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.371 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; +; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #240: Setup slack is -0.777 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.349 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.777 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.351 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.961 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.270 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.349 ; 3.351 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.434 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.466 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.322 ; 0.856 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|dataf ; +; 6.349 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~521|combout ; +; 6.349 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|d ; +; 6.349 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #241: Setup slack is -0.777 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|a_reg_data[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.218 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.777 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.220 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.749 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.218 ; 3.220 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.218 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|sclr ; +; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N43 ; ; vx_d_e_reg|a_reg_data[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #242: Setup slack is -0.777 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|a_reg_data[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.218 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.777 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.220 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.749 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.218 ; 3.220 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.218 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|sclr ; +; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #243: Setup slack is -0.777 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|a_reg_data[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.218 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.777 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.220 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.749 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.218 ; 3.220 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.218 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|sclr ; +; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N40 ; ; vx_d_e_reg|a_reg_data[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #244: Setup slack is -0.777 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.325 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.777 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.333 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.714 ; 81 ; 0.192 ; 0.682 ; +; Cell ; ; 14 ; 0.492 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.325 ; 3.333 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.654 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.682 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.686 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.298 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.325 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.325 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.325 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #245: Setup slack is -0.776 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.369 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.776 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.371 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.925 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.369 ; 3.371 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.343 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.369 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.369 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; +; 6.369 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #246: Setup slack is -0.776 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.363 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.776 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.365 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.954 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.291 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.363 ; 3.365 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.474 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.502 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.508 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.336 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.363 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.363 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; +; 6.363 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #247: Setup slack is -0.776 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|a_reg_data[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.218 ; +; Data Required Time ; 5.442 ; +; Slack ; -0.776 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.220 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.749 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.218 ; 3.220 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.218 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|sclr ; +; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.442 ; 0.054 ; ; uTsu ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #248: Setup slack is -0.776 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.330 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.776 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.332 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.834 ; 85 ; 0.108 ; 0.888 ; +; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.330 ; 3.332 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.303 ; 0.888 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|dataf ; +; 6.330 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|combout ; +; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|d ; +; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #249: Setup slack is -0.776 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; +; To Node ; vx_e_m_reg|alu_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.371 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.776 (VIOLATED) ; ++--------------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.001 ; ; ; ; ; ; +; Data Delay ; 3.408 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.336 ; 79 ; 0.000 ; 2.336 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.887 ; 85 ; 0.114 ; 0.959 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.963 ; 2.963 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.963 ; 2.336 ; RR ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|clk ; +; 2.963 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; +; 6.371 ; 3.408 ; ; ; ; ; ; data path ; +; 3.090 ; 0.127 ; RR ; uTco ; 1 ; FF_X38_Y157_N16 ; ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|q ; +; 3.150 ; 0.060 ; RR ; CELL ; 648 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE~la_lab/laboutt[10] ; +; 4.109 ; 0.959 ; RR ; IC ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|datad ; +; 4.189 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|combout ; +; 4.193 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89~la_lab/laboutb[6] ; +; 4.454 ; 0.261 ; FF ; IC ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|dataf ; +; 4.482 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|combout ; +; 4.487 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105~la_lab/laboutt[15] ; +; 5.142 ; 0.655 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datac ; +; 5.228 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; +; 5.234 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; +; 5.357 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; +; 5.420 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.424 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.199 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.226 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.231 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.345 ; 0.114 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; +; 6.371 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; +; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; +; 6.371 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; +; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.163 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #250: Setup slack is -0.775 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.369 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.775 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.371 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.925 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.369 ; 3.371 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.343 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.369 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.369 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; +; 6.369 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #251: Setup slack is -0.775 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.363 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.775 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.365 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.954 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.291 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.363 ; 3.365 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.474 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.502 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.508 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.336 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.363 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.363 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; +; 6.363 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #252: Setup slack is -0.775 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.370 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.775 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.372 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 83 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.370 ; 3.372 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.307 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.387 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.391 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.245 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; +; 6.370 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; +; 6.370 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; +; 6.370 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #253: Setup slack is -0.775 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.368 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.775 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.370 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.908 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.368 ; 3.370 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.341 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; +; 6.368 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; +; 6.368 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; +; 6.368 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #254: Setup slack is -0.775 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[19] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.414 ; +; Data Required Time ; 5.639 ; +; Slack ; -0.775 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.090 ; ; ; ; ; ; +; Data Delay ; 2.359 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.312 ; 76 ; 0.000 ; 2.312 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.062 ; 87 ; 0.551 ; 0.786 ; +; Cell ; ; 8 ; 0.164 ; 7 ; 0.000 ; 0.059 ; +; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.055 ; 3.055 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.055 ; 2.312 ; FF ; IC ; 1 ; FF_X92_Y148_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19]|clk ; +; 4.055 ; 0.000 ; FR ; CELL ; 1 ; FF_X92_Y148_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19] ; +; 6.414 ; 2.359 ; ; ; ; ; ; data path ; +; 4.188 ; 0.133 ; FF ; uTco ; 1 ; FF_X92_Y148_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19]|q ; +; 4.231 ; 0.043 ; FF ; CELL ; 1 ; FF_X92_Y148_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19]~la_mlab/laboutt[9] ; +; 4.956 ; 0.725 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|dataf ; +; 4.982 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; +; 4.987 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; +; 5.773 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; +; 5.799 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; +; 5.804 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; +; 6.355 ; 0.551 ; FF ; IC ; 1 ; MLABCELL_X74_Y160_N30 ; High Speed ; vx_fetch|VX_Warp_two|i199~16|datae ; +; 6.414 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X74_Y160_N30 ; High Speed ; vx_fetch|VX_Warp_two|i199~16|combout ; +; 6.414 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19]|d ; +; 6.414 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19] ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y160_N32 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[19] ; +; 5.465 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.639 ; 0.204 ; ; uTsu ; 1 ; FF_X74_Y160_N32 ; ; vx_fetch|VX_Warp_two|real_PC[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #255: Setup slack is -0.773 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.368 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.773 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.370 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 83 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.460 ; 14 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.368 ; 3.370 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.307 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.387 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.391 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.245 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; +; 6.368 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; +; 6.368 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; +; 6.368 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #256: Setup slack is -0.772 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.359 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.772 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.361 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.777 ; 83 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.359 ; 3.361 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.621 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.647 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.653 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.252 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.359 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #257: Setup slack is -0.772 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.327 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.772 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.329 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.827 ; 85 ; 0.108 ; 0.944 ; +; Cell ; ; 12 ; 0.380 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.327 ; 3.329 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.298 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; +; 6.327 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; +; 6.327 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; +; 6.327 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #258: Setup slack is -0.772 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.327 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.772 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.329 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.826 ; 85 ; 0.108 ; 0.943 ; +; Cell ; ; 12 ; 0.381 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.327 ; 3.329 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.297 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; +; 6.327 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; +; 6.327 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; +; 6.327 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #259: Setup slack is -0.772 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.359 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.772 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.361 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.894 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.359 ; 3.361 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.333 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; +; 6.359 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; +; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; +; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #260: Setup slack is -0.771 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.358 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.771 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.360 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.777 ; 83 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.358 ; 3.360 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.621 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.647 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.653 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.252 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.358 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #261: Setup slack is -0.771 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.358 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.771 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.360 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.935 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.303 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.358 ; 3.360 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.469 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.497 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.503 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.331 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.358 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; +; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #262: Setup slack is -0.770 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.369 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.770 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.371 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.853 ; 85 ; 0.108 ; 0.787 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.369 ; 3.371 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.980 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 6.008 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 6.014 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.294 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.369 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.369 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.369 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #263: Setup slack is -0.770 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.384 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.770 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.386 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.979 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.384 ; 3.386 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.358 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; +; 6.384 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; +; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; +; 6.384 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #264: Setup slack is -0.770 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.353 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.770 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.355 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.898 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.353 ; 3.355 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.471 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.498 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.504 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.326 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; +; 6.353 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; +; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; +; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #265: Setup slack is -0.770 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.324 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.770 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.326 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.823 ; 85 ; 0.108 ; 0.940 ; +; Cell ; ; 12 ; 0.381 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.324 ; 3.326 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.294 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; +; 6.324 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; +; 6.324 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; +; 6.324 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #266: Setup slack is -0.770 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.357 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.770 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.359 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.913 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.357 ; 3.359 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.331 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; +; 6.357 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; +; 6.357 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; +; 6.357 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #267: Setup slack is -0.770 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.371 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.770 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.373 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.845 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.371 ; 3.373 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.272 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.299 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.305 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.284 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; +; 6.371 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; +; 6.371 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; +; 6.371 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #268: Setup slack is -0.770 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.358 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.770 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.360 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.935 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.303 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.358 ; 3.360 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.469 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.497 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.503 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.331 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.358 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; +; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #269: Setup slack is -0.770 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.318 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.770 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.326 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.700 ; 81 ; 0.138 ; 0.722 ; +; Cell ; ; 14 ; 0.501 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.318 ; 3.326 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.647 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.675 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.679 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.291 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.318 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #270: Setup slack is -0.770 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[2] ; +; To Node ; vx_e_m_reg|csr_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.386 ; +; Data Required Time ; 5.616 ; +; Slack ; -0.770 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.009 ; ; ; ; ; ; +; Data Delay ; 3.397 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.818 ; 83 ; 0.122 ; 0.775 ; +; Cell ; ; 16 ; 0.459 ; 14 ; 0.000 ; 0.081 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]|clk ; +; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2] ; +; 6.386 ; 3.397 ; ; ; ; ; ; data path ; +; 3.109 ; 0.120 ; RR ; uTco ; 1 ; FF_X51_Y153_N52 ; ; vx_csr_handler|decode_csr_address[2]|q ; +; 3.175 ; 0.066 ; RR ; CELL ; 686 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]~la_lab/laboutb[14] ; +; 3.914 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|datae ; +; 3.991 ; 0.077 ; RF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|combout ; +; 3.997 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145~la_mlab/laboutb[9] ; +; 4.438 ; 0.441 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|datac ; +; 4.519 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; +; 4.524 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; +; 4.879 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; +; 4.907 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; +; 4.913 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; +; 5.176 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; +; 5.235 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; +; 5.241 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; +; 5.364 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; +; 5.427 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.431 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.206 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.233 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.238 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.360 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; +; 6.386 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; +; 6.386 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; +; 6.386 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; +; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; +; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.616 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #271: Setup slack is -0.769 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.368 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.769 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.370 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.853 ; 85 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.134 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.368 ; 3.370 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.478 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.509 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.514 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.234 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; +; 6.368 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; +; 6.368 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; +; 6.368 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #272: Setup slack is -0.769 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.353 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.769 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.355 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.884 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.349 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.353 ; 3.355 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.454 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.481 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.485 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.260 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; +; 6.353 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #273: Setup slack is -0.769 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.368 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.769 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.370 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.890 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.368 ; 3.370 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.491 ; 0.573 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.518 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.524 ; 0.006 ; FF ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.341 ; 0.817 ; FF ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; +; 6.368 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; +; 6.368 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; +; 6.368 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #274: Setup slack is -0.768 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.364 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.768 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.366 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.893 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.351 ; 10 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.364 ; 3.366 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.331 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; +; 5.360 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; +; 5.364 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; +; 6.272 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; +; 6.364 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.364 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.364 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #275: Setup slack is -0.768 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.369 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.768 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.371 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.864 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.386 ; 11 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.369 ; 3.371 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.270 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.297 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.303 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.282 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; +; 6.369 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; +; 6.369 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; +; 6.369 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #276: Setup slack is -0.767 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.367 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.767 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.369 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.962 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.367 ; 3.369 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.340 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.367 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; +; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #277: Setup slack is -0.767 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.359 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.767 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.361 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.845 ; 85 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.359 ; 3.361 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.280 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; +; 6.359 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; +; 6.359 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; +; 6.359 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #278: Setup slack is -0.767 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.340 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.767 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.342 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.934 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.340 ; 3.342 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.321 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.348 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.352 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.313 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.340 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #279: Setup slack is -0.767 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|PC_next_out[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.182 ; +; Data Required Time ; 5.415 ; +; Slack ; -0.767 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.184 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.712 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.182 ; 3.184 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.182 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; +; 6.182 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.415 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #280: Setup slack is -0.767 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.369 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.767 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.371 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.892 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.369 ; 3.371 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.546 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.572 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.578 ; 0.006 ; FF ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.342 ; 0.764 ; FF ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; +; 6.369 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; +; 6.369 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; +; 6.369 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #281: Setup slack is -0.766 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.314 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.766 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.316 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.861 ; 86 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.333 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.314 ; 3.316 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.643 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.671 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.675 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.287 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.314 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #282: Setup slack is -0.766 (VIOLATED) +=============================================================================== ++--------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.367 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.766 (VIOLATED) ; ++--------------------+-----------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.369 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.962 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.367 ; 3.369 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.340 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.367 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; +; 6.367 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #283: Setup slack is -0.766 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.340 ; +; Data Required Time ; 5.574 ; +; Slack ; -0.766 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.342 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.934 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.340 ; 3.342 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.321 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.348 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.352 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.313 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.340 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #284: Setup slack is -0.766 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|PC_next_out[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.182 ; +; Data Required Time ; 5.416 ; +; Slack ; -0.766 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.184 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.712 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.182 ; 3.184 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.182 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; +; 6.182 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.416 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #285: Setup slack is -0.765 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.352 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.765 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.354 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.806 ; 84 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.428 ; 13 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.352 ; 3.354 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.614 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.640 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.646 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.245 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.352 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #286: Setup slack is -0.765 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_address[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.316 ; +; Data Required Time ; 5.551 ; +; Slack ; -0.765 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.318 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.818 ; 85 ; 0.108 ; 0.935 ; +; Cell ; ; 12 ; 0.378 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.316 ; 3.318 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.288 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; +; 6.316 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; +; 6.316 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; +; 6.316 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #287: Setup slack is -0.765 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.358 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.765 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.360 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.896 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.358 ; 3.360 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.332 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.358 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; +; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #288: Setup slack is -0.765 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.352 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.765 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.354 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.919 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.314 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.352 ; 3.354 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.463 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.491 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.497 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.325 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.352 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; +; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #289: Setup slack is -0.765 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.375 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.765 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.377 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.987 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.270 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.375 ; 3.377 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.567 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.349 ; 0.782 ; RR ; IC ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|dataf ; +; 6.375 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~796|combout ; +; 6.375 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|d ; +; 6.375 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #290: Setup slack is -0.765 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.318 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.765 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.077 ; ; ; ; ; ; +; Data Delay ; 3.320 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.822 ; 85 ; 0.108 ; 0.876 ; +; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.318 ; 3.320 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.291 ; 0.876 ; FF ; IC ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|dataf ; +; 6.318 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|combout ; +; 6.318 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|d ; +; 6.318 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|clk ; +; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; +; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.162 ; ; uTsu ; 1 ; FF_X80_Y149_N44 ; ; vx_d_e_reg|b_reg_data[25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #291: Setup slack is -0.765 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[2] ; +; To Node ; vx_e_m_reg|alu_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.378 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.765 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.009 ; ; ; ; ; ; +; Data Delay ; 3.389 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.810 ; 83 ; 0.114 ; 0.775 ; +; Cell ; ; 16 ; 0.459 ; 14 ; 0.000 ; 0.081 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]|clk ; +; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2] ; +; 6.378 ; 3.389 ; ; ; ; ; ; data path ; +; 3.109 ; 0.120 ; RR ; uTco ; 1 ; FF_X51_Y153_N52 ; ; vx_csr_handler|decode_csr_address[2]|q ; +; 3.175 ; 0.066 ; RR ; CELL ; 686 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]~la_lab/laboutb[14] ; +; 3.914 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|datae ; +; 3.991 ; 0.077 ; RF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|combout ; +; 3.997 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145~la_mlab/laboutb[9] ; +; 4.438 ; 0.441 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|datac ; +; 4.519 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; +; 4.524 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; +; 4.879 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; +; 4.907 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; +; 4.913 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; +; 5.176 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; +; 5.235 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; +; 5.241 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; +; 5.364 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; +; 5.427 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.431 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.206 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.233 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.238 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.352 ; 0.114 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; +; 6.378 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; +; 6.378 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; +; 6.378 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; +; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; +; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.163 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #292: Setup slack is -0.764 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.351 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.764 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.353 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.806 ; 84 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.427 ; 13 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.351 ; 3.353 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.614 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.640 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.646 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.245 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.351 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.351 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.351 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #293: Setup slack is -0.764 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.358 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.764 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.360 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.896 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.358 ; 3.360 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.332 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.358 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; +; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #294: Setup slack is -0.764 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.352 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.764 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.354 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.919 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.314 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.352 ; 3.354 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.463 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.491 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.497 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.325 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.352 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; +; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #295: Setup slack is -0.764 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.347 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.764 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.349 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.889 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.347 ; 3.349 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.511 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.538 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.544 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.320 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; +; 6.347 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; +; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; +; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #296: Setup slack is -0.764 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.370 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.764 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.372 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.370 ; 3.372 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.128 ; 0.713 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|dataf ; +; 6.158 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|combout ; +; 6.164 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35~la_mlab/laboutt[9] ; +; 6.294 ; 0.130 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|datae ; +; 6.370 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; +; 6.370 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; +; 6.370 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #297: Setup slack is -0.763 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.364 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.763 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.366 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.853 ; 85 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.364 ; 3.366 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.478 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.509 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.514 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.234 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; +; 6.364 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; +; 6.364 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; +; 6.364 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #298: Setup slack is -0.763 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.346 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.763 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.348 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.941 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.346 ; 3.348 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.535 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.562 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.567 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.318 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; +; 6.346 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; +; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; +; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #299: Setup slack is -0.763 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_address[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.512 ; +; Slack ; -0.763 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.121 ; ; ; ; ; ; +; Data Delay ; 3.277 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.746 ; 84 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.410 ; 13 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.275 ; 3.277 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.419 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.202 ; 0.783 ; RR ; IC ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|datae ; +; 6.275 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|combout ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|d ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.377 ; 2.877 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; +; 5.377 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.347 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.512 ; 0.165 ; ; uTsu ; 1 ; FF_X49_Y149_N28 ; ; vx_d_e_reg|csr_address[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #300: Setup slack is -0.763 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.335 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.763 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.337 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.826 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.335 ; 3.337 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.494 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.308 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; +; 6.335 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #301: Setup slack is -0.762 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.376 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.762 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.378 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.921 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.376 ; 3.378 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.350 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; +; 6.376 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; +; 6.376 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; +; 6.376 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #302: Setup slack is -0.762 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.361 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.762 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.363 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.896 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.361 ; 3.363 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.335 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; +; 6.361 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; +; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; +; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #303: Setup slack is -0.762 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.335 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.762 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.337 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.915 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.300 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.335 ; 3.337 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.316 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.343 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.347 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.308 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.335 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #304: Setup slack is -0.762 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.357 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.762 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.359 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.825 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.413 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.357 ; 3.359 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.501 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.530 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.535 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.277 ; 0.742 ; FF ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; +; 6.357 ; 0.080 ; FF ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; +; 6.357 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; +; 6.357 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #305: Setup slack is -0.761 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.360 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.761 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.362 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.795 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.445 ; 13 ; 0.000 ; 0.134 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.360 ; 3.362 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.470 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.501 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.506 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.226 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; +; 6.360 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; +; 6.360 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; +; 6.360 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #306: Setup slack is -0.761 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.345 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.761 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.347 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.826 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.345 ; 3.347 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.446 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.473 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.477 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.252 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; +; 6.345 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; +; 6.345 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; +; 6.345 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #307: Setup slack is -0.761 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.335 ; +; Data Required Time ; 5.574 ; +; Slack ; -0.761 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.337 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.915 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.300 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.335 ; 3.337 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.316 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.343 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.347 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.308 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.335 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #308: Setup slack is -0.761 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.360 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.761 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.362 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.845 ; 85 ; 0.106 ; 1.302 ; +; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.360 ; 3.362 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.243 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; +; 6.360 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; +; 6.360 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; +; 6.360 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #309: Setup slack is -0.761 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.339 ; +; Data Required Time ; 5.578 ; +; Slack ; -0.761 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.341 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.881 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.339 ; 3.341 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.312 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; +; 6.339 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; +; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; +; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #310: Setup slack is -0.761 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.352 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.761 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.354 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.893 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.352 ; 3.354 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.325 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; +; 6.352 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; +; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; +; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #311: Setup slack is -0.761 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[25] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.389 ; +; Data Required Time ; 5.628 ; +; Slack ; -0.761 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.113 ; ; ; ; ; ; +; Data Delay ; 2.317 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.996 ; 86 ; 0.421 ; 0.887 ; +; Cell ; ; 8 ; 0.188 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|clk ; +; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; +; 6.389 ; 2.317 ; ; ; ; ; ; data path ; +; 4.205 ; 0.133 ; FF ; uTco ; 1 ; FF_X108_Y149_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|q ; +; 4.249 ; 0.044 ; FF ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]~la_lab/laboutb[6] ; +; 4.937 ; 0.688 ; FF ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|datae ; +; 5.021 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; +; 5.025 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; +; 5.912 ; 0.887 ; FF ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; +; 5.937 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; +; 5.942 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; +; 6.363 ; 0.421 ; FF ; IC ; 1 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|dataf ; +; 6.389 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|combout ; +; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]|d ; +; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25] ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]|clk ; +; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25] ; +; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.628 ; 0.199 ; ; uTsu ; 1 ; FF_X75_Y158_N38 ; ; vx_fetch|VX_Warp_three|real_PC[25] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #312: Setup slack is -0.760 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.356 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.760 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.358 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.835 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.356 ; 3.358 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.323 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; +; 5.352 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; +; 5.356 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; +; 6.264 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; +; 6.356 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.356 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.356 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #313: Setup slack is -0.760 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_address[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.310 ; +; Data Required Time ; 5.550 ; +; Slack ; -0.760 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.312 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.813 ; 85 ; 0.108 ; 0.930 ; +; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.310 ; 3.312 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.283 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; +; 6.310 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #314: Setup slack is -0.760 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.360 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.760 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.362 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.830 ; 84 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.410 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.360 ; 3.362 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.504 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.530 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.536 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.267 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; +; 6.360 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; +; 6.360 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; +; 6.360 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #315: Setup slack is -0.760 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.359 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.760 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.361 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.915 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.359 ; 3.361 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.333 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; +; 6.359 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; +; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; +; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #316: Setup slack is -0.760 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.353 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.760 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.355 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.908 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.353 ; 3.355 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.271 ; 0.703 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|datac ; +; 6.353 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~794|combout ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|d ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.168 ; ; uTsu ; 1 ; FF_X95_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #317: Setup slack is -0.760 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.389 ; +; Data Required Time ; 5.629 ; +; Slack ; -0.760 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.113 ; ; ; ; ; ; +; Data Delay ; 2.317 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.996 ; 86 ; 0.421 ; 0.887 ; +; Cell ; ; 8 ; 0.188 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|clk ; +; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; +; 6.389 ; 2.317 ; ; ; ; ; ; data path ; +; 4.205 ; 0.133 ; FF ; uTco ; 1 ; FF_X108_Y149_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|q ; +; 4.249 ; 0.044 ; FF ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]~la_lab/laboutb[6] ; +; 4.937 ; 0.688 ; FF ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|datae ; +; 5.021 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; +; 5.025 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; +; 5.912 ; 0.887 ; FF ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; +; 5.937 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; +; 5.942 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; +; 6.363 ; 0.421 ; FF ; IC ; 1 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|dataf ; +; 6.389 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|combout ; +; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE|d ; +; 6.389 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE|clk ; +; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; +; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X75_Y158_N37 ; ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #318: Setup slack is -0.759 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.344 ; +; Data Required Time ; 5.585 ; +; Slack ; -0.759 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.346 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.875 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.349 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.344 ; 3.346 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.454 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.481 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.485 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.251 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; +; 6.344 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; +; 6.344 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; +; 6.344 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #319: Setup slack is -0.759 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.359 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.759 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.361 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.904 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.359 ; 3.361 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.557 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.332 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.359 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; +; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #320: Setup slack is -0.759 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.353 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.759 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.355 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.886 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.353 ; 3.355 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.325 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; +; 6.353 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; +; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; +; 6.353 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #321: Setup slack is -0.759 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.346 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.759 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.348 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.884 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.346 ; 3.348 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.320 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; +; 6.346 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; +; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; +; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #322: Setup slack is -0.759 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.353 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.759 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.355 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.841 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.353 ; 3.355 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.546 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.271 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; +; 6.353 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #323: Setup slack is -0.759 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.372 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.759 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.374 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.852 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.372 ; 3.374 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.545 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.285 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; +; 6.372 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; +; 6.372 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; +; 6.372 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #324: Setup slack is -0.759 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.355 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.759 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.357 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.877 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.355 ; 3.357 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.491 ; 0.573 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.518 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.524 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.328 ; 0.804 ; FF ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; +; 6.355 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; +; 6.355 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; +; 6.355 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #325: Setup slack is -0.758 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.758 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.700 ; 82 ; 0.192 ; 0.657 ; +; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; +; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.612 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.640 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.644 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.278 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.306 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #326: Setup slack is -0.758 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.307 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.758 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.309 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.701 ; 82 ; 0.192 ; 0.657 ; +; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.307 ; 3.309 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; +; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.612 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.640 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.644 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.279 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.307 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #327: Setup slack is -0.758 (VIOLATED) +=============================================================================== ++--------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.359 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.758 (VIOLATED) ; ++--------------------+-----------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.361 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.904 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.359 ; 3.361 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.557 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.332 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.359 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; +; 6.359 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #328: Setup slack is -0.758 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.312 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.758 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.314 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.812 ; 85 ; 0.108 ; 0.929 ; +; Cell ; ; 12 ; 0.380 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.312 ; 3.314 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.283 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; +; 6.312 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; +; 6.312 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; +; 6.312 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #329: Setup slack is -0.758 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.358 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.758 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.360 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.849 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.358 ; 3.360 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.502 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.528 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.534 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.265 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; +; 6.358 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; +; 6.358 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; +; 6.358 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #330: Setup slack is -0.758 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.219 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.758 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.221 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.219 ; 3.221 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|sload ; +; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N10 ; ; vx_fetch|VX_Warp_zero|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #331: Setup slack is -0.758 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.219 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.758 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.221 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.219 ; 3.221 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|sload ; +; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N4 ; ; vx_fetch|VX_Warp_zero|real_PC[14] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #332: Setup slack is -0.758 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.348 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.758 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.350 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.889 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.348 ; 3.350 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.321 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; +; 6.348 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; +; 6.348 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; +; 6.348 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #333: Setup slack is -0.758 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_csr_handler|decode_csr_address[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.498 ; +; Slack ; -0.758 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.141 ; ; ; ; ; ; +; Data Delay ; 3.264 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 4 ; 2.872 ; 88 ; 0.666 ; 0.817 ; +; Cell ; ; 8 ; 0.267 ; 8 ; 0.000 ; 0.112 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.158 ; 79 ; 0.000 ; 2.158 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.256 ; 3.264 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.868 ; 0.666 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|dataa ; +; 3.980 ; 0.112 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; +; 3.986 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; +; 4.663 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; +; 4.690 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; +; 4.694 ; 0.004 ; RR ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; +; 5.406 ; 0.712 ; RR ; IC ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|dataf ; +; 5.434 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|combout ; +; 5.439 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4~la_lab/laboutb[19] ; +; 6.256 ; 0.817 ; FF ; IC ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4]|d ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.351 ; 2.851 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.223 ; 2.158 ; RR ; IC ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4]|clk ; +; 5.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4] ; +; 5.351 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.321 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.498 ; 0.177 ; ; uTsu ; 1 ; FF_X38_Y157_N17 ; ; vx_csr_handler|decode_csr_address[4] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #334: Setup slack is -0.757 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.757 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.698 ; 82 ; 0.192 ; 0.657 ; +; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; +; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.612 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.640 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.644 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.276 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.304 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #335: Setup slack is -0.757 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.757 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.792 ; 84 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.611 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.639 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.643 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.278 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.306 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #336: Setup slack is -0.757 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.305 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.757 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.307 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 84 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.305 ; 3.307 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.611 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.639 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.643 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.277 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.305 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #337: Setup slack is -0.757 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.351 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.757 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.353 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.905 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.351 ; 3.353 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.323 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; +; 6.351 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; +; 6.351 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; +; 6.351 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #338: Setup slack is -0.757 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.358 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.757 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.360 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.835 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.358 ; 3.360 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.259 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.286 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.292 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.271 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; +; 6.358 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; +; 6.358 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; +; 6.358 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #339: Setup slack is -0.757 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.219 ; +; Data Required Time ; 5.462 ; +; Slack ; -0.757 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.221 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.219 ; 3.221 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|sload ; +; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N14 ; ; vx_fetch|VX_Warp_zero|real_PC[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #340: Setup slack is -0.757 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.219 ; +; Data Required Time ; 5.462 ; +; Slack ; -0.757 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.221 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.219 ; 3.221 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|sload ; +; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N5 ; ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #341: Setup slack is -0.756 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.303 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.756 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.305 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 84 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.303 ; 3.305 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.611 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.639 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.643 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.275 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.303 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #342: Setup slack is -0.756 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.340 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.756 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.342 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.934 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.340 ; 3.342 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.312 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; +; 6.340 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #343: Setup slack is -0.756 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.329 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.756 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.331 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.899 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.311 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.329 ; 3.331 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.310 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.337 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.341 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.302 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.329 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #344: Setup slack is -0.756 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.337 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.756 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.339 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.879 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.337 ; 3.339 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.511 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.538 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.544 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.310 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; +; 6.337 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; +; 6.337 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; +; 6.337 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #345: Setup slack is -0.756 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.362 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.756 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.364 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.845 ; 85 ; 0.106 ; 1.302 ; +; Cell ; ; 12 ; 0.398 ; 12 ; 0.000 ; 0.119 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.362 ; 3.364 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.243 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; +; 6.362 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; +; 6.362 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; +; 6.362 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #346: Setup slack is -0.756 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[16] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.307 ; +; Data Required Time ; 5.551 ; +; Slack ; -0.756 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.078 ; ; ; ; ; ; +; Data Delay ; 3.309 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.710 ; 82 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.478 ; 14 ; 0.000 ; 0.128 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.307 ; 3.309 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.179 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|datab ; +; 6.307 ; 0.128 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|combout ; +; 6.307 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|d ; +; 6.307 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|clk ; +; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; +; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.551 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y152_N32 ; ; vx_d_e_reg|b_reg_data[16] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #347: Setup slack is -0.755 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.357 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.755 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.359 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.839 ; 85 ; 0.108 ; 0.787 ; +; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.357 ; 3.359 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.986 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 6.016 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 6.022 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.282 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.357 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.357 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.357 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #348: Setup slack is -0.755 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.356 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.755 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.358 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.795 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.441 ; 13 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.356 ; 3.358 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.470 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.501 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.506 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.226 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; +; 6.356 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; +; 6.356 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; +; 6.356 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #349: Setup slack is -0.755 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.338 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.755 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.340 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.883 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.338 ; 3.340 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.527 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.554 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.559 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.310 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; +; 6.338 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; +; 6.338 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; +; 6.338 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #350: Setup slack is -0.755 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.341 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.755 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.343 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.877 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.341 ; 3.343 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.447 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.474 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.480 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.315 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; +; 6.341 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; +; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; +; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #351: Setup slack is -0.755 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.329 ; +; Data Required Time ; 5.574 ; +; Slack ; -0.755 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.331 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.899 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.311 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.329 ; 3.331 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.310 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.337 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.341 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.302 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.329 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #352: Setup slack is -0.755 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[16] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.219 ; +; Data Required Time ; 5.464 ; +; Slack ; -0.755 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.221 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.219 ; 3.221 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|sload ; +; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N32 ; ; vx_fetch|VX_Warp_zero|real_PC[16] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #353: Setup slack is -0.755 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.219 ; +; Data Required Time ; 5.464 ; +; Slack ; -0.755 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.221 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.219 ; 3.221 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|sload ; +; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N44 ; ; vx_fetch|VX_Warp_zero|real_PC[17] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #354: Setup slack is -0.755 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.219 ; +; Data Required Time ; 5.464 ; +; Slack ; -0.755 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.221 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.717 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.219 ; 3.221 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.219 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|sload ; +; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[20] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #355: Setup slack is -0.754 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.360 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.754 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.362 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.793 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.448 ; 13 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.360 ; 3.362 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.080 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.107 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.113 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.284 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.360 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.360 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; +; 6.360 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #356: Setup slack is -0.754 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.360 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.754 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.362 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.893 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.360 ; 3.362 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.332 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; +; 6.360 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; +; 6.360 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; +; 6.360 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #357: Setup slack is -0.754 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.346 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.754 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.348 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.886 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.079 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.346 ; 3.348 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.610 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.267 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; +; 6.346 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; +; 6.346 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; +; 6.346 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #358: Setup slack is -0.754 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.341 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.754 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.343 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.952 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.341 ; 3.343 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.381 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.408 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.413 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.313 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.341 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|d ; +; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #359: Setup slack is -0.754 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.341 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.754 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.343 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.952 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.341 ; 3.343 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.381 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.408 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.413 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.313 ; 0.900 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|dataf ; +; 6.341 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~860|combout ; +; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|d ; +; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N47 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N47 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #360: Setup slack is -0.754 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.353 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.754 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.355 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.680 ; 80 ; 0.192 ; 0.681 ; +; Cell ; ; 14 ; 0.554 ; 17 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.353 ; 3.355 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.970 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.996 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 6.002 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.280 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.353 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #361: Setup slack is -0.754 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.353 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.754 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.355 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.830 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.353 ; 3.355 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.481 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.508 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.513 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.261 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.353 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #362: Setup slack is -0.753 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.339 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.753 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.341 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.896 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.324 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.339 ; 3.341 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.445 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.478 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.313 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; +; 6.339 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; +; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; +; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #363: Setup slack is -0.753 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.166 ; +; Data Required Time ; 5.413 ; +; Slack ; -0.753 (VIOLATED) ; ++--------------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.141 ; ; ; ; ; ; +; Data Delay ; 3.174 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 4 ; 2.836 ; 89 ; 0.630 ; 0.817 ; +; Cell ; ; 8 ; 0.211 ; 7 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.158 ; 79 ; 0.000 ; 2.158 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.166 ; 3.174 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.810 ; 0.630 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|datad ; +; 3.890 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; +; 3.896 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; +; 4.573 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; +; 4.600 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; +; 4.604 ; 0.004 ; RR ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; +; 5.316 ; 0.712 ; RR ; IC ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|dataf ; +; 5.344 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|combout ; +; 5.349 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4~la_lab/laboutb[19] ; +; 6.166 ; 0.817 ; FF ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|d ; +; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.351 ; 2.851 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.223 ; 2.158 ; RR ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|clk ; +; 5.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; +; 5.351 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.321 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.413 ; 0.092 ; ; uTsu ; 1 ; FF_X38_Y157_N16 ; ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #364: Setup slack is -0.753 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.352 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.753 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.360 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.695 ; 80 ; 0.192 ; 0.682 ; +; Cell ; ; 14 ; 0.538 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.352 ; 3.360 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.969 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.995 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 6.001 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.279 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.352 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.352 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.352 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #365: Setup slack is -0.753 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.365 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.753 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.367 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.907 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.365 ; 3.367 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.339 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; +; 6.365 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; +; 6.365 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; +; 6.365 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #366: Setup slack is -0.753 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.305 ; +; Data Required Time ; 5.552 ; +; Slack ; -0.753 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.078 ; ; ; ; ; ; +; Data Delay ; 3.307 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.710 ; 82 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.476 ; 14 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.305 ; 3.307 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.179 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|datab ; +; 6.305 ; 0.126 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|combout ; +; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|d ; +; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|clk ; +; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; +; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.552 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y152_N34 ; ; vx_d_e_reg|b_reg_data[17] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #367: Setup slack is -0.752 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.361 ; +; Data Required Time ; 5.609 ; +; Slack ; -0.752 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.363 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.780 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.361 ; 3.363 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.122 ; 0.769 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; +; 6.151 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; +; 6.157 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; +; 6.285 ; 0.128 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; +; 6.361 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; +; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; +; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #368: Setup slack is -0.752 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.360 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.752 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.362 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.793 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.448 ; 13 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.360 ; 3.362 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.080 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.107 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.113 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.284 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.360 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.360 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; +; 6.360 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #369: Setup slack is -0.752 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.358 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.752 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.360 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.912 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.358 ; 3.360 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.330 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; +; 6.358 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; +; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; +; 6.358 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #370: Setup slack is -0.752 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.345 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.752 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.347 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.937 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.345 ; 3.347 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.319 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.345 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; +; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #371: Setup slack is -0.752 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.222 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.752 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.224 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.827 ; 88 ; 0.119 ; 1.398 ; +; Cell ; ; 10 ; 0.275 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.222 ; 3.224 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.457 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.791 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.819 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.824 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.222 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #372: Setup slack is -0.752 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.351 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.752 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.359 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.706 ; 81 ; 0.142 ; 0.710 ; +; Cell ; ; 14 ; 0.528 ; 16 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.351 ; 3.359 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.254 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.962 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.990 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.996 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.276 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.351 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.351 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.351 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #373: Setup slack is -0.752 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.353 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.752 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.355 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.830 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.353 ; 3.355 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.481 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.508 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.513 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.261 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.353 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; +; 6.353 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #374: Setup slack is -0.751 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.361 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.751 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.363 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.780 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.361 ; 3.363 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.112 ; 0.759 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; +; 6.139 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; +; 6.145 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; +; 6.283 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; +; 6.361 ; 0.078 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; +; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; +; 6.361 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #375: Setup slack is -0.751 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.336 ; +; Data Required Time ; 5.585 ; +; Slack ; -0.751 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.338 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.817 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.336 ; 3.338 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.446 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.473 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.477 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.243 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; +; 6.336 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; +; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; +; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #376: Setup slack is -0.751 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.345 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.751 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.347 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.937 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.345 ; 3.347 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.319 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.345 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; +; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #377: Setup slack is -0.751 (VIOLATED) +=============================================================================== ++-----------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------+ +; Property ; Value ; ++--------------------+--------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[1] ; +; To Node ; vx_e_m_reg|alu_result[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.751 (VIOLATED) ; ++--------------------+--------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.079 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.317 ; 79 ; 0.000 ; 2.317 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.678 ; 81 ; 0.127 ; 0.747 ; +; Cell ; ; 16 ; 0.447 ; 14 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.183 ; 6 ; 0.183 ; 0.183 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.944 ; 2.944 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.944 ; 2.317 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; +; 2.944 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; +; 6.252 ; 3.308 ; ; ; ; ; ; data path ; +; 3.127 ; 0.183 ; FF ; uTco ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1]|q ; +; 3.195 ; 0.068 ; FF ; CELL ; 4 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]~la_lab/laboutt[4] ; +; 3.820 ; 0.625 ; FF ; IC ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|dataf ; +; 3.848 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|combout ; +; 3.852 ; 0.004 ; FF ; CELL ; 71 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22~la_lab/laboutb[2] ; +; 4.224 ; 0.372 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|datac ; +; 4.316 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|combout ; +; 4.321 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28~la_mlab/laboutt[2] ; +; 4.448 ; 0.127 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; +; 4.742 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; +; 4.817 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.821 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.254 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.281 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.287 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.444 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; +; 5.472 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; +; 5.477 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; +; 6.224 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; +; 6.252 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #378: Setup slack is -0.750 (VIOLATED) +=============================================================================== ++----------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------+ +; Property ; Value ; ++--------------------+-------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.336 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.750 (VIOLATED) ; ++--------------------+-------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.338 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.696 ; 81 ; 0.192 ; 0.712 ; +; Cell ; ; 14 ; 0.520 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.336 ; 3.338 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; +; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.530 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.556 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.562 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.274 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.336 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #379: Setup slack is -0.750 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.346 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.750 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.348 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.840 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.346 ; 3.348 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.470 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.547 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.551 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.319 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; +; 6.346 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; +; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; +; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #380: Setup slack is -0.749 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.335 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.749 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.337 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.787 ; 84 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.428 ; 13 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.335 ; 3.337 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.529 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.555 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.561 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.273 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.335 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #381: Setup slack is -0.749 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.349 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.749 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.351 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.887 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.349 ; 3.351 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.266 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; +; 6.349 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; +; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; +; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #382: Setup slack is -0.749 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.348 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.749 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.350 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.886 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.348 ; 3.350 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.322 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; +; 6.348 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; +; 6.348 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; +; 6.348 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #383: Setup slack is -0.749 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.341 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.749 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.343 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.867 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.354 ; 11 ; 0.000 ; 0.079 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.341 ; 3.343 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.605 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.262 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; +; 6.341 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; +; 6.341 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; +; 6.341 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #384: Setup slack is -0.748 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.332 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.748 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.334 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.876 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.332 ; 3.334 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.557 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.304 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; +; 6.332 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; +; 6.332 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; +; 6.332 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #385: Setup slack is -0.748 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.350 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.748 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.352 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.674 ; 80 ; 0.192 ; 0.690 ; +; Cell ; ; 14 ; 0.557 ; 17 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.350 ; 3.352 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.979 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 6.008 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 6.014 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.277 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.350 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.350 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.350 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #386: Setup slack is -0.748 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[22] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.377 ; +; Data Required Time ; 5.629 ; +; Slack ; -0.748 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.098 ; ; ; ; ; ; +; Data Delay ; 2.320 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.314 ; 76 ; 0.000 ; 2.314 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.939 ; 84 ; 0.403 ; 0.872 ; +; Cell ; ; 8 ; 0.241 ; 10 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.140 ; 6 ; 0.140 ; 0.140 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.057 ; 3.057 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.057 ; 2.314 ; FF ; IC ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]|clk ; +; 4.057 ; 0.000 ; FR ; CELL ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; +; 6.377 ; 2.320 ; ; ; ; ; ; data path ; +; 4.197 ; 0.140 ; FF ; uTco ; 1 ; FF_X92_Y141_N41 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]|q ; +; 4.266 ; 0.069 ; FF ; CELL ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[7] ; +; 5.138 ; 0.872 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|datad ; +; 5.212 ; 0.074 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; +; 5.218 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; +; 5.882 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; +; 5.910 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; +; 5.915 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[12] ; +; 6.318 ; 0.403 ; FF ; IC ; 1 ; MLABCELL_X76_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~19|datae ; +; 6.377 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X76_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~19|combout ; +; 6.377 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22]|d ; +; 6.377 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22]|clk ; +; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22] ; +; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X76_Y158_N14 ; ; vx_fetch|VX_Warp_three|real_PC[22] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #387: Setup slack is -0.748 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.329 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.748 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.331 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.853 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.357 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.329 ; 3.331 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.493 ; 0.005 ; FF ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.302 ; 0.809 ; FF ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; +; 6.329 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #388: Setup slack is -0.747 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.347 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.747 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.349 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.820 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.408 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.347 ; 3.349 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.491 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.517 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.523 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.254 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; +; 6.347 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; +; 6.347 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; +; 6.347 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #389: Setup slack is -0.747 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.340 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.747 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.342 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.918 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.340 ; 3.342 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.314 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.340 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #390: Setup slack is -0.747 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.349 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.747 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.357 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.689 ; 80 ; 0.192 ; 0.690 ; +; Cell ; ; 14 ; 0.541 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.349 ; 3.357 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.978 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 6.007 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 6.013 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.276 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.349 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #391: Setup slack is -0.746 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_mask[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.334 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.746 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.336 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.820 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.334 ; 3.336 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.647 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.673 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.679 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.306 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; +; 6.334 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #392: Setup slack is -0.746 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_mask[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.334 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.746 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.336 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.820 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.334 ; 3.336 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.363 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.647 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.673 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.679 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.306 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; +; 6.334 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #393: Setup slack is -0.746 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.329 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.746 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.331 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.864 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.329 ; 3.331 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.447 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.474 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.480 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.302 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; +; 6.329 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #394: Setup slack is -0.746 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.340 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.746 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.342 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.876 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.340 ; 3.342 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.312 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; +; 6.340 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #395: Setup slack is -0.746 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.333 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.746 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.335 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.925 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.333 ; 3.335 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.307 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; +; 6.333 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #396: Setup slack is -0.746 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.340 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.746 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.342 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.918 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.340 ; 3.342 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.314 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.340 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #397: Setup slack is -0.746 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.350 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.746 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.352 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.831 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.350 ; 3.352 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.377 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; +; 5.407 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; +; 5.411 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; +; 6.264 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; +; 6.350 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; +; 6.350 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; +; 6.350 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #398: Setup slack is -0.745 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.745 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.697 ; 82 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.477 ; 14 ; 0.000 ; 0.127 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.166 ; 0.751 ; FF ; IC ; 1 ; LABCELL_X79_Y151_N6 ; High Speed ; vx_d_e_reg|i385~6|dataa ; +; 6.293 ; 0.127 ; FR ; CELL ; 1 ; LABCELL_X79_Y151_N6 ; High Speed ; vx_d_e_reg|i385~6|combout ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|d ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #399: Setup slack is -0.744 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.744 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.782 ; 84 ; 0.110 ; 0.788 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.598 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.626 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.630 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.265 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.293 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #400: Setup slack is -0.744 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.292 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.744 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.294 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.781 ; 84 ; 0.110 ; 0.788 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.292 ; 3.294 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.598 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.626 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.630 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.264 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.292 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #401: Setup slack is -0.744 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.327 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.744 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.329 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.883 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.327 ; 3.329 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.445 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.478 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.300 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; +; 6.327 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; +; 6.327 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; +; 6.327 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #402: Setup slack is -0.744 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|b_reg_data[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.299 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.744 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.301 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.811 ; 85 ; 0.108 ; 0.944 ; +; Cell ; ; 12 ; 0.369 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.299 ; 3.301 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.270 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; +; 6.299 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; +; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; +; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #403: Setup slack is -0.744 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|b_reg_data[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.299 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.744 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.301 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.810 ; 85 ; 0.108 ; 0.943 ; +; Cell ; ; 12 ; 0.370 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.299 ; 3.301 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.269 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; +; 6.299 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; +; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; +; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #404: Setup slack is -0.744 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.345 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.744 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.347 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.876 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.351 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.345 ; 3.347 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.246 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.273 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.279 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.258 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; +; 6.345 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; +; 6.345 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; +; 6.345 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #405: Setup slack is -0.744 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.350 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.744 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.352 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.873 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.350 ; 3.352 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.323 ; 0.800 ; FF ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; +; 6.350 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; +; 6.350 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; +; 6.350 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #406: Setup slack is -0.743 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.330 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.743 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.332 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.770 ; 83 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.440 ; 13 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.330 ; 3.332 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.592 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.618 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.624 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.223 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.330 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.330 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.330 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #407: Setup slack is -0.743 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.290 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.743 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.292 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.779 ; 84 ; 0.110 ; 0.788 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.290 ; 3.292 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.598 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.626 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.630 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.262 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.290 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #408: Setup slack is -0.743 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.336 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.743 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.338 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.929 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.336 ; 3.338 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.309 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; +; 6.336 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; +; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; +; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #409: Setup slack is -0.743 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.335 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.743 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.337 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.851 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.365 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.335 ; 3.337 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.599 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.256 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; +; 6.335 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; +; 6.335 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; +; 6.335 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #410: Setup slack is -0.743 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.338 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.743 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.340 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.800 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.420 ; 13 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.338 ; 3.340 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.275 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.355 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.359 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.213 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|datab ; +; 6.338 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~840|combout ; +; 6.338 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|d ; +; 6.338 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #411: Setup slack is -0.742 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.329 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.742 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.331 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.770 ; 83 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.439 ; 13 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.329 ; 3.331 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.592 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.618 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.624 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.223 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.329 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #412: Setup slack is -0.742 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.328 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.742 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.330 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.867 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.328 ; 3.330 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.434 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.467 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.302 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; +; 6.328 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; +; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; +; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #413: Setup slack is -0.742 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|b_reg_data[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.296 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.742 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.298 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.807 ; 85 ; 0.108 ; 0.940 ; +; Cell ; ; 12 ; 0.370 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.296 ; 3.298 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.266 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; +; 6.296 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #414: Setup slack is -0.742 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_f_d_reg|curr_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.207 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.742 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.209 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.752 ; 86 ; 0.119 ; 1.297 ; +; Cell ; ; 10 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.207 ; 3.209 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.877 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.905 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.910 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.207 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|ena ; +; 6.207 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N32 ; ; vx_f_d_reg|curr_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #415: Setup slack is -0.742 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_f_d_reg|curr_PC[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.207 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.742 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.209 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.752 ; 86 ; 0.119 ; 1.297 ; +; Cell ; ; 10 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.207 ; 3.209 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.877 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.905 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.910 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.207 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|ena ; +; 6.207 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N38 ; ; vx_f_d_reg|curr_PC[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #416: Setup slack is -0.742 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.336 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.742 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.338 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.908 ; 87 ; 0.106 ; 1.378 ; +; Cell ; ; 12 ; 0.309 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.336 ; 3.338 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.306 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.336 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; +; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #417: Setup slack is -0.742 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.323 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.742 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.325 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.812 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.323 ; 3.325 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.437 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; +; 5.517 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; +; 5.522 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; +; 6.295 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; +; 6.323 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; +; 6.323 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; +; 6.323 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #418: Setup slack is -0.742 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.347 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.742 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.349 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.889 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.347 ; 3.349 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.320 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; +; 6.347 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; +; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; +; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #419: Setup slack is -0.741 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.341 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.741 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.343 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.829 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.341 ; 3.343 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.258 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; +; 6.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; +; 6.341 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; +; 6.341 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #420: Setup slack is -0.741 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.347 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.741 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.349 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.883 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.347 ; 3.349 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.319 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; +; 6.347 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; +; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; +; 6.347 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #421: Setup slack is -0.741 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.334 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.741 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.336 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.902 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.334 ; 3.336 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.308 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.334 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #422: Setup slack is -0.741 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.342 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.741 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.344 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.840 ; 85 ; 0.096 ; 1.046 ; +; Cell ; ; 14 ; 0.382 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.342 ; 3.344 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.493 ; 0.096 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.569 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.574 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.620 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.646 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.650 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.775 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.799 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.805 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.209 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.235 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.241 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.255 ; 1.014 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; +; 6.342 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; +; 6.342 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; +; 6.342 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #423: Setup slack is -0.741 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.336 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.741 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.055 ; ; ; ; ; ; +; Data Delay ; 3.338 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.800 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.418 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.168 ; 79 ; 0.000 ; 2.168 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.336 ; 3.338 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.275 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.355 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.359 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.213 ; 0.854 ; RR ; IC ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|datab ; +; 6.336 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X92_Y162_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~845|combout ; +; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|d ; +; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.443 ; 2.943 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.233 ; 2.168 ; RR ; IC ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13]|clk ; +; 5.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y162_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; +; 5.443 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.413 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.182 ; ; uTsu ; 1 ; FF_X92_Y162_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #424: Setup slack is -0.741 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.328 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.741 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.330 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.906 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.328 ; 3.330 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.302 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; +; 6.328 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; +; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; +; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #425: Setup slack is -0.740 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.334 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.740 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.336 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.902 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.334 ; 3.336 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.308 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.334 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #426: Setup slack is -0.740 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.342 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.740 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.350 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.675 ; 80 ; 0.138 ; 0.722 ; +; Cell ; ; 14 ; 0.550 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.342 ; 3.350 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.971 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 6.000 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 6.006 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.269 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.342 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.342 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.342 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #427: Setup slack is -0.740 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.336 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.740 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.338 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.829 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.388 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.336 ; 3.338 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.470 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.547 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.552 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; +; 6.309 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; +; 6.336 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; +; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; +; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #428: Setup slack is -0.740 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.345 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.740 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.347 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.806 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.420 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.345 ; 3.347 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.502 ; 0.584 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.531 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.536 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.258 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; +; 6.345 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; +; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; +; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #429: Setup slack is -0.740 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_mask[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.564 ; +; Slack ; -0.740 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.808 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.276 ; 0.862 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N33 ; High Speed ; vx_d_e_reg|i531~3|dataf ; +; 6.304 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N33 ; High Speed ; vx_d_e_reg|i531~3|combout ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3]|d ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N35 ; ; vx_d_e_reg|csr_mask[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #430: Setup slack is -0.740 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_mask[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.564 ; +; Slack ; -0.740 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.807 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.378 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.275 ; 0.861 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N36 ; High Speed ; vx_d_e_reg|i531~2|dataf ; +; 6.304 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N36 ; High Speed ; vx_d_e_reg|i531~2|combout ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2]|d ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N38 ; ; vx_d_e_reg|csr_mask[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #431: Setup slack is -0.739 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|PC_next_out[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.154 ; +; Data Required Time ; 5.415 ; +; Slack ; -0.739 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.156 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.696 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.154 ; 3.156 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.154 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; +; 6.154 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.415 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #432: Setup slack is -0.739 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.318 ; +; Data Required Time ; 5.579 ; +; Slack ; -0.739 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.320 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.838 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.318 ; 3.320 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.501 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.530 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.536 ; 0.006 ; FF ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; +; 6.291 ; 0.755 ; FF ; IC ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|dataf ; +; 6.318 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|combout ; +; 6.318 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|d ; +; 6.318 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #433: Setup slack is -0.739 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_address[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.505 ; +; Slack ; -0.739 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.125 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.715 ; 84 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.410 ; 13 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.419 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.171 ; 0.752 ; RR ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datae ; +; 6.244 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; +; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; +; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; +; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #434: Setup slack is -0.739 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.336 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.739 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.338 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.908 ; 87 ; 0.106 ; 1.378 ; +; Cell ; ; 12 ; 0.309 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.336 ; 3.338 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.306 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.336 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; +; 6.336 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #435: Setup slack is -0.738 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[2] ; +; To Node ; vx_e_m_reg|csr_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.354 ; +; Data Required Time ; 5.616 ; +; Slack ; -0.738 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.009 ; ; ; ; ; ; +; Data Delay ; 3.365 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.842 ; 84 ; 0.122 ; 0.777 ; +; Cell ; ; 16 ; 0.403 ; 12 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]|clk ; +; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2] ; +; 6.354 ; 3.365 ; ; ; ; ; ; data path ; +; 3.109 ; 0.120 ; RR ; uTco ; 1 ; FF_X51_Y153_N52 ; ; vx_csr_handler|decode_csr_address[2]|q ; +; 3.175 ; 0.066 ; RR ; CELL ; 686 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]~la_lab/laboutb[14] ; +; 3.952 ; 0.777 ; RR ; IC ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|datae ; +; 4.029 ; 0.077 ; RF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|combout ; +; 4.034 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144~la_mlab/laboutb[8] ; +; 4.461 ; 0.427 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|dataf ; +; 4.487 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; +; 4.492 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; +; 4.847 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; +; 4.875 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; +; 4.881 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; +; 5.144 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; +; 5.203 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; +; 5.209 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; +; 5.332 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; +; 5.395 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.399 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.174 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.201 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.206 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.328 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; +; 6.354 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; +; 6.354 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; +; 6.354 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; +; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; +; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.616 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #436: Setup slack is -0.738 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.195 ; +; Data Required Time ; 5.457 ; +; Slack ; -0.738 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.197 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.691 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.195 ; 3.197 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.195 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|sload ; +; 6.195 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.457 ; 0.014 ; ; uTsu ; 1 ; FF_X73_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #437: Setup slack is -0.738 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.337 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.738 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.345 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.568 ; 77 ; 0.118 ; 0.708 ; +; Cell ; ; 14 ; 0.651 ; 19 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.337 ; 3.345 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.948 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.976 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.982 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.262 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.337 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.337 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.337 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #438: Setup slack is -0.738 (VIOLATED) +=============================================================================== ++----------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.292 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.738 (VIOLATED) ; ++--------------------+-------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.294 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.793 ; 85 ; 0.108 ; 0.910 ; +; Cell ; ; 12 ; 0.379 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.292 ; 3.294 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.264 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; +; 6.292 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; +; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|d ; +; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #439: Setup slack is -0.738 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.352 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.738 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.354 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.887 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.352 ; 3.354 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.326 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; +; 6.352 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; +; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; +; 6.352 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #440: Setup slack is -0.738 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|PC_next_out[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.154 ; +; Data Required Time ; 5.416 ; +; Slack ; -0.738 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.156 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.696 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.154 ; 3.156 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.154 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; +; 6.154 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.416 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #441: Setup slack is -0.738 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.336 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.738 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.338 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.818 ; 84 ; 0.106 ; 1.275 ; +; Cell ; ; 12 ; 0.399 ; 12 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.336 ; 3.338 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.216 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.336 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; +; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #442: Setup slack is -0.738 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.341 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.738 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.048 ; ; ; ; ; ; +; Data Delay ; 3.343 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.884 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.341 ; 3.343 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.486 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.513 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.517 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.313 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; +; 6.341 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; +; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; +; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; +; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #443: Setup slack is -0.738 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; +; To Node ; vx_e_m_reg|alu_result[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.503 ; +; Slack ; -0.738 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.083 ; ; ; ; ; ; +; Data Delay ; 3.293 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.622 ; 80 ; 0.125 ; 0.816 ; +; Cell ; ; 14 ; 0.548 ; 17 ; 0.000 ; 0.124 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|clk ; +; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; +; 6.241 ; 3.293 ; ; ; ; ; ; data path ; +; 3.071 ; 0.123 ; FF ; uTco ; 1 ; FF_X79_Y153_N40 ; ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|q ; +; 3.115 ; 0.044 ; FF ; CELL ; 2 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE~la_lab/laboutb[6] ; +; 3.931 ; 0.816 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|dataf ; +; 3.958 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|combout ; +; 3.964 ; 0.006 ; FF ; CELL ; 70 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20~la_mlab/laboutt[7] ; +; 4.457 ; 0.493 ; FF ; IC ; 1 ; LABCELL_X68_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~30|datad ; +; 4.539 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X68_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~30|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 6 ; LABCELL_X68_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~30~la_lab/laboutb[16] ; +; 4.722 ; 0.179 ; RR ; IC ; 1 ; MLABCELL_X69_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~36|datac ; +; 4.815 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X69_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~36|combout ; +; 4.821 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X69_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~36~la_mlab/laboutb[3] ; +; 4.946 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50|dataa ; +; 5.070 ; 0.124 ; RR ; CELL ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50|combout ; +; 5.076 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50~la_mlab/laboutb[15] ; +; 5.301 ; 0.225 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|datad ; +; 5.379 ; 0.078 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|combout ; +; 5.385 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52~la_mlab/laboutb[11] ; +; 6.169 ; 0.784 ; RR ; IC ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|datad ; +; 6.241 ; 0.072 ; RR ; CELL ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|combout ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|d ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.503 ; 0.168 ; ; uTsu ; 1 ; FF_X46_Y153_N34 ; ; vx_e_m_reg|alu_result[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #444: Setup slack is -0.737 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.292 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.737 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.294 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.793 ; 85 ; 0.108 ; 0.910 ; +; Cell ; ; 12 ; 0.379 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.292 ; 3.294 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.264 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; +; 6.292 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; +; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|d ; +; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N17 ; ; vx_d_e_reg|b_reg_data[24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #445: Setup slack is -0.737 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.336 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.737 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.338 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.761 ; 83 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.134 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.336 ; 3.338 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.446 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.477 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.482 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.202 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; +; 6.336 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; +; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; +; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #446: Setup slack is -0.737 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.321 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.737 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.323 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.792 ; 84 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.409 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.321 ; 3.323 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.422 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.449 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.453 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.228 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; +; 6.321 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; +; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; +; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #447: Setup slack is -0.737 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|csr_address[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.288 ; +; Data Required Time ; 5.551 ; +; Slack ; -0.737 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.290 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.802 ; 85 ; 0.108 ; 0.935 ; +; Cell ; ; 12 ; 0.367 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.288 ; 3.290 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.260 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; +; 6.288 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; +; 6.288 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; +; 6.288 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #448: Setup slack is -0.736 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.342 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.736 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.344 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.794 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.428 ; 13 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.342 ; 3.344 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.062 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.089 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.095 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.266 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.342 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.342 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; +; 6.342 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #449: Setup slack is -0.736 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.322 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.736 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.324 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.777 ; 84 ; 0.110 ; 0.788 ; +; Cell ; ; 14 ; 0.426 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.322 ; 3.324 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.516 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.542 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.548 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.260 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.322 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #450: Setup slack is -0.736 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[19] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.290 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.736 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.292 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.791 ; 85 ; 0.108 ; 0.908 ; +; Cell ; ; 12 ; 0.379 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.290 ; 3.292 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.262 ; 0.908 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|dataf ; +; 6.290 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|combout ; +; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|d ; +; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N22 ; ; vx_d_e_reg|b_reg_data[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #451: Setup slack is -0.736 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.332 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.736 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.334 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.801 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.411 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.332 ; 3.334 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.299 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; +; 5.328 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; +; 5.332 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; +; 6.240 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; +; 6.332 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #452: Setup slack is -0.736 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.350 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.736 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.352 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.906 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.350 ; 3.352 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.324 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; +; 6.350 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; +; 6.350 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; +; 6.350 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #453: Setup slack is -0.736 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.335 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.736 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.337 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.927 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.335 ; 3.337 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.309 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; +; 6.335 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #454: Setup slack is -0.736 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.344 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.736 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.346 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.765 ; 83 ; 0.107 ; 0.868 ; +; Cell ; ; 14 ; 0.460 ; 14 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.344 ; 3.346 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.127 ; 0.712 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33|dataf ; +; 6.155 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33|combout ; +; 6.161 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33~la_mlab/laboutt[11] ; +; 6.268 ; 0.107 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|datae ; +; 6.344 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|combout ; +; 6.344 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|d ; +; 6.344 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y158_N25 ; ; vx_fetch|VX_Warp_one|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #455: Setup slack is -0.735 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.735 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.678 ; 82 ; 0.192 ; 0.657 ; +; Cell ; ; 14 ; 0.485 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; +; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.612 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.640 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.644 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.256 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.283 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #456: Setup slack is -0.735 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[12] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.195 ; +; Data Required Time ; 5.460 ; +; Slack ; -0.735 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.197 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.691 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.195 ; 3.197 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.195 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|sload ; +; 6.195 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.460 ; 0.017 ; ; uTsu ; 1 ; FF_X73_Y161_N46 ; ; vx_fetch|VX_Warp_zero|real_PC[12] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #457: Setup slack is -0.735 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.328 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.735 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.330 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.871 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.328 ; 3.330 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.468 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.499 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.503 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.301 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; +; 6.328 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; +; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; +; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #458: Setup slack is -0.735 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.288 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.735 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.290 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.788 ; 85 ; 0.108 ; 0.905 ; +; Cell ; ; 12 ; 0.380 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.288 ; 3.290 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.259 ; 0.905 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|dataf ; +; 6.288 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|combout ; +; 6.288 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|d ; +; 6.288 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N25 ; ; vx_d_e_reg|b_reg_data[31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #459: Setup slack is -0.735 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.335 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.735 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.337 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.870 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.335 ; 3.337 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.533 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.308 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.335 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #460: Setup slack is -0.735 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.334 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.735 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.336 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.780 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.435 ; 13 ; 0.000 ; 0.134 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.334 ; 3.336 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.444 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.480 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.200 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; +; 6.334 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; +; 6.334 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; +; 6.334 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #461: Setup slack is -0.735 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.319 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.735 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.321 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.811 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.319 ; 3.321 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.420 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.447 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.451 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.226 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; +; 6.319 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; +; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; +; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #462: Setup slack is -0.735 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.322 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.735 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.324 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.890 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.322 ; 3.324 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.296 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; +; 6.322 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #463: Setup slack is -0.734 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.342 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.734 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.344 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.794 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.428 ; 13 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.342 ; 3.344 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.062 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.089 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.095 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.266 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.342 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.342 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; +; 6.342 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #464: Setup slack is -0.734 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.734 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.769 ; 84 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.611 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.639 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.643 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.255 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.282 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #465: Setup slack is -0.734 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.195 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.734 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.197 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.691 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.195 ; 3.197 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.195 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|sload ; +; 6.195 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.018 ; ; uTsu ; 1 ; FF_X73_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #466: Setup slack is -0.734 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.333 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.734 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.341 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.733 ; 82 ; 0.128 ; 0.722 ; +; Cell ; ; 14 ; 0.483 ; 14 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.333 ; 3.341 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.236 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.944 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.972 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.978 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.258 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.333 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.333 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.333 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #467: Setup slack is -0.734 (VIOLATED) +=============================================================================== ++--------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.335 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.734 (VIOLATED) ; ++--------------------+-----------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.337 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.870 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.335 ; 3.337 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.533 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.308 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.335 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; +; 6.335 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #468: Setup slack is -0.734 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.330 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.734 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.332 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.820 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.330 ; 3.332 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.297 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; +; 5.326 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; +; 5.330 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; +; 6.238 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; +; 6.330 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #469: Setup slack is -0.734 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.334 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.734 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.336 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.861 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.355 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.334 ; 3.336 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.478 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.504 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.510 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.241 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; +; 6.334 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; +; 6.334 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; +; 6.334 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #470: Setup slack is -0.734 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|csr_address[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.239 ; +; Data Required Time ; 5.505 ; +; Slack ; -0.734 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 4 ; 2.847 ; 88 ; 0.590 ; 0.986 ; +; Cell ; ; 10 ; 0.273 ; 8 ; 0.000 ; 0.081 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.239 ; 3.247 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.798 ; 0.635 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|datad ; +; 3.879 ; 0.081 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; +; 3.885 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; +; 4.521 ; 0.636 ; RR ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; +; 4.548 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; +; 4.552 ; 0.004 ; FF ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; +; 5.538 ; 0.986 ; FF ; IC ; 1 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1|dataf ; +; 5.565 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1|combout ; +; 5.570 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1~la_lab/laboutt[3] ; +; 6.160 ; 0.590 ; FF ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datac ; +; 6.239 ; 0.079 ; FF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; +; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; +; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; +; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #471: Setup slack is -0.734 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.330 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.734 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.332 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.902 ; 87 ; 0.106 ; 1.372 ; +; Cell ; ; 12 ; 0.309 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.330 ; 3.332 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.300 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; +; 6.330 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #472: Setup slack is -0.734 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.333 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.734 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.335 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.795 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.419 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.333 ; 3.335 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.214 ; 0.297 ; RR ; IC ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|dataf ; +; 5.241 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|combout ; +; 5.245 ; 0.004 ; FF ; CELL ; 32 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9~la_lab/laboutb[16] ; +; 6.243 ; 0.998 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|datad ; +; 6.333 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|combout ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|d ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X107_Y158_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #473: Setup slack is -0.734 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.349 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.734 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.351 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.830 ; 84 ; 0.106 ; 1.300 ; +; Cell ; ; 12 ; 0.400 ; 12 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.349 ; 3.351 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.228 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.349 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; +; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #474: Setup slack is -0.734 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.333 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.734 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.335 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.818 ; 84 ; 0.106 ; 1.275 ; +; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.333 ; 3.335 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.216 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; +; 6.333 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; +; 6.333 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; +; 6.333 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #475: Setup slack is -0.734 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.349 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.734 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.351 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.830 ; 84 ; 0.106 ; 1.300 ; +; Cell ; ; 12 ; 0.400 ; 12 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.349 ; 3.351 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.228 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.349 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; +; 6.349 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #476: Setup slack is -0.733 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[2] ; +; To Node ; vx_e_m_reg|alu_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.346 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.733 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.009 ; ; ; ; ; ; +; Data Delay ; 3.357 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.834 ; 84 ; 0.114 ; 0.777 ; +; Cell ; ; 16 ; 0.403 ; 12 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]|clk ; +; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2] ; +; 6.346 ; 3.357 ; ; ; ; ; ; data path ; +; 3.109 ; 0.120 ; RR ; uTco ; 1 ; FF_X51_Y153_N52 ; ; vx_csr_handler|decode_csr_address[2]|q ; +; 3.175 ; 0.066 ; RR ; CELL ; 686 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]~la_lab/laboutb[14] ; +; 3.952 ; 0.777 ; RR ; IC ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|datae ; +; 4.029 ; 0.077 ; RF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|combout ; +; 4.034 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144~la_mlab/laboutb[8] ; +; 4.461 ; 0.427 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|dataf ; +; 4.487 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; +; 4.492 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; +; 4.847 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; +; 4.875 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; +; 4.881 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; +; 5.144 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; +; 5.203 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; +; 5.209 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; +; 5.332 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; +; 5.395 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.399 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.174 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.201 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.206 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.320 ; 0.114 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; +; 6.346 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; +; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; +; 6.346 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; +; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; +; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.163 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #477: Setup slack is -0.733 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.333 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.733 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.335 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.889 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.333 ; 3.335 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.531 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.306 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.333 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #478: Setup slack is -0.733 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.316 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.733 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.318 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.854 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.316 ; 3.318 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.434 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.467 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.289 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; +; 6.316 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; +; 6.316 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; +; 6.316 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #479: Setup slack is -0.733 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.327 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.733 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.329 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.917 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.292 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.327 ; 3.329 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.299 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; +; 6.327 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; +; 6.327 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; +; 6.327 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #480: Setup slack is -0.733 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.334 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.733 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.336 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.841 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.374 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.334 ; 3.336 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.235 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.262 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.268 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.247 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; +; 6.334 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; +; 6.334 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; +; 6.334 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #481: Setup slack is -0.733 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.320 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.733 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.322 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.930 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.272 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.320 ; 3.322 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.431 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.459 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.465 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.293 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.320 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.320 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|d ; +; 6.320 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #482: Setup slack is -0.733 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.323 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.733 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.325 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.844 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.360 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.323 ; 3.325 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.322 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.294 ; 0.940 ; FF ; IC ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|dataf ; +; 6.323 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|combout ; +; 6.323 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|d ; +; 6.323 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.162 ; ; uTsu ; 1 ; FF_X109_Y154_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #483: Setup slack is -0.733 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.334 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.733 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.336 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.829 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.334 ; 3.336 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.461 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.537 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.541 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.307 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; +; 6.334 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #484: Setup slack is -0.732 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.315 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.732 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.317 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.910 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.315 ; 3.317 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.479 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.506 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.512 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.288 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; +; 6.315 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; +; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; +; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #485: Setup slack is -0.732 (VIOLATED) +=============================================================================== ++--------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.333 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.732 (VIOLATED) ; ++--------------------+-----------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.335 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.889 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.333 ; 3.335 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.531 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.306 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.333 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #486: Setup slack is -0.732 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|csr_address[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.550 ; +; Slack ; -0.732 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.797 ; 85 ; 0.108 ; 0.930 ; +; Cell ; ; 12 ; 0.366 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.255 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; +; 6.282 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #487: Setup slack is -0.732 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.320 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.732 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.322 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.930 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.272 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.320 ; 3.322 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.431 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.459 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.465 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.293 ; 0.828 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|dataf ; +; 6.320 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X91_Y144_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~988|combout ; +; 6.320 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|d ; +; 6.320 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #488: Setup slack is -0.732 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.323 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.732 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.325 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.866 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.323 ; 3.325 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.546 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.296 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; +; 6.323 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; +; 6.323 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; +; 6.323 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #489: Setup slack is -0.732 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.314 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.732 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.316 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.852 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.314 ; 3.316 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.563 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; +; 6.287 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; +; 6.314 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; +; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; +; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #490: Setup slack is -0.732 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.328 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.732 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.330 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.795 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.414 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.328 ; 3.330 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.254 ; 0.328 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; +; 5.280 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; +; 5.285 ; 0.005 ; FF ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; +; 6.244 ; 0.959 ; FF ; IC ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|datad ; +; 6.328 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|combout ; +; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|d ; +; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y162_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #491: Setup slack is -0.732 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.336 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.732 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.338 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.818 ; 84 ; 0.106 ; 1.275 ; +; Cell ; ; 12 ; 0.399 ; 12 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.336 ; 3.338 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.216 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.336 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; +; 6.336 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #492: Setup slack is -0.731 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.303 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.731 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.305 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.847 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.303 ; 3.305 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.378 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.458 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.462 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.276 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; +; 6.303 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; +; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; +; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #493: Setup slack is -0.731 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.314 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.731 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.316 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.849 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.314 ; 3.316 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.503 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.530 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.535 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.286 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; +; 6.314 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; +; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; +; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #494: Setup slack is -0.731 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.332 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.731 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.334 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.761 ; 83 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.332 ; 3.334 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.446 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.477 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.482 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.202 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; +; 6.332 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; +; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; +; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #495: Setup slack is -0.731 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.330 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.731 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.332 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.908 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.330 ; 3.332 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.304 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; +; 6.330 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; +; 6.330 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; +; 6.330 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #496: Setup slack is -0.731 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.346 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.731 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.348 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.830 ; 85 ; 0.106 ; 1.300 ; +; Cell ; ; 12 ; 0.397 ; 12 ; 0.000 ; 0.118 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.346 ; 3.348 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.228 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|datab ; +; 6.346 ; 0.118 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; +; 6.346 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; +; 6.346 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #497: Setup slack is -0.730 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.329 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.730 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.331 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.922 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.329 ; 3.331 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.511 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.301 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; +; 6.329 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #498: Setup slack is -0.730 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|b_reg_data[30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.284 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.730 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.286 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.796 ; 85 ; 0.108 ; 0.929 ; +; Cell ; ; 12 ; 0.369 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.284 ; 3.286 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.255 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; +; 6.284 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; +; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; +; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #499: Setup slack is -0.730 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.328 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.730 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.330 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.868 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.328 ; 3.330 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.554 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.301 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|dataf ; +; 6.328 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|combout ; +; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|d ; +; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #500: Setup slack is -0.730 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.324 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.730 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.326 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.865 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.324 ; 3.326 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.297 ; 0.596 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|dataf ; +; 6.324 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|combout ; +; 6.324 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|d ; +; 6.324 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #501: Setup slack is -0.730 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.330 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.730 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.332 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.811 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.330 ; 3.332 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.243 ; 0.645 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|datad ; +; 6.330 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; +; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; +; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #502: Setup slack is -0.730 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.341 ; +; Data Required Time ; 5.611 ; +; Slack ; -0.730 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.343 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.880 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.341 ; 3.343 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.313 ; 0.770 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|dataf ; +; 6.341 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|combout ; +; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|d ; +; 6.341 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #503: Setup slack is -0.730 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.324 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.730 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.326 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.414 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.324 ; 3.326 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.254 ; 0.328 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; +; 5.280 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; +; 5.285 ; 0.005 ; FF ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; +; 6.240 ; 0.955 ; FF ; IC ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|datad ; +; 6.324 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|combout ; +; 6.324 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|d ; +; 6.324 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #504: Setup slack is -0.730 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.340 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.730 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.342 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.880 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.340 ; 3.342 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.481 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.508 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.514 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.312 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|dataf ; +; 6.340 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|combout ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|d ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.164 ; ; uTsu ; 1 ; FF_X104_Y146_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #505: Setup slack is -0.729 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.278 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.729 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.286 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.665 ; 81 ; 0.116 ; 0.686 ; +; Cell ; ; 14 ; 0.496 ; 15 ; 0.000 ; 0.114 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.278 ; 3.286 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; +; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.583 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.611 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.615 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.250 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.278 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #506: Setup slack is -0.729 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.277 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.729 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.664 ; 81 ; 0.116 ; 0.686 ; +; Cell ; ; 14 ; 0.496 ; 15 ; 0.000 ; 0.114 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.277 ; 3.285 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; +; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.583 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.611 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.615 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.249 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.277 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #507: Setup slack is -0.729 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.307 ; +; Data Required Time ; 5.578 ; +; Slack ; -0.729 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.309 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.902 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.307 ; 3.309 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.280 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; +; 6.307 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #508: Setup slack is -0.729 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.320 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.729 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.322 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.914 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.320 ; 3.322 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.293 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; +; 6.320 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; +; 6.320 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; +; 6.320 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #509: Setup slack is -0.729 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.312 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.729 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.314 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.868 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.312 ; 3.314 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.501 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.528 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.533 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.284 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; +; 6.312 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; +; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; +; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #510: Setup slack is -0.729 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.330 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.729 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.332 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.780 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.431 ; 13 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.330 ; 3.332 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.444 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.480 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.200 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; +; 6.330 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; +; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; +; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #511: Setup slack is -0.729 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.315 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.729 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.317 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.908 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.315 ; 3.317 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.421 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.448 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.454 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.289 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; +; 6.315 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; +; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; +; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #512: Setup slack is -0.729 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.329 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.729 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.331 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.842 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.367 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.329 ; 3.331 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.473 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.499 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.505 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.236 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; +; 6.329 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; +; 6.329 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; +; 6.329 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #513: Setup slack is -0.729 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.328 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.729 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.330 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.866 ; 86 ; 0.127 ; 1.302 ; +; Cell ; ; 12 ; 0.342 ; 10 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.328 ; 3.330 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.211 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; +; 6.328 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; +; 6.328 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; +; 6.328 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #514: Setup slack is -0.729 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.328 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.729 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.330 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.869 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.328 ; 3.330 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.300 ; 0.600 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|dataf ; +; 6.328 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|combout ; +; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|d ; +; 6.328 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #515: Setup slack is -0.729 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.333 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.729 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.335 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.818 ; 84 ; 0.106 ; 1.275 ; +; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.333 ; 3.335 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.216 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; +; 6.333 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; +; 6.333 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|d ; +; 6.333 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N11 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #516: Setup slack is -0.728 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.728 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.662 ; 81 ; 0.116 ; 0.686 ; +; Cell ; ; 14 ; 0.496 ; 15 ; 0.000 ; 0.114 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.275 ; 3.283 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; +; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.583 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.611 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.615 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.247 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.275 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #517: Setup slack is -0.728 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.277 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.728 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.705 ; 82 ; 0.117 ; 0.710 ; +; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.277 ; 3.285 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.582 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.610 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.614 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.249 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.277 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #518: Setup slack is -0.728 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.276 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.728 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.704 ; 82 ; 0.117 ; 0.710 ; +; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.276 ; 3.284 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.582 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.610 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.614 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.248 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.276 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #519: Setup slack is -0.728 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.334 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.728 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.336 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.924 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.292 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.334 ; 3.336 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.306 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; +; 6.334 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #520: Setup slack is -0.728 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.322 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.728 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.324 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.898 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.304 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.322 ; 3.324 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.294 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; +; 6.322 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #521: Setup slack is -0.728 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|csr_address[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.278 ; +; Data Required Time ; 5.550 ; +; Slack ; -0.728 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.280 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.845 ; 87 ; 0.119 ; 0.922 ; +; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.278 ; 3.280 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.329 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.251 ; 0.922 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; +; 6.278 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #522: Setup slack is -0.728 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.345 ; +; Data Required Time ; 5.617 ; +; Slack ; -0.728 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.027 ; ; ; ; ; ; +; Data Delay ; 3.347 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.885 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.345 ; 3.347 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.543 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.317 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|dataf ; +; 6.345 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|combout ; +; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|d ; +; 6.345 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; +; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.617 ; 0.176 ; ; uTsu ; 1 ; FF_X107_Y149_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #523: Setup slack is -0.728 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.346 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.728 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.348 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.821 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.346 ; 3.348 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.481 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.508 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.514 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.253 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|datac ; +; 6.346 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|combout ; +; 6.346 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|d ; +; 6.346 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y142_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #524: Setup slack is -0.727 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.340 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.727 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.342 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.873 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.340 ; 3.342 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.478 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.509 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.513 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.253 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; +; 6.340 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; +; 6.340 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; +; 6.340 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #525: Setup slack is -0.727 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.321 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.727 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.323 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.862 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.321 ; 3.323 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.514 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.239 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; +; 6.321 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; +; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; +; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #526: Setup slack is -0.727 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.274 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.727 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.702 ; 82 ; 0.117 ; 0.710 ; +; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.274 ; 3.282 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.582 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.610 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.614 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.246 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.274 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #527: Setup slack is -0.727 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.312 ; +; Data Required Time ; 5.585 ; +; Slack ; -0.727 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.314 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.783 ; 84 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.409 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.312 ; 3.314 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.422 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.449 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.453 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.219 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; +; 6.312 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; +; 6.312 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; +; 6.312 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #528: Setup slack is -0.727 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.322 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.727 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.324 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.896 ; 87 ; 0.106 ; 1.366 ; +; Cell ; ; 12 ; 0.307 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.322 ; 3.324 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.294 ; 1.366 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|dataf ; +; 6.322 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|combout ; +; 6.322 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|d ; +; 6.322 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #529: Setup slack is -0.727 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.325 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.727 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.051 ; ; ; ; ; ; +; Data Delay ; 3.327 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.869 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.325 ; 3.327 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.568 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.594 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.299 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|dataf ; +; 6.325 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|combout ; +; 6.325 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|d ; +; 6.325 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.447 ; 2.947 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; +; 5.447 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.417 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y163_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #530: Setup slack is -0.726 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.332 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.726 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.334 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.837 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 14 ; 0.377 ; 11 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.332 ; 3.334 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.297 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.052 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.079 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.085 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.256 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.332 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.332 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; +; 6.332 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #531: Setup slack is -0.726 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.316 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.726 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.318 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.910 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.316 ; 3.318 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.289 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; +; 6.316 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; +; 6.316 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; +; 6.316 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #532: Setup slack is -0.726 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|b_reg_data[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.726 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.812 ; 86 ; 0.108 ; 0.944 ; +; Cell ; ; 12 ; 0.349 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.252 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; +; 6.281 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #533: Setup slack is -0.726 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|b_reg_data[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.726 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.811 ; 86 ; 0.108 ; 0.943 ; +; Cell ; ; 12 ; 0.350 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.251 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; +; 6.281 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #534: Setup slack is -0.726 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.325 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.726 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.333 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.726 ; 82 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.482 ; 14 ; 0.000 ; 0.090 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.325 ; 3.333 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.228 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.936 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.964 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.970 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.250 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.325 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.325 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.325 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #535: Setup slack is -0.726 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.332 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.726 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.334 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.807 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.332 ; 3.334 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.240 ; 0.672 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|datad ; +; 6.332 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|combout ; +; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|d ; +; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #536: Setup slack is -0.725 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.310 ; +; Data Required Time ; 5.585 ; +; Slack ; -0.725 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.312 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.802 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.310 ; 3.312 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.420 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.447 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.451 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.217 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; +; 6.310 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #537: Setup slack is -0.725 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.339 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.725 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.341 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.877 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.339 ; 3.341 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.313 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; +; 6.339 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; +; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; +; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #538: Setup slack is -0.725 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.324 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.725 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.326 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.892 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.324 ; 3.326 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.298 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; +; 6.324 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; +; 6.324 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; +; 6.324 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #539: Setup slack is -0.725 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.312 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.725 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.314 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.853 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.312 ; 3.314 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.284 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; +; 6.312 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; +; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|d ; +; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #540: Setup slack is -0.725 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.312 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.725 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.314 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.853 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.312 ; 3.314 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.284 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; +; 6.312 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; +; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|d ; +; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #541: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.333 ; +; Data Required Time ; 5.609 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.335 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.764 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.450 ; 13 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.333 ; 3.335 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.094 ; 0.769 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; +; 6.123 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; +; 6.129 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; +; 6.257 ; 0.128 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; +; 6.333 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #542: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.332 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.334 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.837 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 14 ; 0.377 ; 11 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.332 ; 3.334 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.297 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.052 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.079 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.085 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.256 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.332 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.332 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; +; 6.332 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #543: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.305 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.307 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.900 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.305 ; 3.307 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.479 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.506 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.512 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.278 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; +; 6.305 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; +; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; +; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #544: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.307 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.309 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.852 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.307 ; 3.309 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.471 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.498 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.504 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.280 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; +; 6.307 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #545: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.326 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.328 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.923 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.283 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.326 ; 3.328 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.536 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.562 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.568 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.300 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; +; 6.326 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; +; 6.326 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; +; 6.326 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #546: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.308 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.310 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.842 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.308 ; 3.310 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.533 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.280 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; +; 6.308 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; +; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; +; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #547: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.323 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.325 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.751 ; 83 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.453 ; 14 ; 0.000 ; 0.134 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.323 ; 3.325 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.433 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.464 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.469 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.189 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; +; 6.323 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; +; 6.323 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; +; 6.323 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #548: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.308 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.310 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.782 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.308 ; 3.310 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.409 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.436 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.440 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.215 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; +; 6.308 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; +; 6.308 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; +; 6.308 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #549: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.310 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.312 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.889 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.301 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.310 ; 3.312 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.416 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.443 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.449 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.284 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; +; 6.310 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; +; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; +; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #550: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|b_reg_data[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.278 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.280 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.808 ; 86 ; 0.108 ; 0.940 ; +; Cell ; ; 12 ; 0.350 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.278 ; 3.280 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.248 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; +; 6.278 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; +; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; +; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #551: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.297 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.299 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.910 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.269 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.297 ; 3.299 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.278 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.305 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.309 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.270 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.297 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|d ; +; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #552: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_f_d_reg|curr_PC[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.192 ; +; Data Required Time ; 5.468 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.028 ; ; ; ; ; ; +; Data Delay ; 3.194 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.737 ; 86 ; 0.119 ; 1.282 ; +; Cell ; ; 10 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.192 ; 3.194 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.877 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.905 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.910 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.192 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|ena ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; +; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N25 ; ; vx_f_d_reg|curr_PC[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #553: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_f_d_reg|curr_PC[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.192 ; +; Data Required Time ; 5.468 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.028 ; ; ; ; ; ; +; Data Delay ; 3.194 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.737 ; 86 ; 0.119 ; 1.282 ; +; Cell ; ; 10 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.192 ; 3.194 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.877 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.905 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.910 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.192 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|ena ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; +; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N44 ; ; vx_f_d_reg|curr_PC[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #554: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.330 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.332 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.866 ; 86 ; 0.127 ; 1.302 ; +; Cell ; ; 12 ; 0.344 ; 10 ; 0.000 ; 0.119 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.330 ; 3.332 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.211 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; +; 6.330 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; +; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; +; 6.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #555: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++----------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------+ +; Property ; Value ; ++--------------------+-------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.311 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+-------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.313 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.604 ; 79 ; 0.192 ; 0.667 ; +; Cell ; ; 14 ; 0.588 ; 18 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.311 ; 3.313 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.573 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.599 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.605 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.204 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.311 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.311 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.311 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #556: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.322 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.324 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.799 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.322 ; 3.324 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.455 ; 0.538 ; RR ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.530 ; 0.075 ; RF ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.534 ; 0.004 ; FF ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.295 ; 0.761 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|dataf ; +; 6.322 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|combout ; +; 6.322 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|d ; +; 6.322 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #557: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.338 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.340 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.821 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.338 ; 3.340 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.252 ; 0.655 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|datac ; +; 6.338 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|combout ; +; 6.338 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|d ; +; 6.338 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X103_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #558: Setup slack is -0.724 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.313 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.724 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.315 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.749 ; 83 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.445 ; 13 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.313 ; 3.315 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.491 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.495 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.231 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; +; 6.313 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|d ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y164_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #559: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.333 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.335 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.764 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.450 ; 13 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.333 ; 3.335 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.084 ; 0.759 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; +; 6.111 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; +; 6.117 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; +; 6.255 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; +; 6.333 ; 0.078 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #560: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.325 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.333 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.554 ; 77 ; 0.118 ; 0.714 ; +; Cell ; ; 14 ; 0.653 ; 20 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.325 ; 3.333 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.954 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.984 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.990 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.250 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.325 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.325 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.325 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #561: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.295 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.297 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.295 ; 3.297 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.370 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.450 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.454 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.268 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; +; 6.295 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #562: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.310 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.318 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.544 ; 77 ; 0.118 ; 0.688 ; +; Cell ; ; 14 ; 0.648 ; 20 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.310 ; 3.318 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.516 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.542 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.548 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.236 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.310 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #563: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.319 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.321 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.409 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.319 ; 3.321 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.286 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; +; 5.315 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; +; 5.319 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; +; 6.227 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; +; 6.319 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #564: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.329 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.331 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.905 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.304 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.329 ; 3.331 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.301 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; +; 6.329 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; +; 6.329 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #565: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|csr_address[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.839 ; 87 ; 0.119 ; 0.916 ; +; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.329 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.245 ; 0.916 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; +; 6.272 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.200 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #566: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.323 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.325 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.826 ; 85 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.378 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.323 ; 3.325 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.467 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.493 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.499 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.230 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; +; 6.323 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; +; 6.323 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; +; 6.323 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #567: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.297 ; +; Data Required Time ; 5.574 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.299 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.910 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.269 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.297 ; 3.299 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.278 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.305 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.309 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.270 ; 0.961 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|dataf ; +; 6.297 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X89_Y164_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~521|combout ; +; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|d ; +; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.574 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y164_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #568: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++---------------------------------------------+ +; Path Summary ; ++--------------------+------------------------+ +; Property ; Value ; ++--------------------+------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.310 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.312 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.604 ; 79 ; 0.192 ; 0.667 ; +; Cell ; ; 14 ; 0.587 ; 18 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.310 ; 3.312 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.573 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.599 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.605 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.204 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.310 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #569: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.310 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.318 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.619 ; 79 ; 0.192 ; 0.682 ; +; Cell ; ; 14 ; 0.572 ; 17 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.310 ; 3.318 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.572 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.598 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.604 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.203 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.310 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #570: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.847 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.279 ; 0.681 ; RR ; IC ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|dataf ; +; 6.306 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|combout ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|d ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #571: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|a_reg_data[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.167 ; +; Data Required Time ; 5.444 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.077 ; ; ; ; ; ; +; Data Delay ; 3.169 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.698 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.167 ; 3.169 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.167 ; 0.752 ; FF ; IC ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2]|sclr ; +; 6.167 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2]|clk ; +; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2] ; +; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.444 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y157_N40 ; ; vx_d_e_reg|a_reg_data[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #572: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.322 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.324 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.862 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.322 ; 3.324 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.509 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.541 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.545 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.296 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|dataf ; +; 6.322 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|combout ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|d ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #573: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|a_reg_data[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.167 ; +; Data Required Time ; 5.444 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.077 ; ; ; ; ; ; +; Data Delay ; 3.169 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.698 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.167 ; 3.169 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.167 ; 0.752 ; FF ; IC ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5]|sclr ; +; 6.167 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5]|clk ; +; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5] ; +; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.444 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y157_N46 ; ; vx_d_e_reg|a_reg_data[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #574: Setup slack is -0.723 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.313 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.723 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.315 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.749 ; 83 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.445 ; 13 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.313 ; 3.315 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.491 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.495 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.231 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; +; 6.313 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|d ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #575: Setup slack is -0.722 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.321 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.722 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.323 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.851 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.321 ; 3.323 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.481 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.229 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.321 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; +; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #576: Setup slack is -0.722 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.318 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.722 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.320 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.911 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.318 ; 3.320 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.511 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.290 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; +; 6.318 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #577: Setup slack is -0.722 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.321 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.722 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.323 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.864 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.321 ; 3.323 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.503 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.293 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; +; 6.321 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; +; 6.321 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; +; 6.321 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #578: Setup slack is -0.722 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.722 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.861 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.531 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.278 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; +; 6.306 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #579: Setup slack is -0.722 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.322 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.722 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.324 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.860 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.322 ; 3.324 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.520 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.295 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.322 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #580: Setup slack is -0.722 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.316 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.722 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.318 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.882 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.315 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.316 ; 3.318 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.288 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; +; 6.316 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; +; 6.316 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; +; 6.316 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #581: Setup slack is -0.722 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|a_reg_data[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.114 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.722 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.116 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.643 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.114 ; 3.116 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.114 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|sclr ; +; 6.114 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N16 ; ; vx_d_e_reg|a_reg_data[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #582: Setup slack is -0.722 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|a_reg_data[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.114 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.722 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.116 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.643 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.114 ; 3.116 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.114 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|sclr ; +; 6.114 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N26 ; ; vx_d_e_reg|a_reg_data[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #583: Setup slack is -0.722 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.114 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.722 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.116 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.643 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.114 ; 3.116 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.114 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|sclr ; +; 6.114 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N25 ; ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #584: Setup slack is -0.722 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.309 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.722 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.317 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.619 ; 79 ; 0.192 ; 0.682 ; +; Cell ; ; 14 ; 0.571 ; 17 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.309 ; 3.317 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.572 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.598 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.604 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.203 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.309 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #585: Setup slack is -0.722 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.335 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.722 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.337 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.809 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.335 ; 3.337 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.509 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.541 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.545 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.243 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|datac ; +; 6.335 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|combout ; +; 6.335 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|d ; +; 6.335 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #586: Setup slack is -0.721 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.307 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.721 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.315 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.660 ; 80 ; 0.116 ; 0.712 ; +; Cell ; ; 14 ; 0.530 ; 16 ; 0.000 ; 0.114 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.307 ; 3.315 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; +; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.501 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.527 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.533 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.245 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.307 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #587: Setup slack is -0.721 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.721 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.759 ; 84 ; 0.110 ; 0.788 ; +; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.598 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.626 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.630 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.242 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.269 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #588: Setup slack is -0.721 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.333 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.721 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.335 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.928 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.333 ; 3.335 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.307 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; +; 6.333 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; +; 6.333 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #589: Setup slack is -0.721 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.312 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.721 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.314 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.856 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.312 ; 3.314 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.285 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; +; 6.312 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; +; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; +; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #590: Setup slack is -0.721 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.299 ; +; Data Required Time ; 5.578 ; +; Slack ; -0.721 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.301 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.844 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.299 ; 3.301 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.272 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; +; 6.299 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; +; 6.299 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; +; 6.299 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #591: Setup slack is -0.721 (VIOLATED) +=============================================================================== ++--------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.322 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.721 (VIOLATED) ; ++--------------------+-----------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.324 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.860 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.322 ; 3.324 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.520 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.295 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.322 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #592: Setup slack is -0.721 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|PC_next_out[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.136 ; +; Data Required Time ; 5.415 ; +; Slack ; -0.721 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.138 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.697 ; 86 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.319 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.136 ; 3.138 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.136 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; +; 6.136 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.415 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #593: Setup slack is -0.721 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.320 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.721 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.322 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.808 ; 85 ; 0.104 ; 1.302 ; +; Cell ; ; 12 ; 0.392 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.320 ; 3.322 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.203 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; +; 6.320 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; +; 6.320 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; +; 6.320 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #594: Setup slack is -0.721 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.577 ; +; Slack ; -0.721 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.058 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.841 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.165 ; 79 ; 0.000 ; 2.165 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.298 ; 3.300 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.395 ; 0.454 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|dataf ; +; 5.424 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|combout ; +; 5.428 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29~la_lab/laboutb[14] ; +; 6.272 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|dataf ; +; 6.298 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|combout ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|d ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.440 ; 2.940 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.230 ; 2.165 ; RR ; IC ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|clk ; +; 5.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; +; 5.440 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.410 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.577 ; 0.167 ; ; uTsu ; 1 ; FF_X88_Y164_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #595: Setup slack is -0.721 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|rs1[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.285 ; +; Data Required Time ; 5.564 ; +; Slack ; -0.721 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.287 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.789 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.285 ; 3.287 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.257 ; 0.843 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N0 ; High Speed ; vx_d_e_reg|i316~1|dataf ; +; 6.285 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N0 ; High Speed ; vx_d_e_reg|i316~1|combout ; +; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1]|d ; +; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N2 ; ; vx_d_e_reg|rs1[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #596: Setup slack is -0.720 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|csr_mask[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.308 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.720 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.310 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.805 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.384 ; 12 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.308 ; 3.310 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.621 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.647 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.653 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.280 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; +; 6.308 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; +; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; +; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #597: Setup slack is -0.720 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|csr_mask[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.308 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.720 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.310 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.805 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.384 ; 12 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.308 ; 3.310 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.621 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.647 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.653 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.280 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; +; 6.308 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; +; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; +; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #598: Setup slack is -0.720 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.720 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.788 ; 85 ; 0.116 ; 0.788 ; +; Cell ; ; 14 ; 0.362 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.574 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.602 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.606 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.241 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.269 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #599: Setup slack is -0.720 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.720 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.787 ; 85 ; 0.116 ; 0.788 ; +; Cell ; ; 14 ; 0.362 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.574 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.602 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.606 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.240 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.268 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #600: Setup slack is -0.720 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.321 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.720 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.323 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.851 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.321 ; 3.323 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.481 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.229 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.321 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; +; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #601: Setup slack is -0.720 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.720 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.314 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.700 ; 81 ; 0.117 ; 0.712 ; +; Cell ; ; 14 ; 0.489 ; 15 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.306 ; 3.314 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.500 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.526 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.532 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.244 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.306 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #602: Setup slack is -0.720 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.303 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.720 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.305 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.895 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.303 ; 3.305 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.421 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.448 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.454 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.276 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; +; 6.303 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; +; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; +; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #603: Setup slack is -0.720 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|PC_next_out[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.136 ; +; Data Required Time ; 5.416 ; +; Slack ; -0.720 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.138 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.697 ; 86 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.319 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.136 ; 3.138 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.136 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; +; 6.136 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.416 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #604: Setup slack is -0.720 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.190 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.720 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.192 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.735 ; 86 ; 0.119 ; 1.398 ; +; Cell ; ; 10 ; 0.335 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.190 ; 3.192 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.425 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.759 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.787 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.792 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.190 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.190 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #605: Setup slack is -0.720 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_mask[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.284 ; +; Data Required Time ; 5.564 ; +; Slack ; -0.720 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.286 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.788 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.377 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.284 ; 3.286 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.256 ; 0.842 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N6 ; High Speed ; vx_d_e_reg|i531~0|dataf ; +; 6.284 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N6 ; High Speed ; vx_d_e_reg|i531~0|combout ; +; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0]|d ; +; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N7 ; ; vx_d_e_reg|csr_mask[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #606: Setup slack is -0.720 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_address[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.232 ; +; Data Required Time ; 5.512 ; +; Slack ; -0.720 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.122 ; ; ; ; ; ; +; Data Delay ; 3.234 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.749 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.364 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.232 ; 3.234 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.419 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.205 ; 0.786 ; RR ; IC ; 1 ; LABCELL_X51_Y152_N21 ; High Speed ; vx_d_e_reg|i498~4|dataf ; +; 6.232 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y152_N21 ; High Speed ; vx_d_e_reg|i498~4|combout ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4]|d ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.376 ; 2.876 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4] ; +; 5.376 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.346 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.512 ; 0.166 ; ; uTsu ; 1 ; FF_X51_Y152_N22 ; ; vx_d_e_reg|csr_address[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #607: Setup slack is -0.719 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.719 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.785 ; 85 ; 0.116 ; 0.788 ; +; Cell ; ; 14 ; 0.362 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.574 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.602 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.606 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.238 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.266 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #608: Setup slack is -0.719 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.321 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.719 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.329 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.719 ; 82 ; 0.128 ; 0.722 ; +; Cell ; ; 14 ; 0.485 ; 15 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.321 ; 3.329 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.236 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.950 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.980 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.986 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.246 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.321 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #609: Setup slack is -0.719 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.332 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.719 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.334 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.815 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.332 ; 3.334 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.470 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.501 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.505 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.245 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; +; 6.332 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; +; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; +; 6.332 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #610: Setup slack is -0.719 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.313 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.719 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.315 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.804 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.313 ; 3.315 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.506 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.231 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; +; 6.313 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #611: Setup slack is -0.719 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|csr_address[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.551 ; +; Slack ; -0.719 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.803 ; 86 ; 0.108 ; 0.935 ; +; Cell ; ; 12 ; 0.347 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.242 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; +; 6.270 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; +; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; +; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #612: Setup slack is -0.719 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|a_reg_data[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.114 ; +; Data Required Time ; 5.395 ; +; Slack ; -0.719 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.116 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.643 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.114 ; 3.116 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.114 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|sclr ; +; 6.114 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N38 ; ; vx_d_e_reg|a_reg_data[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #613: Setup slack is -0.719 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|a_reg_data[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.114 ; +; Data Required Time ; 5.395 ; +; Slack ; -0.719 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.116 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.643 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.114 ; 3.116 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.114 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|sclr ; +; 6.114 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N32 ; ; vx_d_e_reg|a_reg_data[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #614: Setup slack is -0.719 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.318 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.719 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.320 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.861 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.318 ; 3.320 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.599 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.291 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|dataf ; +; 6.318 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|combout ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|d ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #615: Setup slack is -0.719 (VIOLATED) +=============================================================================== ++----------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; To Node ; vx_e_m_reg|alu_result[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.220 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.719 (VIOLATED) ; ++--------------------+-------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.087 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.325 ; 79 ; 0.000 ; 2.325 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.566 ; 79 ; 0.120 ; 0.864 ; +; Cell ; ; 16 ; 0.520 ; 16 ; 0.000 ; 0.132 ; +; uTco ; ; 1 ; 0.182 ; 6 ; 0.182 ; 0.182 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.952 ; 2.952 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.952 ; 2.325 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; +; 2.952 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; 6.220 ; 3.268 ; ; ; ; ; ; data path ; +; 3.134 ; 0.182 ; FF ; uTco ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|q ; +; 3.178 ; 0.044 ; FF ; CELL ; 4 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE~la_lab/laboutt[10] ; +; 4.042 ; 0.864 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~22|dataf ; +; 4.069 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~22|combout ; +; 4.075 ; 0.006 ; RR ; CELL ; 3 ; MLABCELL_X72_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~22~la_mlab/laboutb[3] ; +; 4.196 ; 0.121 ; RR ; IC ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43|datab ; +; 4.307 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43|combout ; +; 4.313 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43~la_mlab/laboutt[12] ; +; 4.437 ; 0.124 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|datad ; +; 4.527 ; 0.090 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|combout ; +; 4.533 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46~la_mlab/laboutt[8] ; +; 4.653 ; 0.120 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|dataa ; +; 4.785 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.789 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.222 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.249 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.255 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.412 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; +; 5.440 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; +; 5.445 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; +; 6.192 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; +; 6.220 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; +; 6.220 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; +; 6.220 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #616: Setup slack is -0.719 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[29] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.138 ; +; Data Required Time ; 5.419 ; +; Slack ; -0.719 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.140 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.138 ; 3.140 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29]|sclr ; +; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.419 ; 0.014 ; ; uTsu ; 1 ; FF_X80_Y155_N22 ; ; vx_d_e_reg|PC_next_out[29] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #617: Setup slack is -0.718 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.314 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.718 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.316 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.861 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.333 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.314 ; 3.316 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.438 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.515 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.519 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.287 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; +; 6.314 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; +; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; +; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #618: Setup slack is -0.718 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.308 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.718 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.310 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.852 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.308 ; 3.310 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.281 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; +; 6.308 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; +; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; +; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #619: Setup slack is -0.718 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.301 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.718 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.303 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.839 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.301 ; 3.303 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.490 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.517 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.522 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.273 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; +; 6.301 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #620: Setup slack is -0.718 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.319 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.718 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.321 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.751 ; 83 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.319 ; 3.321 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.433 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.464 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.469 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.189 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; +; 6.319 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; +; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; +; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #621: Setup slack is -0.718 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.718 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.873 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.312 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.410 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.437 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.443 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.278 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; +; 6.304 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #622: Setup slack is -0.718 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[27] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.138 ; +; Data Required Time ; 5.420 ; +; Slack ; -0.718 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.140 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.138 ; 3.140 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27]|sclr ; +; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.420 ; 0.015 ; ; uTsu ; 1 ; FF_X80_Y155_N16 ; ; vx_d_e_reg|PC_next_out[27] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #623: Setup slack is -0.718 (VIOLATED) +=============================================================================== ++-----------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------+ +; Property ; Value ; ++--------------------+--------------------------+ +; From Node ; vx_d_e_reg|a_reg_data[9] ; +; To Node ; vx_e_m_reg|alu_result[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.219 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.718 (VIOLATED) ; ++--------------------+--------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.320 ; 79 ; 0.000 ; 2.320 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.595 ; 79 ; 0.131 ; 0.774 ; +; Cell ; ; 16 ; 0.443 ; 14 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.234 ; 7 ; 0.234 ; 0.234 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.947 ; 2.947 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.947 ; 2.320 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; +; 2.947 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; +; 6.219 ; 3.272 ; ; ; ; ; ; data path ; +; 3.181 ; 0.234 ; RR ; uTco ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9]|q ; +; 3.245 ; 0.064 ; RR ; CELL ; 15 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]~la_lab/laboutb[2] ; +; 4.019 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30|datae ; +; 4.092 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30|combout ; +; 4.098 ; 0.006 ; RR ; CELL ; 3 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30~la_mlab/laboutt[13] ; +; 4.234 ; 0.136 ; RR ; IC ; 1 ; MLABCELL_X74_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~32|datad ; +; 4.323 ; 0.089 ; RF ; CELL ; 1 ; MLABCELL_X74_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~32|combout ; +; 4.329 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X74_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~32~la_mlab/laboutt[1] ; +; 4.460 ; 0.131 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|dataf ; +; 4.488 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; +; 4.492 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; +; 4.709 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; +; 4.784 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.788 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.221 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.248 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.254 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.411 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; +; 5.439 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; +; 5.444 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; +; 6.191 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; +; 6.219 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; +; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; +; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #624: Setup slack is -0.717 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.317 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.717 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.319 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.795 ; 84 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.317 ; 3.319 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.534 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.234 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; +; 6.317 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; +; 6.317 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; +; 6.317 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #625: Setup slack is -0.717 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.323 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.717 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.325 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.889 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.315 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.323 ; 3.325 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.295 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; +; 6.323 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; +; 6.323 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; +; 6.323 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #626: Setup slack is -0.717 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.138 ; +; Data Required Time ; 5.421 ; +; Slack ; -0.717 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.140 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.138 ; 3.140 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26]|sclr ; +; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.421 ; 0.016 ; ; uTsu ; 1 ; FF_X80_Y155_N14 ; ; vx_d_e_reg|PC_next_out[26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #627: Setup slack is -0.716 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.297 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.716 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.299 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.842 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.297 ; 3.299 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.471 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.498 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.504 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.270 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; +; 6.297 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; +; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; +; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #628: Setup slack is -0.716 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.318 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.716 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.320 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.865 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.333 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.318 ; 3.320 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.528 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.554 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.560 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.292 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; +; 6.318 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #629: Setup slack is -0.716 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|b_reg_data[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.716 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.854 ; 87 ; 0.108 ; 0.943 ; +; Cell ; ; 12 ; 0.299 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.241 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; +; 6.271 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #630: Setup slack is -0.716 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|b_reg_data[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.716 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.855 ; 87 ; 0.108 ; 0.944 ; +; Cell ; ; 12 ; 0.298 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.242 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; +; 6.271 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #631: Setup slack is -0.716 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|a_reg_data[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.157 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.716 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.159 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.686 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.157 ; 3.159 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.157 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|sclr ; +; 6.157 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #632: Setup slack is -0.716 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|a_reg_data[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.157 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.716 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.159 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.686 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.157 ; 3.159 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.157 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|sclr ; +; 6.157 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N40 ; ; vx_d_e_reg|a_reg_data[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #633: Setup slack is -0.716 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|a_reg_data[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.157 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.716 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.159 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.686 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.157 ; 3.159 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.157 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|sclr ; +; 6.157 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N43 ; ; vx_d_e_reg|a_reg_data[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #634: Setup slack is -0.716 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_f_d_reg|curr_PC[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.181 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.716 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.183 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.737 ; 86 ; 0.119 ; 1.297 ; +; Cell ; ; 10 ; 0.325 ; 10 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.181 ; 3.183 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.517 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.851 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.879 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.884 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.181 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|ena ; +; 6.181 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N38 ; ; vx_f_d_reg|curr_PC[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #635: Setup slack is -0.716 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_f_d_reg|curr_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.181 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.716 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.183 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.737 ; 86 ; 0.119 ; 1.297 ; +; Cell ; ; 10 ; 0.325 ; 10 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.181 ; 3.183 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.517 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.851 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.879 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.884 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.181 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|ena ; +; 6.181 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N32 ; ; vx_f_d_reg|curr_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #636: Setup slack is -0.716 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.322 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.716 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.324 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.808 ; 84 ; 0.104 ; 1.302 ; +; Cell ; ; 12 ; 0.394 ; 12 ; 0.000 ; 0.119 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.322 ; 3.324 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.203 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; +; 6.322 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; +; 6.322 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; +; 6.322 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #637: Setup slack is -0.716 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.303 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.716 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.311 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.605 ; 79 ; 0.138 ; 0.722 ; +; Cell ; ; 14 ; 0.581 ; 18 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.303 ; 3.311 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.565 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.591 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.597 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.196 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.303 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #638: Setup slack is -0.716 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.577 ; +; Slack ; -0.716 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.833 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.543 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.265 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|dataf ; +; 6.293 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|combout ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|d ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.577 ; 0.163 ; ; uTsu ; 1 ; FF_X93_Y162_N53 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #639: Setup slack is -0.715 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.715 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.771 ; 85 ; 0.108 ; 0.888 ; +; Cell ; ; 12 ; 0.378 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.242 ; 0.888 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|dataf ; +; 6.269 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|combout ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|d ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #640: Setup slack is -0.715 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.315 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.715 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.317 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.814 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.315 ; 3.317 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.532 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.232 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; +; 6.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; +; 6.315 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; +; 6.315 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #641: Setup slack is -0.715 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.715 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.876 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.298 ; 3.300 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.416 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.443 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.449 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.271 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; +; 6.298 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #642: Setup slack is -0.715 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|a_reg_data[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.157 ; +; Data Required Time ; 5.442 ; +; Slack ; -0.715 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.159 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.686 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.157 ; 3.159 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.157 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|sclr ; +; 6.157 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.442 ; 0.054 ; ; uTsu ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #643: Setup slack is -0.715 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.302 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.715 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.310 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.605 ; 79 ; 0.138 ; 0.722 ; +; Cell ; ; 14 ; 0.580 ; 18 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.302 ; 3.310 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.565 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.591 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.597 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.196 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.302 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #644: Setup slack is -0.715 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.319 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.715 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.321 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.860 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.319 ; 3.321 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.366 ; 0.437 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|dataf ; +; 5.395 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|combout ; +; 5.399 ; 0.004 ; RR ; CELL ; 16 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14~la_lab/laboutt[4] ; +; 6.292 ; 0.893 ; RR ; IC ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|dataf ; +; 6.319 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|combout ; +; 6.319 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|d ; +; 6.319 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y159_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #645: Setup slack is -0.715 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.288 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.715 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.290 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.783 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.288 ; 3.290 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.461 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.537 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.541 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.261 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|dataf ; +; 6.288 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|combout ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|d ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #646: Setup slack is -0.715 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_address[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.227 ; +; Data Required Time ; 5.512 ; +; Slack ; -0.715 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.122 ; ; ; ; ; ; +; Data Delay ; 3.229 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.743 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.365 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.227 ; 3.229 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.419 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.199 ; 0.780 ; RR ; IC ; 1 ; LABCELL_X51_Y152_N9 ; High Speed ; vx_d_e_reg|i498~2|dataf ; +; 6.227 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X51_Y152_N9 ; High Speed ; vx_d_e_reg|i498~2|combout ; +; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2]|d ; +; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.376 ; 2.876 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2] ; +; 5.376 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.346 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.512 ; 0.166 ; ; uTsu ; 1 ; FF_X51_Y152_N11 ; ; vx_d_e_reg|csr_address[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #647: Setup slack is -0.715 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.310 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.715 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.312 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.884 ; 87 ; 0.106 ; 1.354 ; +; Cell ; ; 12 ; 0.307 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.310 ; 3.312 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.282 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; +; 6.310 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|d ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #648: Setup slack is -0.714 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.318 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.714 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.320 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.852 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 10 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.318 ; 3.320 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.345 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; +; 5.375 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; +; 5.379 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; +; 6.232 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; +; 6.318 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; +; 6.318 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; +; 6.318 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #649: Setup slack is -0.714 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.313 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.714 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.315 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.793 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.313 ; 3.315 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.473 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.221 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.313 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #650: Setup slack is -0.714 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.310 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.714 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.312 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.853 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.310 ; 3.312 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.503 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.282 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; +; 6.310 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; +; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; +; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #651: Setup slack is -0.714 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.299 ; +; Data Required Time ; 5.585 ; +; Slack ; -0.714 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.301 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.773 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.299 ; 3.301 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.409 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.436 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.440 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.206 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; +; 6.299 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; +; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; +; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #652: Setup slack is -0.714 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|csr_address[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.550 ; +; Slack ; -0.714 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.798 ; 86 ; 0.108 ; 0.930 ; +; Cell ; ; 12 ; 0.346 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.237 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; +; 6.264 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #653: Setup slack is -0.714 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|b_reg_data[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.714 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.851 ; 87 ; 0.108 ; 0.940 ; +; Cell ; ; 12 ; 0.299 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.238 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; +; 6.268 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #654: Setup slack is -0.714 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[1] ; +; To Node ; vx_e_m_reg|csr_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.313 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.714 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.013 ; ; ; ; ; ; +; Data Delay ; 3.338 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.348 ; 79 ; 0.000 ; 2.348 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.675 ; 80 ; 0.122 ; 0.777 ; +; Cell ; ; 16 ; 0.534 ; 16 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.129 ; 4 ; 0.129 ; 0.129 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.975 ; 2.975 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.975 ; 2.348 ; RR ; IC ; 1 ; FF_X40_Y149_N38 ; High Speed ; vx_csr_handler|decode_csr_address[1]|clk ; +; 2.975 ; 0.000 ; RR ; CELL ; 1 ; FF_X40_Y149_N38 ; High Speed ; vx_csr_handler|decode_csr_address[1] ; +; 6.313 ; 3.338 ; ; ; ; ; ; data path ; +; 3.104 ; 0.129 ; RR ; uTco ; 1 ; FF_X40_Y149_N38 ; ; vx_csr_handler|decode_csr_address[1]|q ; +; 3.167 ; 0.063 ; RR ; CELL ; 548 ; FF_X40_Y149_N38 ; High Speed ; vx_csr_handler|decode_csr_address[1]~la_lab/laboutb[5] ; +; 3.808 ; 0.641 ; RR ; IC ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|datae ; +; 3.883 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|combout ; +; 3.888 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196~la_lab/laboutb[1] ; +; 4.335 ; 0.447 ; RR ; IC ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|datae ; +; 4.408 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|combout ; +; 4.414 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200~la_mlab/laboutt[0] ; +; 4.539 ; 0.125 ; RR ; IC ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|datac ; +; 4.619 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|combout ; +; 4.623 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211~la_lab/laboutb[14] ; +; 5.059 ; 0.436 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|datad ; +; 5.139 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; +; 5.143 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; +; 5.270 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; +; 5.353 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.357 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.134 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.160 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.165 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.287 ; 0.122 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; +; 6.313 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; +; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #655: Setup slack is -0.714 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[0]~DUPLICATE ; +; To Node ; vx_e_m_reg|csr_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.313 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.714 (VIOLATED) ; ++--------------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.013 ; ; ; ; ; ; +; Data Delay ; 3.338 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.348 ; 79 ; 0.000 ; 2.348 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.743 ; 82 ; 0.122 ; 0.777 ; +; Cell ; ; 16 ; 0.469 ; 14 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+-------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+-------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.975 ; 2.975 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.975 ; 2.348 ; RR ; IC ; 1 ; FF_X40_Y149_N28 ; High Speed ; vx_csr_handler|decode_csr_address[0]~DUPLICATE|clk ; +; 2.975 ; 0.000 ; RR ; CELL ; 1 ; FF_X40_Y149_N28 ; High Speed ; vx_csr_handler|decode_csr_address[0]~DUPLICATE ; +; 6.313 ; 3.338 ; ; ; ; ; ; data path ; +; 3.101 ; 0.126 ; FF ; uTco ; 1 ; FF_X40_Y149_N28 ; ; vx_csr_handler|decode_csr_address[0]~DUPLICATE|q ; +; 3.145 ; 0.044 ; FF ; CELL ; 363 ; FF_X40_Y149_N28 ; High Speed ; vx_csr_handler|decode_csr_address[0]~DUPLICATE~la_lab/laboutt[18] ; +; 3.854 ; 0.709 ; FF ; IC ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|dataf ; +; 3.883 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|combout ; +; 3.888 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196~la_lab/laboutb[1] ; +; 4.335 ; 0.447 ; RR ; IC ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|datae ; +; 4.408 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|combout ; +; 4.414 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200~la_mlab/laboutt[0] ; +; 4.539 ; 0.125 ; RR ; IC ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|datac ; +; 4.619 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|combout ; +; 4.623 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211~la_lab/laboutb[14] ; +; 5.059 ; 0.436 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|datad ; +; 5.139 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; +; 5.143 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; +; 5.270 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; +; 5.353 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.357 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.134 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.160 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.165 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.287 ; 0.122 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; +; 6.313 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+----------------------+------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; +; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #656: Setup slack is -0.714 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.301 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.714 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.303 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.824 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.301 ; 3.303 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.493 ; 0.575 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.519 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.524 ; 0.005 ; FF ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.273 ; 0.749 ; FF ; IC ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|dataf ; +; 6.301 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|combout ; +; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|d ; +; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #657: Setup slack is -0.714 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.318 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.714 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.320 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.784 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.415 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.318 ; 3.320 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.493 ; 0.005 ; FF ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.233 ; 0.740 ; FF ; IC ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|datac ; +; 6.318 ; 0.085 ; FF ; CELL ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|combout ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|d ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X107_Y157_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #658: Setup slack is -0.713 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|csr_mask[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.301 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.713 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.303 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.834 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.349 ; 11 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.301 ; 3.303 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.614 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.640 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.646 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.273 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; +; 6.301 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #659: Setup slack is -0.713 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|csr_mask[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.301 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.713 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.303 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.834 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.349 ; 11 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.301 ; 3.303 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.614 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.640 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.646 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.273 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; +; 6.301 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #660: Setup slack is -0.713 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.325 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.713 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.327 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.870 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.325 ; 3.327 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.299 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; +; 6.325 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; +; 6.325 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; +; 6.325 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #661: Setup slack is -0.713 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.310 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.713 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.312 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.884 ; 87 ; 0.106 ; 1.354 ; +; Cell ; ; 12 ; 0.307 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.310 ; 3.312 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.282 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; +; 6.310 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|d ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #662: Setup slack is -0.713 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.138 ; +; Data Required Time ; 5.425 ; +; Slack ; -0.713 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.140 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.138 ; 3.140 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30]|sclr ; +; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.425 ; 0.020 ; ; uTsu ; 1 ; FF_X80_Y155_N25 ; ; vx_d_e_reg|PC_next_out[30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #663: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.299 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.301 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.766 ; 84 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.413 ; 13 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.299 ; 3.301 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.561 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.587 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.593 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.192 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.299 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.299 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.299 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #664: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.783 ; 84 ; 0.116 ; 0.788 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.298 ; 3.300 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.492 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.518 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.524 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.236 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.298 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #665: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.313 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.315 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.793 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.313 ; 3.315 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.473 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.221 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.313 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #666: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.311 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.319 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.677 ; 81 ; 0.136 ; 0.708 ; +; Cell ; ; 14 ; 0.516 ; 16 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.311 ; 3.319 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; FF ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.676 ; 0.514 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; +; 3.759 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.763 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.899 ; 0.136 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.978 ; 0.079 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.983 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.339 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.429 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.434 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.117 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.208 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.214 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.922 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.950 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.956 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.236 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.311 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.311 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.311 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #667: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.566 ; 78 ; 0.127 ; 0.657 ; +; Cell ; ; 14 ; 0.577 ; 18 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.261 ; 3.269 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.919 ; 0.113 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.925 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.079 ; 0.154 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.186 ; 0.107 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.191 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.318 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.439 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.444 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.101 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.194 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.200 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.566 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.594 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.598 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.233 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.261 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #668: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.565 ; 78 ; 0.127 ; 0.657 ; +; Cell ; ; 14 ; 0.577 ; 18 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.260 ; 3.268 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.919 ; 0.113 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.925 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.079 ; 0.154 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.186 ; 0.107 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.191 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.318 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.439 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.444 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.101 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.194 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.200 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.566 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.594 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.598 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.232 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.260 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #669: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.326 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.328 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.918 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.326 ; 3.328 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.300 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; +; 6.326 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; +; 6.326 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; +; 6.326 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #670: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|b_reg_data[30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.797 ; 86 ; 0.108 ; 0.929 ; +; Cell ; ; 12 ; 0.349 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.237 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; +; 6.266 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #671: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.138 ; +; Data Required Time ; 5.426 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.140 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.138 ; 3.140 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22]|sclr ; +; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N1 ; ; vx_d_e_reg|PC_next_out[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #672: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[23] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.138 ; +; Data Required Time ; 5.426 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.140 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.138 ; 3.140 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23]|sclr ; +; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N5 ; ; vx_d_e_reg|PC_next_out[23] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #673: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.138 ; +; Data Required Time ; 5.426 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.140 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.138 ; 3.140 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24]|sclr ; +; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N7 ; ; vx_d_e_reg|PC_next_out[24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #674: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.138 ; +; Data Required Time ; 5.426 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.140 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.138 ; 3.140 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28]|sclr ; +; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N19 ; ; vx_d_e_reg|PC_next_out[28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #675: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.835 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.547 ; 0.006 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[3] ; +; 6.266 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|dataf ; +; 6.293 ; 0.027 ; RR ; CELL ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|combout ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|d ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y159_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #676: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.138 ; +; Data Required Time ; 5.426 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.140 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.138 ; 3.140 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31]|sclr ; +; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N29 ; ; vx_d_e_reg|PC_next_out[31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #677: Setup slack is -0.712 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.307 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.712 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.309 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.881 ; 87 ; 0.106 ; 1.351 ; +; Cell ; ; 12 ; 0.307 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.307 ; 3.309 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.279 ; 1.351 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|dataf ; +; 6.307 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|combout ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|d ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #678: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.310 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.312 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.659 ; 80 ; 0.192 ; 0.681 ; +; Cell ; ; 14 ; 0.531 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.310 ; 3.312 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; +; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.927 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.953 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.959 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.237 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.310 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #679: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.766 ; 84 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.412 ; 12 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.298 ; 3.300 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.561 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.587 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.593 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.192 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.298 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #680: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.834 ; 86 ; 0.119 ; 1.046 ; +; Cell ; ; 14 ; 0.352 ; 11 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.604 ; 0.119 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.631 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.636 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.682 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.708 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.712 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.837 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.861 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.867 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.450 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.479 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.484 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.226 ; 0.742 ; FF ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; +; 6.306 ; 0.080 ; FF ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #681: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.837 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.444 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.479 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.277 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; +; 6.304 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #682: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.295 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.297 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.832 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.295 ; 3.297 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.520 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.267 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; +; 6.295 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #683: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.258 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.563 ; 78 ; 0.127 ; 0.657 ; +; Cell ; ; 14 ; 0.577 ; 18 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.258 ; 3.266 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.919 ; 0.113 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.925 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.079 ; 0.154 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.186 ; 0.107 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.191 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.318 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.439 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.444 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.101 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.194 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.200 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.566 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.594 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.598 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.230 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.258 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #684: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.310 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.312 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.792 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.134 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.310 ; 3.312 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.420 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.451 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.456 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.176 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; +; 6.310 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #685: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.295 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.297 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.823 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.354 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.295 ; 3.297 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.396 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.423 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.427 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.202 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; +; 6.295 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; +; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; +; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #686: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.303 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.305 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.862 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.323 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.303 ; 3.305 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.567 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.224 ; 0.657 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|datac ; +; 6.303 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~773|combout ; +; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|d ; +; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #687: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|PC_next_out[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.126 ; +; Data Required Time ; 5.415 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.128 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.740 ; 88 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.268 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.126 ; 3.128 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.297 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.126 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; +; 6.126 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.415 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #688: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.313 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.321 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.712 ; 82 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.484 ; 15 ; 0.000 ; 0.090 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.313 ; 3.321 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.228 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.942 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.972 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.978 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.238 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.313 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.313 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #689: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.702 ; 82 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.479 ; 14 ; 0.000 ; 0.090 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.298 ; 3.306 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.228 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.504 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.530 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.536 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.224 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.298 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #690: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.814 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.360 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.501 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.530 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.536 ; 0.006 ; FF ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; +; 6.267 ; 0.731 ; FF ; IC ; 1 ; MLABCELL_X94_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~655|dataf ; +; 6.293 ; 0.026 ; FF ; CELL ; 1 ; MLABCELL_X94_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~655|combout ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15]|d ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.164 ; ; uTsu ; 1 ; FF_X94_Y164_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #691: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.138 ; +; Data Required Time ; 5.427 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.140 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.669 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.138 ; 3.140 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.138 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25]|sclr ; +; 6.138 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.427 ; 0.022 ; ; uTsu ; 1 ; FF_X80_Y155_N11 ; ; vx_d_e_reg|PC_next_out[25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #692: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.312 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.314 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.853 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.312 ; 3.314 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.285 ; 0.687 ; RR ; IC ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|dataf ; +; 6.312 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|combout ; +; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|d ; +; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y144_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #693: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.311 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.313 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.851 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.311 ; 3.313 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.545 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.284 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|dataf ; +; 6.311 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|combout ; +; 6.311 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|d ; +; 6.311 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X102_Y161_N4 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #694: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++----------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.536 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+-------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.696 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.432 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.165 ; 0.750 ; FF ; IC ; 1 ; LABCELL_X79_Y151_N57 ; High Speed ; vx_d_e_reg|i385~81|datad ; +; 6.247 ; 0.082 ; FR ; CELL ; 2 ; LABCELL_X79_Y151_N57 ; High Speed ; vx_d_e_reg|i385~81|combout ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE|d ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.536 ; 0.150 ; ; uTsu ; 1 ; FF_X79_Y151_N58 ; ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #695: Setup slack is -0.711 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.297 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.711 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.299 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.775 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.403 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.297 ; 3.299 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.393 ; 0.476 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.467 ; 0.074 ; RF ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.471 ; 0.004 ; FF ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.270 ; 0.799 ; FF ; IC ; 1 ; LABCELL_X95_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~870|dataf ; +; 6.297 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X95_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~870|combout ; +; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6]|d ; +; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.163 ; ; uTsu ; 1 ; FF_X95_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #696: Setup slack is -0.710 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.309 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.710 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.311 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.750 ; 83 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.439 ; 13 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.309 ; 3.311 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.926 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.952 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.958 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.236 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.309 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.309 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.309 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #697: Setup slack is -0.710 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.167 ; +; Data Required Time ; 5.457 ; +; Slack ; -0.710 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.169 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.675 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.167 ; 3.169 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.167 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|sload ; +; 6.167 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.457 ; 0.014 ; ; uTsu ; 1 ; FF_X73_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #698: Setup slack is -0.710 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.291 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.710 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.293 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.833 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.291 ; 3.293 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.405 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; +; 5.485 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; +; 5.490 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; +; 6.263 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; +; 6.291 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; +; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; +; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #699: Setup slack is -0.710 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.315 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.710 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.317 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.910 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.315 ; 3.317 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.288 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; +; 6.315 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; +; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; +; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #700: Setup slack is -0.710 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.710 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.803 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.383 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.430 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.507 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.279 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; +; 6.306 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #701: Setup slack is -0.710 (VIOLATED) +=============================================================================== ++----------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.710 (VIOLATED) ; ++--------------------+-------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.777 ; 85 ; 0.108 ; 0.910 ; +; Cell ; ; 12 ; 0.368 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.236 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; +; 6.264 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|d ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #702: Setup slack is -0.710 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.710 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.832 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.356 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.273 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; +; 5.302 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; +; 5.306 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; +; 6.214 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; +; 6.306 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #703: Setup slack is -0.710 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|PC_next_out[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.126 ; +; Data Required Time ; 5.416 ; +; Slack ; -0.710 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.128 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.740 ; 88 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.268 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.126 ; 3.128 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.297 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.126 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; +; 6.126 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.416 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #704: Setup slack is -0.710 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.710 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.929 ; 89 ; 0.114 ; 1.378 ; +; Cell ; ; 12 ; 0.255 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.274 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.304 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #705: Setup slack is -0.709 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.302 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.709 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.304 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.856 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.302 ; 3.304 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.442 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.473 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.477 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.275 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; +; 6.302 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; +; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; +; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #706: Setup slack is -0.709 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|b_reg_data[24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.709 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.777 ; 85 ; 0.108 ; 0.910 ; +; Cell ; ; 12 ; 0.368 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.236 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; +; 6.264 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|d ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N17 ; ; vx_d_e_reg|b_reg_data[24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #707: Setup slack is -0.709 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.309 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.709 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.311 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.901 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.309 ; 3.311 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.474 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.502 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.507 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.282 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.309 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; +; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #708: Setup slack is -0.709 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.292 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.709 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.294 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.860 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.292 ; 3.294 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.410 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.437 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.443 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.265 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; +; 6.292 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #709: Setup slack is -0.709 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.302 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.709 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.304 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.913 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.302 ; 3.304 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.276 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|d ; +; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y162_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #710: Setup slack is -0.709 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_f_d_reg|curr_PC[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.174 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.709 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.176 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.766 ; 87 ; 0.119 ; 1.297 ; +; Cell ; ; 10 ; 0.290 ; 9 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.174 ; 3.176 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.510 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.844 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.872 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.174 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|ena ; +; 6.174 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N38 ; ; vx_f_d_reg|curr_PC[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #711: Setup slack is -0.709 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_f_d_reg|curr_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.174 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.709 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.176 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.766 ; 87 ; 0.119 ; 1.297 ; +; Cell ; ; 10 ; 0.290 ; 9 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.174 ; 3.176 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.510 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.844 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.872 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.174 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|ena ; +; 6.174 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N32 ; ; vx_f_d_reg|curr_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #712: Setup slack is -0.709 (VIOLATED) +=============================================================================== ++---------------------------------------------+ +; Path Summary ; ++--------------------+------------------------+ +; Property ; Value ; ++--------------------+------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.179 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.709 (VIOLATED) ; ++--------------------+------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.181 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.625 ; 83 ; 0.163 ; 1.398 ; +; Cell ; ; 10 ; 0.435 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.179 ; 3.181 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 4.696 ; 0.163 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|datac ; +; 4.776 ; 0.080 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.781 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.179 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.179 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #713: Setup slack is -0.709 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.300 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.709 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.302 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.843 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.300 ; 3.302 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.546 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.273 ; 0.727 ; RR ; IC ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|dataf ; +; 6.300 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|combout ; +; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|d ; +; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y162_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #714: Setup slack is -0.709 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.300 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.709 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.302 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.840 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.300 ; 3.302 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.543 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.272 ; 0.729 ; RR ; IC ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|dataf ; +; 6.300 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|combout ; +; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|d ; +; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y161_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #715: Setup slack is -0.709 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.308 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.709 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.310 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.832 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.357 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.308 ; 3.310 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.493 ; 0.575 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.519 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.524 ; 0.005 ; FF ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.281 ; 0.757 ; FF ; IC ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|dataf ; +; 6.308 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|combout ; +; 6.308 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|d ; +; 6.308 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X108_Y157_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #716: Setup slack is -0.708 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.708 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.850 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.438 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.515 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.520 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; +; 6.277 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; +; 6.304 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #717: Setup slack is -0.708 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|b_reg_data[19] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.262 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.708 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.264 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.775 ; 85 ; 0.108 ; 0.908 ; +; Cell ; ; 12 ; 0.368 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.262 ; 3.264 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.234 ; 0.908 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|dataf ; +; 6.262 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|combout ; +; 6.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|d ; +; 6.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N22 ; ; vx_d_e_reg|b_reg_data[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #718: Setup slack is -0.708 (VIOLATED) +=============================================================================== ++--------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.309 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.708 (VIOLATED) ; ++--------------------+-----------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.311 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.901 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.309 ; 3.311 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.474 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.502 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.507 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.282 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.309 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; +; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #719: Setup slack is -0.708 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.302 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.708 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.304 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.913 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.302 ; 3.304 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.276 ; 0.708 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|dataf ; +; 6.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~777|combout ; +; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|d ; +; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.183 ; ; uTsu ; 1 ; FF_X90_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #720: Setup slack is -0.708 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.178 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.708 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.020 ; ; ; ; ; ; +; Data Delay ; 3.186 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.640 ; 83 ; 0.163 ; 1.398 ; +; Cell ; ; 10 ; 0.419 ; 13 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.178 ; 3.186 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 4.695 ; 0.163 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|datac ; +; 4.775 ; 0.080 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.780 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.178 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.178 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #721: Setup slack is -0.708 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.708 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.826 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.366 ; 0.440 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; +; 5.394 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; +; 5.398 ; 0.004 ; FF ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; +; 6.276 ; 0.878 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; +; 6.306 ; 0.030 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #722: Setup slack is -0.708 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.319 ; +; Data Required Time ; 5.611 ; +; Slack ; -0.708 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.321 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.760 ; 83 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.440 ; 13 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.319 ; 3.321 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.470 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.547 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.551 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.239 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|datac ; +; 6.319 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|combout ; +; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|d ; +; 6.319 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #723: Setup slack is -0.708 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.296 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.708 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.298 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.836 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.296 ; 3.298 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.545 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.269 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|dataf ; +; 6.296 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|combout ; +; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|d ; +; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #724: Setup slack is -0.708 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.551 ; +; Slack ; -0.708 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.078 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.716 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.424 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.185 ; 0.770 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N18 ; High Speed ; vx_d_e_reg|i385~45|datae ; +; 6.259 ; 0.074 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N18 ; High Speed ; vx_d_e_reg|i385~45|combout ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14]|d ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14]|clk ; +; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14] ; +; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.551 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y152_N19 ; ; vx_d_e_reg|b_reg_data[14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #725: Setup slack is -0.707 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[12] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.167 ; +; Data Required Time ; 5.460 ; +; Slack ; -0.707 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.169 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.675 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.167 ; 3.169 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.167 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|sload ; +; 6.167 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.460 ; 0.017 ; ; uTsu ; 1 ; FF_X73_Y161_N46 ; ; vx_fetch|VX_Warp_zero|real_PC[12] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #726: Setup slack is -0.707 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|b_reg_data[31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.707 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.772 ; 85 ; 0.108 ; 0.905 ; +; Cell ; ; 12 ; 0.369 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.231 ; 0.905 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|dataf ; +; 6.260 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|combout ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|d ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N25 ; ; vx_d_e_reg|b_reg_data[31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #727: Setup slack is -0.707 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.321 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.707 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.323 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.899 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.321 ; 3.323 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.295 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; +; 6.321 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; +; 6.321 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; +; 6.321 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #728: Setup slack is -0.707 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.177 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.707 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.179 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.725 ; 86 ; 0.110 ; 1.398 ; +; Cell ; ; 10 ; 0.333 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.177 ; 3.179 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.412 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.746 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.774 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.779 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.177 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.177 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #729: Setup slack is -0.707 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.707 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.929 ; 89 ; 0.114 ; 1.378 ; +; Cell ; ; 12 ; 0.255 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.274 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.304 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #730: Setup slack is -0.707 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.301 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.707 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.303 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.823 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.301 ; 3.303 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.491 ; 0.573 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.518 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.524 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.274 ; 0.750 ; FF ; IC ; 1 ; LABCELL_X93_Y144_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1020|dataf ; +; 6.301 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X93_Y144_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1020|combout ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28]|d ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y144_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #731: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.642 ; 81 ; 0.116 ; 0.686 ; +; Cell ; ; 14 ; 0.495 ; 15 ; 0.000 ; 0.114 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.254 ; 3.262 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; +; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.583 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.611 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.615 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.227 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.254 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #732: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.316 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.318 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.818 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.380 ; 11 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.316 ; 3.318 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.329 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.077 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; +; 6.103 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; +; 6.109 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; +; 6.256 ; 0.147 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; +; 6.316 ; 0.060 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; +; 6.316 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; +; 6.316 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #733: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.315 ; +; Data Required Time ; 5.609 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.317 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.765 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.430 ; 13 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.315 ; 3.317 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.076 ; 0.769 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; +; 6.105 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; +; 6.111 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; +; 6.239 ; 0.128 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; +; 6.315 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; +; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; +; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #734: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.167 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.169 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.675 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.167 ; 3.169 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.167 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|sload ; +; 6.167 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.018 ; ; uTsu ; 1 ; FF_X73_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #735: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.309 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.048 ; ; ; ; ; ; +; Data Delay ; 3.311 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.905 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.284 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.309 ; 3.311 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.454 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.481 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.485 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.281 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; +; 6.309 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; +; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; +; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; +; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #736: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.312 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.314 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.907 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.312 ; 3.314 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.479 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.506 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.512 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.285 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; +; 6.312 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; +; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; +; 6.312 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #737: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.310 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.312 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.794 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.310 ; 3.312 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.337 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; +; 5.367 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; +; 5.371 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; +; 6.224 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; +; 6.310 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; +; 6.310 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #738: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_address[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.218 ; +; Data Required Time ; 5.512 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.121 ; ; ; ; ; ; +; Data Delay ; 3.220 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.692 ; 84 ; 0.119 ; 0.821 ; +; Cell ; ; 12 ; 0.406 ; 13 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.218 ; 3.220 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.362 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.145 ; 0.783 ; RR ; IC ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|datae ; +; 6.218 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|combout ; +; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|d ; +; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.377 ; 2.877 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; +; 5.377 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.347 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.512 ; 0.165 ; ; uTsu ; 1 ; FF_X49_Y149_N28 ; ; vx_d_e_reg|csr_address[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #739: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[3] ; +; To Node ; vx_e_m_reg|csr_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.322 ; +; Data Required Time ; 5.616 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.009 ; ; ; ; ; ; +; Data Delay ; 3.333 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.860 ; 86 ; 0.122 ; 0.795 ; +; Cell ; ; 16 ; 0.352 ; 11 ; 0.000 ; 0.063 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]|clk ; +; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3] ; +; 6.322 ; 3.333 ; ; ; ; ; ; data path ; +; 3.110 ; 0.121 ; RR ; uTco ; 1 ; FF_X51_Y153_N38 ; ; vx_csr_handler|decode_csr_address[3]|q ; +; 3.173 ; 0.063 ; RR ; CELL ; 686 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]~la_lab/laboutb[5] ; +; 3.968 ; 0.795 ; RR ; IC ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|dataf ; +; 3.997 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|combout ; +; 4.002 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144~la_mlab/laboutb[8] ; +; 4.429 ; 0.427 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|dataf ; +; 4.455 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; +; 4.815 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; +; 4.843 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; +; 4.849 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; +; 5.112 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; +; 5.171 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; +; 5.177 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; +; 5.300 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; +; 5.363 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.367 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.142 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.169 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.174 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.296 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; +; 6.322 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; +; 6.322 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; +; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; +; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.616 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #740: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.305 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.307 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.773 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.412 ; 12 ; 0.000 ; 0.134 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.305 ; 3.307 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.415 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.446 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.451 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.171 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; +; 6.305 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; +; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; +; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #741: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.290 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.292 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.804 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.366 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.290 ; 3.292 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.391 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.418 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.422 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.197 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; +; 6.290 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; +; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; +; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #742: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.839 ; 86 ; 0.127 ; 1.275 ; +; Cell ; ; 12 ; 0.345 ; 10 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.184 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.304 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #743: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.321 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.323 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.798 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.321 ; 3.323 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.455 ; 0.538 ; RR ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.530 ; 0.075 ; RF ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.534 ; 0.004 ; FF ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.294 ; 0.760 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|dataf ; +; 6.321 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; +; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; +; 6.321 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #744: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[22] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.340 ; +; Data Required Time ; 5.634 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.093 ; ; ; ; ; ; +; Data Delay ; 2.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.314 ; 76 ; 0.000 ; 2.314 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.897 ; 83 ; 0.361 ; 0.872 ; +; Cell ; ; 8 ; 0.246 ; 11 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.140 ; 6 ; 0.140 ; 0.140 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.057 ; 3.057 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.057 ; 2.314 ; FF ; IC ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]|clk ; +; 4.057 ; 0.000 ; FR ; CELL ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; +; 6.340 ; 2.283 ; ; ; ; ; ; data path ; +; 4.197 ; 0.140 ; FF ; uTco ; 1 ; FF_X92_Y141_N41 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]|q ; +; 4.266 ; 0.069 ; FF ; CELL ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[7] ; +; 5.138 ; 0.872 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|datad ; +; 5.212 ; 0.074 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; +; 5.218 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; +; 5.882 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; +; 5.910 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; +; 5.916 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[13] ; +; 6.277 ; 0.361 ; FF ; IC ; 1 ; LABCELL_X75_Y157_N36 ; High Speed ; vx_fetch|VX_Warp_one|i199~17|datae ; +; 6.340 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X75_Y157_N36 ; High Speed ; vx_fetch|VX_Warp_one|i199~17|combout ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22]|d ; +; 6.340 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y157_N37 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[22] ; +; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.634 ; 0.200 ; ; uTsu ; 1 ; FF_X75_Y157_N37 ; ; vx_fetch|VX_Warp_one|real_PC[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #745: Setup slack is -0.706 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[22] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.339 ; +; Data Required Time ; 5.633 ; +; Slack ; -0.706 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.093 ; ; ; ; ; ; +; Data Delay ; 2.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.314 ; 76 ; 0.000 ; 2.314 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.896 ; 83 ; 0.360 ; 0.872 ; +; Cell ; ; 8 ; 0.246 ; 11 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.140 ; 6 ; 0.140 ; 0.140 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.057 ; 3.057 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.057 ; 2.314 ; FF ; IC ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]|clk ; +; 4.057 ; 0.000 ; FR ; CELL ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22] ; +; 6.339 ; 2.282 ; ; ; ; ; ; data path ; +; 4.197 ; 0.140 ; FF ; uTco ; 1 ; FF_X92_Y141_N41 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]|q ; +; 4.266 ; 0.069 ; FF ; CELL ; 1 ; FF_X92_Y141_N41 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[7] ; +; 5.138 ; 0.872 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|datad ; +; 5.212 ; 0.074 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; +; 5.218 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; +; 5.882 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; +; 5.910 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; +; 5.916 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[13] ; +; 6.276 ; 0.360 ; FF ; IC ; 1 ; LABCELL_X75_Y157_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~19|datae ; +; 6.339 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X75_Y157_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~19|combout ; +; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22]|d ; +; 6.339 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y157_N43 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[22] ; +; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.633 ; 0.199 ; ; uTsu ; 1 ; FF_X75_Y157_N43 ; ; vx_fetch|VX_Warp_two|real_PC[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #746: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.307 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.309 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.653 ; 80 ; 0.192 ; 0.690 ; +; Cell ; ; 14 ; 0.534 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.307 ; 3.309 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; +; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.936 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.965 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.971 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.234 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.307 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.307 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.307 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #747: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.315 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.317 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.765 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.430 ; 13 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.315 ; 3.317 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.307 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.066 ; 0.759 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; +; 6.093 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; +; 6.099 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; +; 6.237 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; +; 6.315 ; 0.078 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; +; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; +; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #748: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.682 ; 82 ; 0.117 ; 0.710 ; +; Cell ; ; 14 ; 0.454 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.253 ; 3.261 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.582 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.610 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.614 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.226 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.253 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #749: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.650 ; 81 ; 0.133 ; 0.657 ; +; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.254 ; 3.262 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.687 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; +; 3.763 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.767 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.900 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.983 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.988 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.339 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.432 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.437 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.094 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.187 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.193 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.559 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.587 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.591 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.226 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.254 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #750: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.649 ; 81 ; 0.133 ; 0.657 ; +; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.253 ; 3.261 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.687 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; +; 3.763 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.767 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.900 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.983 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.988 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.339 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.432 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.437 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.094 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.187 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.193 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.559 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.587 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.591 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.225 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.253 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #751: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.288 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.290 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.880 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.288 ; 3.290 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.477 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.509 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.260 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; +; 6.288 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #752: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.792 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.420 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.451 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.456 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.176 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; +; 6.306 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #753: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.301 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.303 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.813 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.368 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.301 ; 3.303 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.834 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.268 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; +; 5.297 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; +; 5.301 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; +; 6.209 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; +; 6.301 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #754: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.786 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.388 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.398 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; +; 5.476 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; +; 5.480 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[10] ; +; 6.266 ; 0.786 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~636|dataf ; +; 6.293 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~636|combout ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28]|d ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #755: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.160 ; +; Data Required Time ; 5.455 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.162 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.658 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.160 ; 3.162 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.160 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5]|sload ; +; 6.160 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.455 ; 0.016 ; ; uTsu ; 1 ; FF_X71_Y160_N26 ; ; vx_fetch|VX_Warp_zero|real_PC[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #756: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.160 ; +; Data Required Time ; 5.455 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.162 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.658 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.160 ; 3.162 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.160 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]|sload ; +; 6.160 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.455 ; 0.016 ; ; uTsu ; 1 ; FF_X71_Y160_N7 ; ; vx_fetch|VX_Warp_zero|real_PC[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #757: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.166 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.024 ; ; ; ; ; ; +; Data Delay ; 3.168 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.664 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.199 ; 80 ; 0.000 ; 2.199 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.166 ; 3.168 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.166 ; 0.256 ; FF ; IC ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11]|sload ; +; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.474 ; 2.974 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.264 ; 2.199 ; RR ; IC ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11]|clk ; +; 5.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11] ; +; 5.474 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.444 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.017 ; ; uTsu ; 1 ; FF_X72_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #758: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[0] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.300 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.110 ; ; ; ; ; ; +; Data Delay ; 2.227 ; ; ; ; ; ; +; Number of Logic Levels ; ; 2 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 2 ; 1.828 ; 82 ; 0.876 ; 0.952 ; +; Cell ; ; 6 ; 0.215 ; 10 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.184 ; 8 ; 0.184 ; 0.184 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]|clk ; +; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; +; 6.300 ; 2.227 ; ; ; ; ; ; data path ; +; 4.257 ; 0.184 ; FF ; uTco ; 1 ; FF_X102_Y159_N56 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]|q ; +; 4.301 ; 0.044 ; FF ; CELL ; 3 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]~la_lab/laboutb[17] ; +; 5.253 ; 0.952 ; FF ; IC ; 1 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97|datad ; +; 5.334 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97|combout ; +; 5.338 ; 0.004 ; FF ; CELL ; 3 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97~la_lab/laboutt[16] ; +; 6.214 ; 0.876 ; FF ; IC ; 1 ; MLABCELL_X69_Y156_N27 ; High Speed ; vx_fetch|VX_Warp_one|i199~0|datae ; +; 6.300 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X69_Y156_N27 ; High Speed ; vx_fetch|VX_Warp_one|i199~0|combout ; +; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y156_N28 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[0]|d ; +; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y156_N28 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[0] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.463 ; 2.963 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X69_Y156_N28 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[0]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y156_N28 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[0] ; +; 5.463 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.433 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.162 ; ; uTsu ; 1 ; FF_X69_Y156_N28 ; ; vx_fetch|VX_Warp_one|real_PC[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #759: Setup slack is -0.705 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.305 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.705 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.307 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.731 ; 83 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.305 ; 3.307 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.494 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.213 ; 0.719 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|datad ; +; 6.305 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|combout ; +; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]|d ; +; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y150_N38 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #760: Setup slack is -0.704 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.704 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.744 ; 83 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.442 ; 13 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.935 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.964 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.970 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.233 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.306 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #761: Setup slack is -0.704 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.257 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.704 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.077 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.759 ; 85 ; 0.108 ; 0.876 ; +; Cell ; ; 12 ; 0.378 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.257 ; 3.259 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.230 ; 0.876 ; FF ; IC ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|dataf ; +; 6.257 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|combout ; +; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|d ; +; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|clk ; +; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; +; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.162 ; ; uTsu ; 1 ; FF_X80_Y149_N44 ; ; vx_d_e_reg|b_reg_data[25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #762: Setup slack is -0.704 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.704 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.785 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.400 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.521 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.221 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; +; 6.304 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #763: Setup slack is -0.704 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.704 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.647 ; 81 ; 0.133 ; 0.657 ; +; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.251 ; 3.259 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.687 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; +; 3.763 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.767 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.900 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.983 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.988 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.339 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.432 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.437 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.094 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.187 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.193 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.559 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.587 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.591 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.223 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.251 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #764: Setup slack is -0.704 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.704 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.882 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.469 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.497 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.502 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.277 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.304 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #765: Setup slack is -0.704 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.291 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.704 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.046 ; ; ; ; ; ; +; Data Delay ; 3.293 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.831 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.177 ; 79 ; 0.000 ; 2.177 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.291 ; 3.293 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.263 ; 0.562 ; RR ; IC ; 1 ; LABCELL_X93_Y149_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~798|dataf ; +; 6.291 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y149_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~798|combout ; +; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30]|d ; +; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.452 ; 2.952 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.242 ; 2.177 ; RR ; IC ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30]|clk ; +; 5.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; +; 5.452 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.422 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y149_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #766: Setup slack is -0.704 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.160 ; +; Data Required Time ; 5.456 ; +; Slack ; -0.704 (VIOLATED) ; ++--------------------+--------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.162 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.658 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.160 ; 3.162 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.160 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE|sload ; +; 6.160 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.456 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y160_N8 ; ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #767: Setup slack is -0.703 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.309 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.703 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.311 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.726 ; 82 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.309 ; 3.311 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.067 ; 0.713 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|dataf ; +; 6.097 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|combout ; +; 6.103 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35~la_mlab/laboutt[9] ; +; 6.233 ; 0.130 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|datae ; +; 6.309 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; +; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; +; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #768: Setup slack is -0.703 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.703 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.298 ; 3.300 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.479 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.508 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.513 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.219 ; 0.706 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; +; 6.298 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #769: Setup slack is -0.703 (VIOLATED) +=============================================================================== ++--------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.703 (VIOLATED) ; ++--------------------+-----------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.882 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.469 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.497 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.502 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.277 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.304 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #770: Setup slack is -0.703 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.290 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.703 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.057 ; ; ; ; ; ; +; Data Delay ; 3.292 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.901 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.166 ; 79 ; 0.000 ; 2.166 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.290 ; 3.292 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.264 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|dataf ; +; 6.290 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y162_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~783|combout ; +; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|d ; +; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.441 ; 2.941 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.231 ; 2.166 ; RR ; IC ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15]|clk ; +; 5.231 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y162_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; +; 5.441 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.411 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y162_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #771: Setup slack is -0.703 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.160 ; +; Data Required Time ; 5.457 ; +; Slack ; -0.703 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.162 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.658 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.160 ; 3.162 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.160 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6]|sload ; +; 6.160 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.457 ; 0.018 ; ; uTsu ; 1 ; FF_X71_Y160_N58 ; ; vx_fetch|VX_Warp_zero|real_PC[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #772: Setup slack is -0.703 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.303 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.703 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.305 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.778 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.303 ; 3.305 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.210 ; 0.612 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|datac ; +; 6.303 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|combout ; +; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|d ; +; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #773: Setup slack is -0.703 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.307 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.703 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.309 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.830 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.307 ; 3.309 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.546 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.572 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.578 ; 0.006 ; FF ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.280 ; 0.702 ; FF ; IC ; 1 ; LABCELL_X108_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~868|dataf ; +; 6.307 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X108_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~868|combout ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4]|d ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #774: Setup slack is -0.702 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.307 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.702 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.309 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.852 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.307 ; 3.309 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.280 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; +; 6.307 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; +; 6.307 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #775: Setup slack is -0.702 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.702 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.775 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.388 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.397 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; +; 5.477 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; +; 5.482 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; +; 6.255 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; +; 6.283 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #776: Setup slack is -0.702 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|b_reg_data[30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.702 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.840 ; 87 ; 0.108 ; 0.929 ; +; Cell ; ; 12 ; 0.298 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.227 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; +; 6.256 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #777: Setup slack is -0.702 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.702 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.923 ; 89 ; 0.114 ; 1.372 ; +; Cell ; ; 12 ; 0.255 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.298 ; 3.300 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.268 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; +; 6.298 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #778: Setup slack is -0.702 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.317 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.702 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.319 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.851 ; 86 ; 0.114 ; 1.300 ; +; Cell ; ; 12 ; 0.346 ; 10 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.317 ; 3.319 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.196 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.317 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.317 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; +; 6.317 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #779: Setup slack is -0.702 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.301 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.702 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.303 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.839 ; 86 ; 0.127 ; 1.275 ; +; Cell ; ; 12 ; 0.342 ; 10 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.301 ; 3.303 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.184 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; +; 6.301 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; +; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; +; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #780: Setup slack is -0.702 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.317 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.702 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.319 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.851 ; 86 ; 0.114 ; 1.300 ; +; Cell ; ; 12 ; 0.346 ; 10 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.317 ; 3.319 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.196 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.317 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.317 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; +; 6.317 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #781: Setup slack is -0.702 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.296 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.702 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.298 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.871 ; 87 ; 0.104 ; 1.378 ; +; Cell ; ; 12 ; 0.305 ; 9 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.296 ; 3.298 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.266 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.296 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; +; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #782: Setup slack is -0.702 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.702 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.682 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.251 ; 3.259 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.143 ; 0.136 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.234 ; 0.091 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.240 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.355 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.381 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.386 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.106 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.184 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.190 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.556 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.584 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.588 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.223 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.251 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #783: Setup slack is -0.702 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.250 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.702 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.681 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.250 ; 3.258 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.143 ; 0.136 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.234 ; 0.091 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.240 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.355 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.381 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.386 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.106 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.184 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.190 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.556 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.584 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.588 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.222 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.250 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #784: Setup slack is -0.702 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.702 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.826 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.366 ; 0.440 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; +; 5.394 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; +; 5.398 ; 0.004 ; FF ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; +; 6.276 ; 0.878 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; +; 6.306 ; 0.030 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #785: Setup slack is -0.702 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_address[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.212 ; +; Data Required Time ; 5.510 ; +; Slack ; -0.702 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.116 ; ; ; ; ; ; +; Data Delay ; 3.220 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 4 ; 2.767 ; 86 ; 0.573 ; 0.870 ; +; Cell ; ; 10 ; 0.328 ; 10 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.212 ; 3.220 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.873 ; 0.688 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|dataa ; +; 3.993 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; +; 3.999 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; +; 4.635 ; 0.636 ; RR ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; +; 4.662 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; +; 4.666 ; 0.004 ; FF ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; +; 5.536 ; 0.870 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N39 ; High Speed ; vx_decode|out_csr_address[0]~5|dataf ; +; 5.562 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N39 ; High Speed ; vx_decode|out_csr_address[0]~5|combout ; +; 5.566 ; 0.004 ; FF ; CELL ; 3 ; LABCELL_X38_Y157_N39 ; High Speed ; vx_decode|out_csr_address[0]~5~la_lab/laboutb[6] ; +; 6.139 ; 0.573 ; FF ; IC ; 1 ; LABCELL_X51_Y153_N18 ; High Speed ; vx_d_e_reg|i498~5|datad ; +; 6.212 ; 0.073 ; FF ; CELL ; 1 ; LABCELL_X51_Y153_N18 ; High Speed ; vx_d_e_reg|i498~5|combout ; +; 6.212 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y153_N19 ; High Speed ; vx_d_e_reg|csr_address[5]|d ; +; 6.212 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y153_N19 ; High Speed ; vx_d_e_reg|csr_address[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.376 ; 2.876 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X51_Y153_N19 ; High Speed ; vx_d_e_reg|csr_address[5]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N19 ; High Speed ; vx_d_e_reg|csr_address[5] ; +; 5.376 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.346 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.510 ; 0.164 ; ; uTsu ; 1 ; FF_X51_Y153_N19 ; ; vx_d_e_reg|csr_address[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #786: Setup slack is -0.702 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[19] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.337 ; +; Data Required Time ; 5.635 ; +; Slack ; -0.702 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.095 ; ; ; ; ; ; +; Data Delay ; 2.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.316 ; 76 ; 0.000 ; 2.316 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.886 ; 83 ; 0.392 ; 0.786 ; +; Cell ; ; 8 ; 0.253 ; 11 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.139 ; 6 ; 0.139 ; 0.139 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.059 ; 3.059 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.059 ; 2.316 ; FF ; IC ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]|clk ; +; 4.059 ; 0.000 ; FR ; CELL ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; +; 6.337 ; 2.278 ; ; ; ; ; ; data path ; +; 4.198 ; 0.139 ; FF ; uTco ; 1 ; FF_X90_Y146_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]|q ; +; 4.267 ; 0.069 ; FF ; CELL ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]~la_mlab/laboutt[15] ; +; 4.975 ; 0.708 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|datae ; +; 5.037 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; +; 5.042 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; +; 5.828 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; +; 5.854 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; +; 5.859 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; +; 6.251 ; 0.392 ; FF ; IC ; 1 ; MLABCELL_X74_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_one|i199~14|datae ; +; 6.337 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X74_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_one|i199~14|combout ; +; 6.337 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19]|d ; +; 6.337 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19] ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19] ; +; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.635 ; 0.201 ; ; uTsu ; 1 ; FF_X74_Y159_N40 ; ; vx_fetch|VX_Warp_one|real_PC[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #787: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.302 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.304 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.850 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.332 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.302 ; 3.304 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.429 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.505 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.509 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.275 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; +; 6.302 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; +; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; +; 6.302 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #788: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.877 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.481 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.255 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; +; 6.282 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #789: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[3] ; +; To Node ; vx_e_m_reg|alu_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.314 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.009 ; ; ; ; ; ; +; Data Delay ; 3.325 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.852 ; 86 ; 0.114 ; 0.795 ; +; Cell ; ; 16 ; 0.352 ; 11 ; 0.000 ; 0.063 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]|clk ; +; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3] ; +; 6.314 ; 3.325 ; ; ; ; ; ; data path ; +; 3.110 ; 0.121 ; RR ; uTco ; 1 ; FF_X51_Y153_N38 ; ; vx_csr_handler|decode_csr_address[3]|q ; +; 3.173 ; 0.063 ; RR ; CELL ; 686 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]~la_lab/laboutb[5] ; +; 3.968 ; 0.795 ; RR ; IC ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|dataf ; +; 3.997 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144|combout ; +; 4.002 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X50_Y167_N42 ; High Speed ; vx_csr_handler|Mux_3~144~la_mlab/laboutb[8] ; +; 4.429 ; 0.427 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|dataf ; +; 4.455 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; +; 4.815 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; +; 4.843 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; +; 4.849 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; +; 5.112 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; +; 5.171 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; +; 5.177 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; +; 5.300 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; +; 5.363 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.367 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.142 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.169 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.174 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.288 ; 0.114 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; +; 6.314 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; +; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; +; 6.314 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; +; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; +; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.163 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #790: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.286 ; +; Data Required Time ; 5.585 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.288 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.814 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.354 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.286 ; 3.288 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.396 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.423 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.427 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.193 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; +; 6.286 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; +; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; +; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #791: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.315 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.317 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.883 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.315 ; 3.317 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.289 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; +; 6.315 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; +; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; +; 6.315 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #792: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.302 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.304 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.852 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.332 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.302 ; 3.304 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.796 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.203 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.230 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.236 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.215 ; 0.979 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|datad ; +; 6.302 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~256|combout ; +; 6.302 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|d ; +; 6.302 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #793: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.679 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.248 ; 3.256 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.143 ; 0.136 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.234 ; 0.091 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.240 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.355 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.381 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.386 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.106 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.184 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.190 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.556 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.584 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.588 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.220 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.248 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #794: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.171 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.020 ; ; ; ; ; ; +; Data Delay ; 3.179 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.626 ; 83 ; 0.138 ; 1.398 ; +; Cell ; ; 10 ; 0.428 ; 13 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.171 ; 3.179 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 4.688 ; 0.163 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|datac ; +; 4.768 ; 0.080 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.773 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.171 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.171 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #795: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.303 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.305 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.823 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.303 ; 3.305 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.502 ; 0.584 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.531 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.536 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.275 ; 0.739 ; FF ; IC ; 1 ; LABCELL_X104_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~718|dataf ; +; 6.303 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X104_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~718|combout ; +; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14]|d ; +; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.166 ; ; uTsu ; 1 ; FF_X104_Y160_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #796: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.821 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.298 ; 3.300 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.322 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.271 ; 0.917 ; FF ; IC ; 1 ; LABCELL_X104_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~263|dataf ; +; 6.298 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X104_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~263|combout ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7]|d ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.163 ; ; uTsu ; 1 ; FF_X104_Y159_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #797: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.288 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.290 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.827 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.288 ; 3.290 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.509 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.541 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.545 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.261 ; 0.716 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~796|dataf ; +; 6.288 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~796|combout ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28]|d ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N38 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #798: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.294 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.296 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.835 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.294 ; 3.296 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 6 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[11] ; +; 6.266 ; 0.666 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~540|dataf ; +; 6.294 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~540|combout ; +; 6.294 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28]|d ; +; 6.294 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #799: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.546 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.696 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.432 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.165 ; 0.750 ; FF ; IC ; 1 ; LABCELL_X79_Y151_N57 ; High Speed ; vx_d_e_reg|i385~81|datad ; +; 6.247 ; 0.082 ; FR ; CELL ; 2 ; LABCELL_X79_Y151_N57 ; High Speed ; vx_d_e_reg|i385~81|combout ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N59 ; High Speed ; vx_d_e_reg|b_reg_data[26]|d ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N59 ; High Speed ; vx_d_e_reg|b_reg_data[26] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X79_Y151_N59 ; High Speed ; vx_d_e_reg|b_reg_data[26]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N59 ; High Speed ; vx_d_e_reg|b_reg_data[26] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.546 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y151_N59 ; ; vx_d_e_reg|b_reg_data[26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #800: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[25] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.334 ; +; Data Required Time ; 5.633 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.107 ; ; ; ; ; ; +; Data Delay ; 2.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.883 ; 83 ; 0.308 ; 0.887 ; +; Cell ; ; 8 ; 0.246 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|clk ; +; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; +; 6.334 ; 2.262 ; ; ; ; ; ; data path ; +; 4.205 ; 0.133 ; FF ; uTco ; 1 ; FF_X108_Y149_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|q ; +; 4.249 ; 0.044 ; FF ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]~la_lab/laboutb[6] ; +; 4.937 ; 0.688 ; FF ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|datae ; +; 5.021 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; +; 5.025 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; +; 5.912 ; 0.887 ; FF ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; +; 5.937 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; +; 5.942 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; +; 6.250 ; 0.308 ; FF ; IC ; 1 ; LABCELL_X73_Y157_N24 ; High Speed ; vx_fetch|VX_Warp_two|i199~22|datac ; +; 6.334 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X73_Y157_N24 ; High Speed ; vx_fetch|VX_Warp_two|i199~22|combout ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y157_N26 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[25]|d ; +; 6.334 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y157_N26 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[25] ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X73_Y157_N26 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[25]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y157_N26 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[25] ; +; 5.465 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.633 ; 0.198 ; ; uTsu ; 1 ; FF_X73_Y157_N26 ; ; vx_fetch|VX_Warp_two|real_PC[25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #801: Setup slack is -0.701 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.295 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.701 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.297 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.385 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.295 ; 3.297 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.461 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.537 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.541 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.269 ; 0.728 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~831|dataf ; +; 6.295 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~831|combout ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31]|d ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #802: Setup slack is -0.700 (VIOLATED) +=============================================================================== ++-----------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------+ +; Property ; Value ; ++--------------------+--------------------------+ +; From Node ; vx_d_e_reg|a_reg_data[9] ; +; To Node ; vx_e_m_reg|alu_result[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.201 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.700 (VIOLATED) ; ++--------------------+--------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.320 ; 79 ; 0.000 ; 2.320 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.586 ; 79 ; 0.120 ; 0.774 ; +; Cell ; ; 16 ; 0.434 ; 13 ; 0.000 ; 0.081 ; +; uTco ; ; 1 ; 0.234 ; 7 ; 0.234 ; 0.234 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.947 ; 2.947 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.947 ; 2.320 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; +; 2.947 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; +; 6.201 ; 3.254 ; ; ; ; ; ; data path ; +; 3.181 ; 0.234 ; RR ; uTco ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9]|q ; +; 3.245 ; 0.064 ; RR ; CELL ; 15 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]~la_lab/laboutb[2] ; +; 4.019 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30|datae ; +; 4.092 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30|combout ; +; 4.098 ; 0.006 ; RR ; CELL ; 3 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30~la_mlab/laboutt[13] ; +; 4.236 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X74_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~33|dataf ; +; 4.263 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X74_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~33|combout ; +; 4.269 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X74_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~33~la_mlab/laboutb[17] ; +; 4.389 ; 0.120 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datad ; +; 4.470 ; 0.081 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; +; 4.474 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; +; 4.691 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; +; 4.766 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.770 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.203 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.230 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.236 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.393 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; +; 5.421 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; +; 5.426 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; +; 6.173 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; +; 6.201 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; +; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; +; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #803: Setup slack is -0.700 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.700 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 84 ; 0.108 ; 0.787 ; +; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.026 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.053 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.059 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.230 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.306 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #804: Setup slack is -0.700 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.700 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.873 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.494 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.526 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.531 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; +; 6.255 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; +; 6.282 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #805: Setup slack is -0.700 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.291 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.700 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.293 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.887 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.284 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.291 ; 3.293 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.514 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.264 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; +; 6.291 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; +; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; +; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #806: Setup slack is -0.700 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.305 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.700 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.307 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.838 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.305 ; 3.307 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.488 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.517 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.522 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.218 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; +; 6.305 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; +; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; +; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #807: Setup slack is -0.700 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.296 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.700 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.298 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.792 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.384 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.296 ; 3.298 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.430 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.507 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.512 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; +; 6.269 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; +; 6.296 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; +; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; +; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #808: Setup slack is -0.700 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.700 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.818 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.447 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.474 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.480 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.256 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; +; 6.283 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #809: Setup slack is -0.700 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.700 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.861 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.472 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.499 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.504 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.255 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; +; 6.283 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #810: Setup slack is -0.700 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.301 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.700 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.303 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.773 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.408 ; 12 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.301 ; 3.303 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.415 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.446 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.451 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.171 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; +; 6.301 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; +; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; +; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #811: Setup slack is -0.700 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.299 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.700 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.301 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.757 ; 84 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.423 ; 13 ; 0.000 ; 0.134 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.299 ; 3.301 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.409 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.440 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.445 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.165 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; +; 6.299 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; +; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; +; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #812: Setup slack is -0.700 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.284 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.700 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.286 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.788 ; 85 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.377 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.284 ; 3.286 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.385 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.412 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.416 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.191 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; +; 6.284 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; +; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; +; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #813: Setup slack is -0.700 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.700 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.839 ; 86 ; 0.127 ; 1.275 ; +; Cell ; ; 12 ; 0.345 ; 10 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.184 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.304 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #814: Setup slack is -0.700 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.305 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.700 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.307 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.731 ; 83 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.305 ; 3.307 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.494 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.213 ; 0.719 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|datad ; +; 6.305 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|combout ; +; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE|d ; +; 6.305 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y150_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #815: Setup slack is -0.699 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.699 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.755 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.346 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.426 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.430 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.244 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; +; 6.271 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #816: Setup slack is -0.699 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.295 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.699 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.297 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.797 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.379 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.295 ; 3.297 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.262 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; +; 5.291 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; +; 5.295 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; +; 6.203 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; +; 6.295 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #817: Setup slack is -0.699 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.314 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.699 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.316 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.851 ; 86 ; 0.114 ; 1.300 ; +; Cell ; ; 12 ; 0.343 ; 10 ; 0.000 ; 0.118 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.314 ; 3.316 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.196 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|datab ; +; 6.314 ; 0.118 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; +; 6.314 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; +; 6.314 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #818: Setup slack is -0.699 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.296 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.699 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.298 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.871 ; 87 ; 0.104 ; 1.378 ; +; Cell ; ; 12 ; 0.305 ; 9 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.296 ; 3.298 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.266 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.296 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; +; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #819: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 84 ; 0.108 ; 0.787 ; +; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.026 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.053 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.059 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.230 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.306 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; +; 6.306 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #820: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.296 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.298 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.889 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.296 ; 3.298 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.488 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.517 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.522 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.269 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|dataf ; +; 6.296 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|combout ; +; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|d ; +; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #821: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.292 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.294 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.886 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.292 ; 3.294 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.265 ; 0.596 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|dataf ; +; 6.292 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|combout ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|d ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #822: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.309 ; +; Data Required Time ; 5.611 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.311 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.901 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.309 ; 3.311 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.281 ; 0.770 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|dataf ; +; 6.309 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|combout ; +; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|d ; +; 6.309 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #823: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.308 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.310 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.901 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.308 ; 3.310 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.482 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.280 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|dataf ; +; 6.308 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|combout ; +; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|d ; +; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.164 ; ; uTsu ; 1 ; FF_X104_Y146_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #824: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.832 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.298 ; 3.300 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.211 ; 0.645 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|datad ; +; 6.298 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #825: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.301 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.048 ; ; ; ; ; ; +; Data Delay ; 3.303 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.847 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.301 ; 3.303 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.446 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.473 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.477 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.273 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; +; 6.301 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; +; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #826: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.306 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.849 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.304 ; 3.306 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.471 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.498 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.504 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.277 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; +; 6.304 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; +; 6.304 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #827: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.837 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.445 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.478 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.254 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; +; 6.281 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #828: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.297 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.299 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.830 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.297 ; 3.299 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.446 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.473 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.479 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.269 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; +; 6.297 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; +; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; +; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #829: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.291 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.293 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.827 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.291 ; 3.293 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.431 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.462 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.466 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.264 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; +; 6.291 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; +; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; +; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #830: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.873 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.291 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.474 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.502 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.507 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.254 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; +; 6.282 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #831: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.866 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.298 ; 3.300 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.463 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.491 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.496 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.271 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.298 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #832: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_f_d_reg|curr_PC[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.166 ; +; Data Required Time ; 5.468 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.028 ; ; ; ; ; ; +; Data Delay ; 3.168 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.722 ; 86 ; 0.119 ; 1.282 ; +; Cell ; ; 10 ; 0.325 ; 10 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.166 ; 3.168 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.517 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.851 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.879 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.884 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.166 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|ena ; +; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; +; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N44 ; ; vx_f_d_reg|curr_PC[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #833: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_f_d_reg|curr_PC[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.166 ; +; Data Required Time ; 5.468 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.028 ; ; ; ; ; ; +; Data Delay ; 3.168 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.722 ; 86 ; 0.119 ; 1.282 ; +; Cell ; ; 10 ; 0.325 ; 10 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.166 ; 3.168 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.517 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.851 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.879 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.884 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.166 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|ena ; +; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; +; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N25 ; ; vx_f_d_reg|curr_PC[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #834: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.296 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.298 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.781 ; 84 ; 0.104 ; 1.275 ; +; Cell ; ; 12 ; 0.395 ; 12 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.296 ; 3.298 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.176 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.296 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #835: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.285 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.287 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.824 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.285 ; 3.287 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; +; 6.258 ; 0.696 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~604|dataf ; +; 6.285 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~604|combout ; +; 6.285 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28]|d ; +; 6.285 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #836: Setup slack is -0.698 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.698 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.761 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.418 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.298 ; 3.300 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.491 ; 0.573 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.518 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.524 ; 0.006 ; FF ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.212 ; 0.688 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1003|datad ; +; 6.298 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X107_Y158_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1003|combout ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11]|d ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #837: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.663 ; 82 ; 0.127 ; 0.734 ; +; Cell ; ; 14 ; 0.464 ; 14 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.246 ; 3.254 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; +; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.091 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.171 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.176 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.303 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.424 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.429 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.086 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.179 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.185 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.551 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.579 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.583 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.218 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.246 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #838: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.245 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.253 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.662 ; 82 ; 0.127 ; 0.734 ; +; Cell ; ; 14 ; 0.464 ; 14 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.245 ; 3.253 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; +; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.091 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.171 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.176 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.303 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.424 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.429 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.086 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.179 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.185 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.551 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.579 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.583 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.217 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.245 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #839: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++----------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; To Node ; vx_e_m_reg|alu_result[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.198 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+-------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.087 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.325 ; 79 ; 0.000 ; 2.325 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.572 ; 79 ; 0.120 ; 0.863 ; +; Cell ; ; 16 ; 0.492 ; 15 ; 0.000 ; 0.132 ; +; uTco ; ; 1 ; 0.182 ; 6 ; 0.182 ; 0.182 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.952 ; 2.952 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.952 ; 2.325 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; +; 2.952 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; 6.198 ; 3.246 ; ; ; ; ; ; data path ; +; 3.134 ; 0.182 ; FF ; uTco ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|q ; +; 3.178 ; 0.044 ; FF ; CELL ; 4 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE~la_lab/laboutt[10] ; +; 4.041 ; 0.863 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~44|dataf ; +; 4.070 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~44|combout ; +; 4.075 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~44~la_mlab/laboutb[4] ; +; 4.195 ; 0.120 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~45|datac ; +; 4.281 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~45|combout ; +; 4.287 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~45~la_mlab/laboutb[16] ; +; 4.419 ; 0.132 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|datac ; +; 4.505 ; 0.086 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|combout ; +; 4.511 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46~la_mlab/laboutt[8] ; +; 4.631 ; 0.120 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|dataa ; +; 4.763 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.767 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.200 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.227 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.233 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.390 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; +; 5.418 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; +; 5.423 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; +; 6.170 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; +; 6.198 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; +; 6.198 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; +; 6.198 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #840: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.609 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.806 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.329 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.089 ; 0.760 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; +; 6.118 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; +; 6.124 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; +; 6.247 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; +; 6.306 ; 0.059 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #841: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.245 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.765 ; 85 ; 0.116 ; 0.788 ; +; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.245 ; 3.247 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.574 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.602 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.606 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.218 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.245 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #842: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.296 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.298 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.740 ; 83 ; 0.110 ; 0.788 ; +; Cell ; ; 14 ; 0.437 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.296 ; 3.298 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.913 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.939 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.945 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.223 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.296 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #843: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.158 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.160 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.158 ; 3.160 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|sload ; +; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N4 ; ; vx_fetch|VX_Warp_zero|real_PC[14] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #844: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.158 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.160 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.158 ; 3.160 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|sload ; +; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N10 ; ; vx_fetch|VX_Warp_zero|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #845: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.296 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.298 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.890 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.296 ; 3.298 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.268 ; 0.600 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|dataf ; +; 6.296 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|combout ; +; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|d ; +; 6.296 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #846: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.299 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.307 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.663 ; 81 ; 0.136 ; 0.714 ; +; Cell ; ; 14 ; 0.518 ; 16 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.299 ; 3.307 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; FF ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.676 ; 0.514 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; +; 3.759 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.763 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.899 ; 0.136 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.978 ; 0.079 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.983 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.339 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.429 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.434 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.117 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.208 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.214 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.928 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.958 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.964 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.224 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.299 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.299 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #847: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.288 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.290 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.822 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.288 ; 3.290 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.261 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; +; 6.288 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #848: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.578 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.277 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.810 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.275 ; 3.277 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.248 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; +; 6.275 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #849: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.774 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.376 ; 11 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.344 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.424 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.428 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.242 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; +; 6.269 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #850: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.291 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.645 ; 80 ; 0.133 ; 0.712 ; +; Cell ; ; 14 ; 0.520 ; 16 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.283 ; 3.291 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.687 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; +; 3.763 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.767 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.900 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.983 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.988 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.339 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.432 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.437 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.094 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.187 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.193 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.477 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.503 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.509 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.221 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.283 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #851: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++--------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+-----------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.866 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.298 ; 3.300 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.463 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.491 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.496 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.271 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.298 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; +; 6.298 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #852: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.301 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.303 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.839 ; 86 ; 0.127 ; 1.275 ; +; Cell ; ; 12 ; 0.342 ; 10 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.301 ; 3.303 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.184 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; +; 6.301 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; +; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|d ; +; 6.301 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N11 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #853: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.296 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.298 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.774 ; 84 ; 0.120 ; 1.302 ; +; Cell ; ; 12 ; 0.402 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.296 ; 3.298 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.179 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; +; 6.296 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #854: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.301 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.303 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.761 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.421 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.301 ; 3.303 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.460 ; 0.534 ; RR ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.488 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.492 ; 0.004 ; FF ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.211 ; 0.719 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~555|datad ; +; 6.301 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X105_Y159_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~555|combout ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11]|d ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #855: Setup slack is -0.697 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[0] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.292 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.697 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.110 ; ; ; ; ; ; +; Data Delay ; 2.219 ; ; ; ; ; ; +; Number of Logic Levels ; ; 2 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 2 ; 1.847 ; 83 ; 0.895 ; 0.952 ; +; Cell ; ; 6 ; 0.188 ; 8 ; 0.000 ; 0.081 ; +; uTco ; ; 1 ; 0.184 ; 8 ; 0.184 ; 0.184 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]|clk ; +; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; +; 6.292 ; 2.219 ; ; ; ; ; ; data path ; +; 4.257 ; 0.184 ; FF ; uTco ; 1 ; FF_X102_Y159_N56 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]|q ; +; 4.301 ; 0.044 ; FF ; CELL ; 3 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]~la_lab/laboutb[17] ; +; 5.253 ; 0.952 ; FF ; IC ; 1 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97|datad ; +; 5.334 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97|combout ; +; 5.338 ; 0.004 ; FF ; CELL ; 3 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97~la_lab/laboutt[16] ; +; 6.233 ; 0.895 ; FF ; IC ; 1 ; MLABCELL_X69_Y156_N36 ; High Speed ; vx_fetch|VX_Warp_two|i199~1|datae ; +; 6.292 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X69_Y156_N36 ; High Speed ; vx_fetch|VX_Warp_two|i199~1|combout ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y156_N38 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[0]|d ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y156_N38 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[0] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.463 ; 2.963 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X69_Y156_N38 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[0]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y156_N38 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[0] ; +; 5.463 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.433 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.162 ; ; uTsu ; 1 ; FF_X69_Y156_N38 ; ; vx_fetch|VX_Warp_two|real_PC[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #856: Setup slack is -0.696 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.696 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.251 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.660 ; 82 ; 0.127 ; 0.734 ; +; Cell ; ; 14 ; 0.464 ; 14 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.243 ; 3.251 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; +; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.091 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.171 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.176 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.303 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.424 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.429 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.086 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.179 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.185 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.551 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.579 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.583 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.215 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.243 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #857: Setup slack is -0.696 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.158 ; +; Data Required Time ; 5.462 ; +; Slack ; -0.696 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.160 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.158 ; 3.160 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|sload ; +; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N5 ; ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #858: Setup slack is -0.696 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.158 ; +; Data Required Time ; 5.462 ; +; Slack ; -0.696 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.160 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.158 ; 3.160 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|sload ; +; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N14 ; ; vx_fetch|VX_Warp_zero|real_PC[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #859: Setup slack is -0.696 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.313 ; +; Data Required Time ; 5.617 ; +; Slack ; -0.696 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.027 ; ; ; ; ; ; +; Data Delay ; 3.315 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.906 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.313 ; 3.315 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.511 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.285 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|dataf ; +; 6.313 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|combout ; +; 6.313 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|d ; +; 6.313 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; +; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.617 ; 0.176 ; ; uTsu ; 1 ; FF_X107_Y149_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #860: Setup slack is -0.696 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.314 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.696 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.316 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.842 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.352 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.314 ; 3.316 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.482 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.221 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|datac ; +; 6.314 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|combout ; +; 6.314 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|d ; +; 6.314 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y142_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #861: Setup slack is -0.696 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.295 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.696 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.297 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.849 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.295 ; 3.297 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.444 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.471 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.477 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.267 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; +; 6.295 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #862: Setup slack is -0.696 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.585 ; +; Slack ; -0.696 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.795 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.366 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.391 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.418 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.422 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.188 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; +; 6.281 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #863: Setup slack is -0.696 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.295 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.696 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.297 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.819 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.357 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.295 ; 3.297 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.391 ; 0.474 ; RR ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; +; 5.418 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; +; 5.422 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; +; 6.267 ; 0.845 ; FF ; IC ; 1 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|dataf ; +; 6.295 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|combout ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]|d ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #864: Setup slack is -0.696 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.166 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.696 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.024 ; ; ; ; ; ; +; Data Delay ; 3.168 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.664 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.199 ; 80 ; 0.000 ; 2.199 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.166 ; 3.168 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.166 ; 0.256 ; FF ; IC ; 1 ; FF_X72_Y161_N35 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[13]|sload ; +; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y161_N35 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[13] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.474 ; 2.974 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.264 ; 2.199 ; RR ; IC ; 1 ; FF_X72_Y161_N35 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[13]|clk ; +; 5.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y161_N35 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[13] ; +; 5.474 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.444 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.026 ; ; uTsu ; 1 ; FF_X72_Y161_N35 ; ; vx_fetch|VX_Warp_zero|real_PC[13] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #865: Setup slack is -0.696 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.296 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.696 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.298 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.761 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.416 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.296 ; 3.298 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.493 ; 0.575 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.519 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.525 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; +; 6.211 ; 0.686 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~971|datad ; +; 6.296 ; 0.085 ; FR ; CELL ; 1 ; MLABCELL_X107_Y158_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~971|combout ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11]|d ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #866: Setup slack is -0.695 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.294 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.695 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.302 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.681 ; 81 ; 0.117 ; 0.710 ; +; Cell ; ; 14 ; 0.496 ; 15 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.294 ; 3.302 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.895 ; 0.710 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.018 ; 0.123 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.024 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.141 ; 0.117 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; +; 4.167 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.172 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.355 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.412 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.417 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.100 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.191 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.197 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.905 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.933 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.219 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.294 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.294 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.294 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #867: Setup slack is -0.695 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.695 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.051 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.890 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.283 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.536 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.562 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.568 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.267 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|dataf ; +; 6.293 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|combout ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|d ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.447 ; 2.947 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; +; 5.447 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.417 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y163_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #868: Setup slack is -0.695 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.291 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.695 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.293 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.832 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.291 ; 3.293 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.235 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; +; 5.262 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; +; 5.267 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; +; 6.209 ; 0.942 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|datad ; +; 6.291 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|combout ; +; 6.291 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|d ; +; 6.291 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y162_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #869: Setup slack is -0.695 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[16] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.551 ; +; Slack ; -0.695 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.078 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.647 ; 81 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.479 ; 15 ; 0.000 ; 0.128 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.118 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|datab ; +; 6.246 ; 0.128 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|combout ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|d ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|clk ; +; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; +; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.551 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y152_N32 ; ; vx_d_e_reg|b_reg_data[16] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #870: Setup slack is -0.695 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.308 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.695 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.310 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.781 ; 84 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.308 ; 3.310 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.446 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.477 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.481 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.221 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; +; 6.308 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; +; 6.308 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; +; 6.308 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #871: Setup slack is -0.695 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.289 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.695 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.291 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.770 ; 84 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.289 ; 3.291 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.450 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.477 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.482 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.207 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; +; 6.289 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; +; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; +; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #872: Setup slack is -0.695 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.286 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.695 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.288 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.841 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.286 ; 3.288 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.259 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; +; 6.286 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; +; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; +; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #873: Setup slack is -0.695 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.578 ; +; Slack ; -0.695 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.829 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.246 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; +; 6.273 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #874: Setup slack is -0.695 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.290 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.695 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.292 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.917 ; 89 ; 0.114 ; 1.366 ; +; Cell ; ; 12 ; 0.253 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.290 ; 3.292 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.262 ; 1.366 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|dataf ; +; 6.290 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|combout ; +; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|d ; +; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #875: Setup slack is -0.695 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.294 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.695 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.296 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.793 ; 85 ; 0.104 ; 1.302 ; +; Cell ; ; 12 ; 0.382 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.294 ; 3.296 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.177 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; +; 6.294 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; +; 6.294 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; +; 6.294 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #876: Setup slack is -0.695 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[19] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.166 ; +; Data Required Time ; 5.471 ; +; Slack ; -0.695 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.024 ; ; ; ; ; ; +; Data Delay ; 3.168 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.664 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.199 ; 80 ; 0.000 ; 2.199 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.166 ; 3.168 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.166 ; 0.256 ; FF ; IC ; 1 ; FF_X72_Y161_N53 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[19]|sload ; +; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y161_N53 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[19] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.474 ; 2.974 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.264 ; 2.199 ; RR ; IC ; 1 ; FF_X72_Y161_N53 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[19]|clk ; +; 5.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y161_N53 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[19] ; +; 5.474 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.444 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.471 ; 0.027 ; ; uTsu ; 1 ; FF_X72_Y161_N53 ; ; vx_fetch|VX_Warp_zero|real_PC[19] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #877: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[16] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.158 ; +; Data Required Time ; 5.464 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.160 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.158 ; 3.160 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|sload ; +; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N32 ; ; vx_fetch|VX_Warp_zero|real_PC[16] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #878: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.158 ; +; Data Required Time ; 5.464 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.160 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.158 ; 3.160 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|sload ; +; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N44 ; ; vx_fetch|VX_Warp_zero|real_PC[17] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #879: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.158 ; +; Data Required Time ; 5.464 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.160 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.654 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.158 ; 3.160 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.158 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|sload ; +; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[20] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #880: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.300 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.302 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.828 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.352 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.300 ; 3.302 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.501 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.532 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.536 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.208 ; 0.672 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|datad ; +; 6.300 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|combout ; +; 6.300 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|d ; +; 6.300 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #881: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.284 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.286 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.818 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.284 ; 3.286 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.257 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; +; 6.284 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; +; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; +; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #882: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.277 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.279 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.845 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.277 ; 3.279 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.466 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.493 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.498 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.249 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; +; 6.277 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #883: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.295 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.297 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.757 ; 84 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.419 ; 13 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.295 ; 3.297 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.409 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.440 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.445 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.165 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; +; 6.295 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; +; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; +; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #884: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.086 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.088 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.627 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.086 ; 3.088 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.086 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|sclr ; +; 6.086 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N25 ; ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #885: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|a_reg_data[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.086 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.088 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.627 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.086 ; 3.088 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.086 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|sclr ; +; 6.086 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N26 ; ; vx_d_e_reg|a_reg_data[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #886: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|a_reg_data[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.086 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.088 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.627 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.086 ; 3.088 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.086 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|sclr ; +; 6.086 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N16 ; ; vx_d_e_reg|a_reg_data[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #887: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.309 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.311 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.793 ; 84 ; 0.104 ; 1.300 ; +; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.309 ; 3.311 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.188 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.309 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.309 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; +; 6.309 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #888: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.781 ; 84 ; 0.104 ; 1.275 ; +; Cell ; ; 12 ; 0.392 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.176 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; +; 6.293 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #889: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.309 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.311 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.793 ; 84 ; 0.104 ; 1.300 ; +; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.309 ; 3.311 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.188 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.309 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.309 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; +; 6.309 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #890: Setup slack is -0.694 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.290 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.694 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.292 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.865 ; 87 ; 0.104 ; 1.372 ; +; Cell ; ; 12 ; 0.305 ; 9 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.290 ; 3.292 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.260 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; +; 6.290 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #891: Setup slack is -0.693 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.280 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.693 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.874 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.280 ; 3.282 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.252 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; +; 6.280 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|d ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #892: Setup slack is -0.693 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.280 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.693 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.874 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.280 ; 3.282 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.668 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.252 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; +; 6.280 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|d ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #893: Setup slack is -0.693 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.294 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.693 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.296 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.792 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.294 ; 3.296 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.421 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.497 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.501 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.267 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; +; 6.294 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; +; 6.294 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; +; 6.294 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #894: Setup slack is -0.693 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.274 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.693 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.276 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.819 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.274 ; 3.276 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.473 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.247 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; +; 6.274 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #895: Setup slack is -0.693 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.292 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.693 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.712 ; 82 ; 0.136 ; 0.708 ; +; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.292 ; 3.300 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.712 ; 0.549 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; +; 3.740 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.744 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.880 ; 0.136 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.959 ; 0.079 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.964 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.320 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.410 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.415 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.098 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.189 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.195 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.903 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.931 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.937 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.217 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.292 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #896: Setup slack is -0.693 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.693 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.800 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.444 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.479 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.219 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; +; 6.306 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #897: Setup slack is -0.693 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.287 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.693 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.289 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.379 ; 12 ; 0.000 ; 0.082 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.287 ; 3.289 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.448 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.475 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.480 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.205 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; +; 6.287 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; +; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; +; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #898: Setup slack is -0.693 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.277 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.693 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.279 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.854 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.303 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.277 ; 3.279 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.469 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.497 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.502 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.249 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; +; 6.277 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #899: Setup slack is -0.693 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.292 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.693 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.294 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.903 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.292 ; 3.294 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.266 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|dataf ; +; 6.292 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X101_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~782|combout ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|d ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #900: Setup slack is -0.693 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; +; To Node ; vx_e_m_reg|alu_result[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.196 ; +; Data Required Time ; 5.503 ; +; Slack ; -0.693 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.083 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.463 ; 76 ; 0.121 ; 0.816 ; +; Cell ; ; 18 ; 0.662 ; 20 ; 0.000 ; 0.176 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|clk ; +; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; +; 6.196 ; 3.248 ; ; ; ; ; ; data path ; +; 3.071 ; 0.123 ; FF ; uTco ; 1 ; FF_X79_Y153_N40 ; ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|q ; +; 3.115 ; 0.044 ; FF ; CELL ; 2 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE~la_lab/laboutb[6] ; +; 3.931 ; 0.816 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|dataf ; +; 3.958 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|combout ; +; 3.964 ; 0.006 ; FF ; CELL ; 70 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20~la_mlab/laboutt[7] ; +; 4.247 ; 0.283 ; FF ; IC ; 5 ; LABCELL_X73_Y152_N0 ; High Speed ; vx_execute|[0].vx_alu|add_0~1|datac ; +; 4.423 ; 0.176 ; FF ; CELL ; 1 ; LABCELL_X73_Y152_N3 ; High Speed ; vx_execute|[0].vx_alu|add_0~5|cout ; +; 4.423 ; 0.000 ; FF ; CELL ; 3 ; LABCELL_X73_Y152_N6 ; High Speed ; vx_execute|[0].vx_alu|add_0~9|cin ; +; 4.440 ; 0.017 ; FR ; CELL ; 1 ; LABCELL_X73_Y152_N9 ; High Speed ; vx_execute|[0].vx_alu|add_0~13|cout ; +; 4.440 ; 0.000 ; RR ; CELL ; 3 ; LABCELL_X73_Y152_N12 ; High Speed ; vx_execute|[0].vx_alu|add_0~17|cin ; +; 4.451 ; 0.011 ; RF ; CELL ; 1 ; LABCELL_X73_Y152_N15 ; High Speed ; vx_execute|[0].vx_alu|add_0~21|cout ; +; 4.451 ; 0.000 ; FF ; CELL ; 3 ; LABCELL_X73_Y152_N18 ; High Speed ; vx_execute|[0].vx_alu|add_0~25|cin ; +; 4.565 ; 0.114 ; FF ; CELL ; 1 ; LABCELL_X73_Y152_N21 ; High Speed ; vx_execute|[0].vx_alu|add_0~29|sumout ; +; 4.570 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X73_Y152_N21 ; High Speed ; vx_execute|[0].vx_alu|add_0~29~la_lab/laboutt[15] ; +; 4.997 ; 0.427 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~51|datac ; +; 5.084 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~51|combout ; +; 5.090 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~51~la_mlab/laboutt[13] ; +; 5.211 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|datac ; +; 5.301 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|combout ; +; 5.307 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52~la_mlab/laboutb[11] ; +; 6.123 ; 0.816 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|datad ; +; 6.196 ; 0.073 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|combout ; +; 6.196 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|d ; +; 6.196 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.503 ; 0.168 ; ; uTsu ; 1 ; FF_X46_Y153_N34 ; ; vx_e_m_reg|alu_result[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #901: Setup slack is -0.693 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.276 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.693 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.764 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.276 ; 3.278 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.546 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.194 ; 0.648 ; RR ; IC ; 1 ; LABCELL_X93_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~845|datac ; +; 6.276 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X93_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~845|combout ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13]|d ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.162 ; ; uTsu ; 1 ; FF_X93_Y160_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #902: Setup slack is -0.693 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[0] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.287 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.693 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.110 ; ; ; ; ; ; +; Data Delay ; 2.214 ; ; ; ; ; ; +; Number of Logic Levels ; ; 2 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 2 ; 1.841 ; 83 ; 0.889 ; 0.952 ; +; Cell ; ; 6 ; 0.189 ; 9 ; 0.000 ; 0.081 ; +; uTco ; ; 1 ; 0.184 ; 8 ; 0.184 ; 0.184 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]|clk ; +; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0] ; +; 6.287 ; 2.214 ; ; ; ; ; ; data path ; +; 4.257 ; 0.184 ; FF ; uTco ; 1 ; FF_X102_Y159_N56 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]|q ; +; 4.301 ; 0.044 ; FF ; CELL ; 3 ; FF_X102_Y159_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[0]~la_lab/laboutb[17] ; +; 5.253 ; 0.952 ; FF ; IC ; 1 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97|datad ; +; 5.334 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97|combout ; +; 5.338 ; 0.004 ; FF ; CELL ; 3 ; LABCELL_X79_Y157_N24 ; High Speed ; vx_decode|out_a_reg_data[0]~97~la_lab/laboutt[16] ; +; 6.227 ; 0.889 ; FF ; IC ; 1 ; MLABCELL_X69_Y156_N54 ; High Speed ; vx_fetch|VX_Warp_three|i199~1|datae ; +; 6.287 ; 0.060 ; FF ; CELL ; 1 ; MLABCELL_X69_Y156_N54 ; High Speed ; vx_fetch|VX_Warp_three|i199~1|combout ; +; 6.287 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y156_N56 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[0]|d ; +; 6.287 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y156_N56 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[0] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.463 ; 2.963 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X69_Y156_N56 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[0]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y156_N56 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[0] ; +; 5.463 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.433 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.161 ; ; uTsu ; 1 ; FF_X69_Y156_N56 ; ; vx_fetch|VX_Warp_three|real_PC[0] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #903: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.149 ; +; Data Required Time ; 5.457 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.151 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.676 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.149 ; 3.151 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.149 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|sload ; +; 6.149 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.457 ; 0.014 ; ; uTsu ; 1 ; FF_X73_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #904: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.770 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.459 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.463 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.199 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; +; 6.281 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|d ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y164_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #905: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.842 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.220 ; 0.655 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|datac ; +; 6.306 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|combout ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|d ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X103_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #906: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.286 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.288 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.827 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.286 ; 3.288 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.235 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; +; 5.262 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; +; 5.267 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; +; 6.204 ; 0.937 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|datad ; +; 6.286 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|combout ; +; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|d ; +; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #907: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.274 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.276 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.815 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.274 ; 3.276 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.486 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.518 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.523 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; +; 6.247 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; +; 6.274 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #908: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.829 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.506 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.256 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; +; 6.283 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #909: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.297 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.299 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.780 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.297 ; 3.299 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.480 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.509 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.514 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.210 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; +; 6.297 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; +; 6.297 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; +; 6.297 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #910: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.552 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.078 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.647 ; 82 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.477 ; 15 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.118 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|datab ; +; 6.244 ; 0.126 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|combout ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|d ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|clk ; +; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; +; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.552 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y152_N34 ; ; vx_d_e_reg|b_reg_data[17] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #911: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.808 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.447 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.474 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.480 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.246 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; +; 6.273 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #912: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.837 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.255 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; +; 6.282 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #913: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.294 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.296 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.831 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.294 ; 3.296 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.504 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.530 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.536 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.268 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; +; 6.294 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; +; 6.294 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; +; 6.294 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #914: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++----------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+-------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.778 ; 86 ; 0.108 ; 0.910 ; +; Cell ; ; 12 ; 0.348 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.218 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; +; 6.246 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|d ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #915: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.682 ; 83 ; 0.133 ; 0.657 ; +; Cell ; ; 14 ; 0.440 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.241 ; 3.249 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.722 ; 0.540 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; +; 3.750 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.754 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.887 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.970 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.975 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.326 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.419 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.424 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.081 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.174 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.180 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.546 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.574 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.578 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.213 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.241 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #916: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.240 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.681 ; 83 ; 0.133 ; 0.657 ; +; Cell ; ; 14 ; 0.440 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.240 ; 3.248 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.722 ; 0.540 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; +; 3.750 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.754 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.887 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.970 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.975 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.326 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.419 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.424 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.081 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.174 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.180 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.546 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.574 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.578 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.212 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.240 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #917: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.296 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.298 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.781 ; 84 ; 0.104 ; 1.275 ; +; Cell ; ; 12 ; 0.395 ; 12 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.296 ; 3.298 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.176 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.296 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #918: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.774 ; 84 ; 0.120 ; 1.302 ; +; Cell ; ; 12 ; 0.404 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.298 ; 3.300 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.179 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; +; 6.298 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #919: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.277 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.814 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.275 ; 3.277 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; +; 6.248 ; 0.686 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~585|dataf ; +; 6.275 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~585|combout ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9]|d ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #920: Setup slack is -0.692 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.692 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.759 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.393 ; 0.476 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.467 ; 0.074 ; RF ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.471 ; 0.004 ; FF ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.254 ; 0.783 ; FF ; IC ; 1 ; LABCELL_X93_Y161_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~877|dataf ; +; 6.282 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X93_Y161_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~877|combout ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13]|d ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y161_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #921: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|csr_mask[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.279 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.281 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.798 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.279 ; 3.281 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.592 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.618 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.624 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.251 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; +; 6.279 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #922: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|csr_mask[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.279 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.281 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.798 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.279 ; 3.281 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.592 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.618 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.624 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.251 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; +; 6.279 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #923: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.734 ; 83 ; 0.110 ; 0.788 ; +; Cell ; ; 14 ; 0.440 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.922 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.951 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.957 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.220 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.293 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #924: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.290 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.292 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.883 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.290 ; 3.292 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.477 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.509 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.513 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.264 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|dataf ; +; 6.290 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|combout ; +; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|d ; +; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #925: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.770 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.459 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.463 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.199 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; +; 6.281 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|d ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #926: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.274 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.276 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.868 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.274 ; 3.276 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.247 ; 0.681 ; RR ; IC ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|dataf ; +; 6.274 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|combout ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|d ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #927: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.291 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.293 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.826 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.291 ; 3.293 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.474 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.502 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.508 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.208 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; +; 6.291 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; +; 6.291 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; +; 6.291 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #928: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|b_reg_data[24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.778 ; 86 ; 0.108 ; 0.910 ; +; Cell ; ; 12 ; 0.348 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.218 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; +; 6.246 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|d ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N17 ; ; vx_d_e_reg|b_reg_data[24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #929: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.238 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.679 ; 83 ; 0.133 ; 0.657 ; +; Cell ; ; 14 ; 0.440 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.238 ; 3.246 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.722 ; 0.540 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; +; 3.750 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.754 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.887 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.970 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.975 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.326 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.419 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.424 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.081 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.174 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.180 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.546 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.574 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.578 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.210 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.238 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #930: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.291 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.293 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.837 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.291 ; 3.293 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.435 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.461 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.467 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.198 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|datad ; +; 6.291 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X90_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~890|combout ; +; 6.291 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|d ; +; 6.291 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #931: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|a_reg_data[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.086 ; +; Data Required Time ; 5.395 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.088 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.627 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.086 ; 3.088 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.086 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|sclr ; +; 6.086 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N38 ; ; vx_d_e_reg|a_reg_data[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #932: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|a_reg_data[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.086 ; +; Data Required Time ; 5.395 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.088 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.627 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.086 ; 3.088 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.086 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|sclr ; +; 6.086 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N32 ; ; vx_d_e_reg|a_reg_data[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #933: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_f_d_reg|curr_PC[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.159 ; +; Data Required Time ; 5.468 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.028 ; ; ; ; ; ; +; Data Delay ; 3.161 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.751 ; 87 ; 0.119 ; 1.282 ; +; Cell ; ; 10 ; 0.290 ; 9 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.159 ; 3.161 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.510 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.844 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.872 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.159 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|ena ; +; 6.159 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; +; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N44 ; ; vx_f_d_reg|curr_PC[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #934: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_f_d_reg|curr_PC[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.159 ; +; Data Required Time ; 5.468 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.028 ; ; ; ; ; ; +; Data Delay ; 3.161 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.751 ; 87 ; 0.119 ; 1.282 ; +; Cell ; ; 10 ; 0.290 ; 9 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.159 ; 3.161 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.510 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.844 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.872 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.159 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|ena ; +; 6.159 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; +; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N25 ; ; vx_f_d_reg|curr_PC[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #935: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.793 ; 84 ; 0.104 ; 1.300 ; +; Cell ; ; 12 ; 0.393 ; 12 ; 0.000 ; 0.118 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.188 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|datab ; +; 6.306 ; 0.118 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #936: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.150 ; +; Data Required Time ; 5.459 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.152 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.648 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.150 ; 3.152 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.150 ; 0.240 ; FF ; IC ; 1 ; FF_X71_Y159_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[21]|sload ; +; 6.150 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y159_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[21] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y159_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[21]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y159_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[21] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.459 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y159_N25 ; ; vx_fetch|VX_Warp_zero|real_PC[21] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #937: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.150 ; +; Data Required Time ; 5.459 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.152 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.648 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.150 ; 3.152 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.150 ; 0.240 ; FF ; IC ; 1 ; FF_X71_Y159_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[3]|sload ; +; 6.150 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y159_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[3] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y159_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[3]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y159_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[3] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.459 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y159_N10 ; ; vx_fetch|VX_Warp_zero|real_PC[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #938: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.290 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.292 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.831 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.290 ; 3.292 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.262 ; 0.665 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|dataf ; +; 6.290 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|combout ; +; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]|d ; +; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #939: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.303 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.305 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.842 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.303 ; 3.305 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.509 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.541 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.546 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[17] ; +; 6.277 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~786|dataf ; +; 6.303 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~786|combout ; +; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18]|d ; +; 6.303 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #940: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.295 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.297 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.819 ; 86 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.357 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.295 ; 3.297 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.391 ; 0.474 ; RR ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; +; 5.418 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; +; 5.422 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; +; 6.267 ; 0.845 ; FF ; IC ; 1 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|dataf ; +; 6.295 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|combout ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE|d ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y150_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #941: Setup slack is -0.691 (VIOLATED) +=============================================================================== ++-----------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------+ +; Property ; Value ; ++--------------------+--------------------------+ +; From Node ; vx_d_e_reg|a_reg_data[0] ; +; To Node ; vx_e_m_reg|alu_result[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.192 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.691 (VIOLATED) ; ++--------------------+--------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.320 ; 79 ; 0.000 ; 2.320 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.607 ; 80 ; 0.132 ; 0.955 ; +; Cell ; ; 14 ; 0.411 ; 13 ; 0.000 ; 0.124 ; +; uTco ; ; 1 ; 0.227 ; 7 ; 0.227 ; 0.227 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.947 ; 2.947 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.947 ; 2.320 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; +; 2.947 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; +; 6.192 ; 3.245 ; ; ; ; ; ; data path ; +; 3.174 ; 0.227 ; FF ; uTco ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0]|q ; +; 3.221 ; 0.047 ; FF ; CELL ; 12 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]~la_lab/laboutb[1] ; +; 4.176 ; 0.955 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|dataa ; +; 4.300 ; 0.124 ; FR ; CELL ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|combout ; +; 4.305 ; 0.005 ; RR ; CELL ; 2 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28~la_mlab/laboutt[2] ; +; 4.437 ; 0.132 ; RR ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datae ; +; 4.510 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; +; 4.514 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; +; 4.729 ; 0.215 ; FF ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; +; 4.792 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.796 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.244 ; 0.448 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.272 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.278 ; 0.006 ; RR ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.424 ; 0.146 ; RR ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; +; 5.450 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; +; 5.455 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; +; 6.166 ; 0.711 ; RR ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; +; 6.192 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; +; 6.192 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; +; 6.192 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #942: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.303 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.305 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.830 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.353 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.303 ; 3.305 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.477 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.509 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.513 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.211 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|datac ; +; 6.303 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|combout ; +; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|d ; +; 6.303 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #943: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.300 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.302 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.843 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.300 ; 3.302 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.474 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.272 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|dataf ; +; 6.300 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|combout ; +; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|d ; +; 6.300 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.164 ; ; uTsu ; 1 ; FF_X104_Y146_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #944: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.301 ; +; Data Required Time ; 5.611 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.303 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.843 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.301 ; 3.303 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.468 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.499 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.503 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.273 ; 0.770 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|dataf ; +; 6.301 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|combout ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|d ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #945: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.290 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.292 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.774 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.290 ; 3.292 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.203 ; 0.645 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|datad ; +; 6.290 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; +; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; +; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #946: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.288 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.290 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.831 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.288 ; 3.290 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.480 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.509 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.514 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.261 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|dataf ; +; 6.288 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|combout ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|d ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #947: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.284 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.286 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.828 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.284 ; 3.286 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.257 ; 0.596 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|dataf ; +; 6.284 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|combout ; +; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|d ; +; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #948: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.289 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.291 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.759 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.410 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.289 ; 3.291 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.417 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.444 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.449 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.197 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.289 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; +; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #949: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.827 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.445 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.478 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.244 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; +; 6.271 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #950: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.286 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.288 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.819 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.286 ; 3.288 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.446 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.473 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.479 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.258 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; +; 6.286 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; +; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; +; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #951: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.292 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.294 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.850 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.323 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.292 ; 3.294 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.502 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.528 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.534 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.266 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; +; 6.292 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #952: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.238 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.520 ; 78 ; 0.118 ; 0.683 ; +; Cell ; ; 14 ; 0.600 ; 18 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.238 ; 3.246 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.602 ; 0.362 ; FF ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.630 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.634 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.212 ; 0.578 ; RR ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.238 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #953: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|b_reg_data[19] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.776 ; 86 ; 0.108 ; 0.908 ; +; Cell ; ; 12 ; 0.348 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.216 ; 0.908 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|dataf ; +; 6.244 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|combout ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|d ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N22 ; ; vx_d_e_reg|b_reg_data[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #954: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.585 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.277 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.779 ; 85 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.377 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.275 ; 3.277 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.385 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.412 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.416 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.182 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; +; 6.275 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; +; 6.275 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; +; 6.275 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #955: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.284 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.286 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.893 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.273 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.284 ; 3.286 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.256 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|dataf ; +; 6.284 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~790|combout ; +; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|d ; +; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #956: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|b_reg_data[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.245 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.808 ; 86 ; 0.108 ; 0.943 ; +; Cell ; ; 12 ; 0.317 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.245 ; 3.247 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.215 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; +; 6.245 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; +; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; +; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #957: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|b_reg_data[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.245 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.809 ; 87 ; 0.108 ; 0.944 ; +; Cell ; ; 12 ; 0.316 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.245 ; 3.247 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.216 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; +; 6.245 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; +; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; +; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #958: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.296 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.298 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.793 ; 85 ; 0.104 ; 1.302 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.119 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.296 ; 3.298 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.177 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; +; 6.296 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; +; 6.296 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #959: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[1] ; +; To Node ; vx_e_m_reg|alu_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++-----------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+-------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+-------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; 0.005 ; ; ; ; ; ; +; Data Delay ; 3.329 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.348 ; 79 ; 0.000 ; 2.348 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.666 ; 80 ; 0.113 ; 0.777 ; +; Cell ; ; 16 ; 0.534 ; 16 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.129 ; 4 ; 0.129 ; 0.129 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+-------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.975 ; 2.975 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.975 ; 2.348 ; RR ; IC ; 1 ; FF_X40_Y149_N38 ; High Speed ; vx_csr_handler|decode_csr_address[1]|clk ; +; 2.975 ; 0.000 ; RR ; CELL ; 1 ; FF_X40_Y149_N38 ; High Speed ; vx_csr_handler|decode_csr_address[1] ; +; 6.304 ; 3.329 ; ; ; ; ; ; data path ; +; 3.104 ; 0.129 ; RR ; uTco ; 1 ; FF_X40_Y149_N38 ; ; vx_csr_handler|decode_csr_address[1]|q ; +; 3.167 ; 0.063 ; RR ; CELL ; 548 ; FF_X40_Y149_N38 ; High Speed ; vx_csr_handler|decode_csr_address[1]~la_lab/laboutb[5] ; +; 3.808 ; 0.641 ; RR ; IC ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|datae ; +; 3.883 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|combout ; +; 3.888 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196~la_lab/laboutb[1] ; +; 4.335 ; 0.447 ; RR ; IC ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|datae ; +; 4.408 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|combout ; +; 4.414 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200~la_mlab/laboutt[0] ; +; 4.539 ; 0.125 ; RR ; IC ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|datac ; +; 4.619 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|combout ; +; 4.623 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211~la_lab/laboutb[14] ; +; 5.059 ; 0.436 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|datad ; +; 5.139 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; +; 5.143 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; +; 5.270 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; +; 5.353 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.357 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.134 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.160 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.165 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.278 ; 0.113 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; +; 6.304 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; +; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; +; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.164 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #960: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[0]~DUPLICATE ; +; To Node ; vx_e_m_reg|alu_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.304 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+------------------------------------------------+ + ++-----------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+-------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+-------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; 0.005 ; ; ; ; ; ; +; Data Delay ; 3.329 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.348 ; 79 ; 0.000 ; 2.348 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.734 ; 82 ; 0.113 ; 0.777 ; +; Cell ; ; 16 ; 0.469 ; 14 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+-------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+-------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+-------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.975 ; 2.975 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.975 ; 2.348 ; RR ; IC ; 1 ; FF_X40_Y149_N28 ; High Speed ; vx_csr_handler|decode_csr_address[0]~DUPLICATE|clk ; +; 2.975 ; 0.000 ; RR ; CELL ; 1 ; FF_X40_Y149_N28 ; High Speed ; vx_csr_handler|decode_csr_address[0]~DUPLICATE ; +; 6.304 ; 3.329 ; ; ; ; ; ; data path ; +; 3.101 ; 0.126 ; FF ; uTco ; 1 ; FF_X40_Y149_N28 ; ; vx_csr_handler|decode_csr_address[0]~DUPLICATE|q ; +; 3.145 ; 0.044 ; FF ; CELL ; 363 ; FF_X40_Y149_N28 ; High Speed ; vx_csr_handler|decode_csr_address[0]~DUPLICATE~la_lab/laboutt[18] ; +; 3.854 ; 0.709 ; FF ; IC ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|dataf ; +; 3.883 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196|combout ; +; 3.888 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X30_Y145_N30 ; High Speed ; vx_csr_handler|Mux_3~196~la_lab/laboutb[1] ; +; 4.335 ; 0.447 ; RR ; IC ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|datae ; +; 4.408 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200|combout ; +; 4.414 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X34_Y149_N0 ; High Speed ; vx_csr_handler|Mux_3~200~la_mlab/laboutt[0] ; +; 4.539 ; 0.125 ; RR ; IC ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|datac ; +; 4.619 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211|combout ; +; 4.623 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X35_Y149_N51 ; High Speed ; vx_csr_handler|Mux_3~211~la_lab/laboutb[14] ; +; 5.059 ; 0.436 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|datad ; +; 5.139 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; +; 5.143 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; +; 5.270 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; +; 5.353 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.357 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.134 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.160 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.165 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.278 ; 0.113 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; +; 6.304 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; +; 6.304 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+----------------------+------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; +; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; +; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.164 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #961: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.822 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.555 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; +; 6.256 ; 0.701 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~732|dataf ; +; 6.283 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~732|combout ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28]|d ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #962: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.813 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.598 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.245 ; 0.647 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~969|dataf ; +; 6.272 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~969|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9]|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y159_N37 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #963: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.292 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.294 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.832 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.292 ; 3.294 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.265 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|dataf ; +; 6.292 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|combout ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE|d ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.164 ; ; uTsu ; 1 ; FF_X108_Y150_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #964: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[25] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.318 ; +; Data Required Time ; 5.628 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.113 ; ; ; ; ; ; +; Data Delay ; 2.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.985 ; 88 ; 0.421 ; 0.887 ; +; Cell ; ; 8 ; 0.130 ; 6 ; 0.000 ; 0.044 ; +; uTco ; ; 1 ; 0.131 ; 6 ; 0.131 ; 0.131 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+-----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+-----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X108_Y149_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25]|clk ; +; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y149_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25] ; +; 6.318 ; 2.246 ; ; ; ; ; ; data path ; +; 4.203 ; 0.131 ; FF ; uTco ; 1 ; FF_X108_Y149_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25]|q ; +; 4.247 ; 0.044 ; FF ; CELL ; 1 ; FF_X108_Y149_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25]~la_lab/laboutt[17] ; +; 4.924 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|dataf ; +; 4.950 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; +; 4.954 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; +; 5.841 ; 0.887 ; FF ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; +; 5.866 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; +; 5.871 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; +; 6.292 ; 0.421 ; FF ; IC ; 1 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|dataf ; +; 6.318 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|combout ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]|d ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25] ; ++---------+---------+----+------+--------+----------------------+------------+-----------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]|clk ; +; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25] ; +; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.628 ; 0.199 ; ; uTsu ; 1 ; FF_X75_Y158_N38 ; ; vx_fetch|VX_Warp_three|real_PC[25] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #965: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.163 ; +; Data Required Time ; 5.473 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.165 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.705 ; 85 ; 0.119 ; 1.196 ; +; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.163 ; 3.165 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.163 ; 1.196 ; FF ; IC ; 1 ; FF_X71_Y157_N8 ; High Speed ; vx_f_d_reg|curr_PC[31]|ena ; +; 6.163 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y157_N8 ; High Speed ; vx_f_d_reg|curr_PC[31] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y157_N8 ; High Speed ; vx_f_d_reg|curr_PC[31]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y157_N8 ; High Speed ; vx_f_d_reg|curr_PC[31] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.473 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y157_N8 ; ; vx_f_d_reg|curr_PC[31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #966: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.163 ; +; Data Required Time ; 5.473 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.165 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.705 ; 85 ; 0.119 ; 1.196 ; +; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.163 ; 3.165 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.163 ; 1.196 ; FF ; IC ; 1 ; FF_X71_Y157_N49 ; High Speed ; vx_f_d_reg|curr_PC[28]|ena ; +; 6.163 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y157_N49 ; High Speed ; vx_f_d_reg|curr_PC[28] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y157_N49 ; High Speed ; vx_f_d_reg|curr_PC[28]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y157_N49 ; High Speed ; vx_f_d_reg|curr_PC[28] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.473 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y157_N49 ; ; vx_f_d_reg|curr_PC[28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #967: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++-----------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------+ +; Property ; Value ; ++--------------------+--------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[1] ; +; To Node ; vx_e_m_reg|alu_result[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.191 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+--------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.079 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.317 ; 79 ; 0.000 ; 2.317 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.563 ; 79 ; 0.127 ; 0.659 ; +; Cell ; ; 16 ; 0.501 ; 15 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.183 ; 6 ; 0.183 ; 0.183 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.944 ; 2.944 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.944 ; 2.317 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; +; 2.944 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; +; 6.191 ; 3.247 ; ; ; ; ; ; data path ; +; 3.127 ; 0.183 ; FF ; uTco ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1]|q ; +; 3.195 ; 0.068 ; FF ; CELL ; 4 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]~la_lab/laboutt[4] ; +; 3.820 ; 0.625 ; FF ; IC ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|dataf ; +; 3.848 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|combout ; +; 3.852 ; 0.004 ; FF ; CELL ; 71 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22~la_lab/laboutb[2] ; +; 4.224 ; 0.372 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|datac ; +; 4.316 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|combout ; +; 4.321 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28~la_mlab/laboutt[2] ; +; 4.448 ; 0.127 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; +; 4.742 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; +; 4.817 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.821 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.254 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.281 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.287 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.417 ; 0.130 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|dataf ; +; 5.444 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|combout ; +; 5.449 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41~la_mlab/laboutb[0] ; +; 6.108 ; 0.659 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|datac ; +; 6.191 ; 0.083 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|combout ; +; 6.191 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|d ; +; 6.191 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N31 ; ; vx_e_m_reg|alu_result[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #968: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.812 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.543 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.244 ; 0.701 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1001|dataf ; +; 6.272 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1001|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9]|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y159_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #969: Setup slack is -0.690 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.308 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.690 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.310 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.799 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.308 ; 3.310 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.491 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.495 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.281 ; 0.786 ; RR ; IC ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|dataf ; +; 6.308 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|combout ; +; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|d ; +; 6.308 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.181 ; ; uTsu ; 1 ; FF_X101_Y160_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #970: Setup slack is -0.689 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.689 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.658 ; 81 ; 0.127 ; 0.734 ; +; Cell ; ; 14 ; 0.498 ; 15 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.275 ; 3.283 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; +; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.091 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.171 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.176 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.303 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.424 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.429 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.086 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.179 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.185 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.469 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.495 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.501 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.213 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.275 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #971: Setup slack is -0.689 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[12] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.149 ; +; Data Required Time ; 5.460 ; +; Slack ; -0.689 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.151 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.676 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.149 ; 3.151 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.149 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|sload ; +; 6.149 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.460 ; 0.017 ; ; uTsu ; 1 ; FF_X73_Y161_N46 ; ; vx_fetch|VX_Warp_zero|real_PC[12] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #972: Setup slack is -0.689 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.577 ; +; Slack ; -0.689 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.058 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.862 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.284 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.165 ; 79 ; 0.000 ; 2.165 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.363 ; 0.454 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|dataf ; +; 5.392 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|combout ; +; 5.396 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29~la_lab/laboutb[14] ; +; 6.240 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|dataf ; +; 6.266 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|combout ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|d ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.440 ; 2.940 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.230 ; 2.165 ; RR ; IC ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|clk ; +; 5.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; +; 5.440 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.410 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.577 ; 0.167 ; ; uTsu ; 1 ; FF_X88_Y164_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #973: Setup slack is -0.689 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.288 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.689 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.290 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.832 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.288 ; 3.290 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.260 ; 0.600 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|dataf ; +; 6.288 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|combout ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|d ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #974: Setup slack is -0.689 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.289 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.689 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.291 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.820 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.349 ; 11 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.289 ; 3.291 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.200 ; 0.304 ; FF ; IC ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|dataf ; +; 5.229 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|combout ; +; 5.233 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9~la_lab/laboutb[16] ; +; 6.198 ; 0.965 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|datad ; +; 6.289 ; 0.091 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|combout ; +; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|d ; +; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #975: Setup slack is -0.689 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.579 ; +; Slack ; -0.689 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.860 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.487 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.516 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.522 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; +; 6.241 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|dataf ; +; 6.268 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|combout ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|d ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #976: Setup slack is -0.689 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.301 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.689 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.303 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.836 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.301 ; 3.303 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.275 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; +; 6.301 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; +; 6.301 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #977: Setup slack is -0.689 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|b_reg_data[31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.242 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.689 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.244 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.773 ; 85 ; 0.108 ; 0.905 ; +; Cell ; ; 12 ; 0.349 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.242 ; 3.244 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.213 ; 0.905 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|dataf ; +; 6.242 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|combout ; +; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|d ; +; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N25 ; ; vx_d_e_reg|b_reg_data[31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #978: Setup slack is -0.689 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.689 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.781 ; 84 ; 0.104 ; 1.275 ; +; Cell ; ; 12 ; 0.392 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.176 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; +; 6.293 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|d ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N11 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #979: Setup slack is -0.689 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.150 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.689 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.152 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.648 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.150 ; 3.152 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.150 ; 0.240 ; FF ; IC ; 1 ; FF_X71_Y159_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[15]|sload ; +; 6.150 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y159_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[15] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y159_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[15]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y159_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[15] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.016 ; ; uTsu ; 1 ; FF_X71_Y159_N17 ; ; vx_fetch|VX_Warp_zero|real_PC[15] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #980: Setup slack is -0.689 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.292 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.689 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.294 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.832 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.292 ; 3.294 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.265 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|dataf ; +; 6.292 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|combout ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]|d ; +; 6.292 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.165 ; ; uTsu ; 1 ; FF_X108_Y150_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #981: Setup slack is -0.689 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.318 ; +; Data Required Time ; 5.629 ; +; Slack ; -0.689 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.113 ; ; ; ; ; ; +; Data Delay ; 2.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.985 ; 88 ; 0.421 ; 0.887 ; +; Cell ; ; 8 ; 0.130 ; 6 ; 0.000 ; 0.044 ; +; uTco ; ; 1 ; 0.131 ; 6 ; 0.131 ; 0.131 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+-----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+-----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X108_Y149_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25]|clk ; +; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y149_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25] ; +; 6.318 ; 2.246 ; ; ; ; ; ; data path ; +; 4.203 ; 0.131 ; FF ; uTco ; 1 ; FF_X108_Y149_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25]|q ; +; 4.247 ; 0.044 ; FF ; CELL ; 1 ; FF_X108_Y149_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[25]~la_lab/laboutt[17] ; +; 4.924 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|dataf ; +; 4.950 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; +; 4.954 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; +; 5.841 ; 0.887 ; FF ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; +; 5.866 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; +; 5.871 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; +; 6.292 ; 0.421 ; FF ; IC ; 1 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|dataf ; +; 6.318 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|combout ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE|d ; +; 6.318 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; ++---------+---------+----+------+--------+----------------------+------------+-----------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE|clk ; +; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; +; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X75_Y158_N37 ; ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #982: Setup slack is -0.689 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.689 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.770 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.542 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; +; 6.202 ; 0.660 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~986|datac ; +; 6.281 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~986|combout ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26]|d ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y143_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #983: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.237 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.239 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.799 ; 86 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.320 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.237 ; 3.239 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.355 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.143 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.170 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.176 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.542 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.570 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.574 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.209 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.237 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #984: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.798 ; 86 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.320 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.355 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.143 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.170 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.176 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.542 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.570 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.574 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.208 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.236 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #985: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.149 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.151 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.676 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.149 ; 3.151 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.149 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|sload ; +; 6.149 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.018 ; ; uTsu ; 1 ; FF_X73_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #986: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.284 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.286 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.838 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.284 ; 3.286 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.444 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.471 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.477 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.256 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; +; 6.284 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; +; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; +; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #987: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.306 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.308 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.784 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.306 ; 3.308 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.474 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.213 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|datac ; +; 6.306 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|combout ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|d ; +; 6.306 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y142_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #988: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.305 ; +; Data Required Time ; 5.617 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.027 ; ; ; ; ; ; +; Data Delay ; 3.307 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.848 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.305 ; 3.307 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.503 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.277 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|dataf ; +; 6.305 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|combout ; +; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|d ; +; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; +; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.617 ; 0.176 ; ; uTsu ; 1 ; FF_X107_Y149_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #989: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.289 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.291 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.759 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.410 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.289 ; 3.291 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.417 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.444 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.449 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.197 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.289 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; +; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #990: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.287 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.289 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.778 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.287 ; 3.289 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.415 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.447 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.195 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.287 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; +; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #991: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|b_reg_data[28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.771 ; 85 ; 0.119 ; 0.877 ; +; Cell ; ; 12 ; 0.351 ; 11 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.337 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.214 ; 0.877 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|dataf ; +; 6.241 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|combout ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|d ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #992: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|b_reg_data[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.242 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.244 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.805 ; 86 ; 0.108 ; 0.940 ; +; Cell ; ; 12 ; 0.317 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.242 ; 3.244 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.212 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; +; 6.242 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; +; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; +; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #993: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|a_reg_data[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.129 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.131 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.670 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.129 ; 3.131 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.129 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|sclr ; +; 6.129 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #994: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|a_reg_data[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.129 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.131 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.670 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.129 ; 3.131 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.129 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|sclr ; +; 6.129 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N40 ; ; vx_d_e_reg|a_reg_data[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #995: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|a_reg_data[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.129 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.131 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.670 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.129 ; 3.131 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.129 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|sclr ; +; 6.129 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N43 ; ; vx_d_e_reg|a_reg_data[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #996: Setup slack is -0.688 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.310 ; +; Data Required Time ; 5.622 ; +; Slack ; -0.688 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.027 ; ; ; ; ; ; +; Data Delay ; 3.312 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.850 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.310 ; 3.312 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.283 ; 0.715 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1017|dataf ; +; 6.310 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1017|combout ; +; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25]|d ; +; 6.310 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; +; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.622 ; 0.181 ; ; uTsu ; 1 ; FF_X107_Y149_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #997: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.234 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.236 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.796 ; 86 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.320 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.234 ; 3.236 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.355 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.143 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.170 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.176 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.542 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.570 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.574 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.206 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.234 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #998: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.286 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.288 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.882 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.284 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.286 ; 3.288 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.535 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.562 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.567 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.259 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|dataf ; +; 6.286 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|combout ; +; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|d ; +; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #999: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.285 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.051 ; ; ; ; ; ; +; Data Delay ; 3.287 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.832 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.333 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.285 ; 3.287 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.528 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.554 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.560 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.259 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|dataf ; +; 6.285 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|combout ; +; 6.285 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|d ; +; 6.285 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.447 ; 2.947 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; +; 5.447 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.417 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y163_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1000: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.774 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.227 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; +; 5.254 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; +; 5.259 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; +; 6.201 ; 0.942 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|datad ; +; 6.283 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|combout ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|d ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y162_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1001: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.299 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.301 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.855 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.299 ; 3.301 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.273 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; +; 6.299 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; +; 6.299 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; +; 6.299 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1002: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.808 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.434 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.467 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.243 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; +; 6.270 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1003: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.838 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.314 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.463 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.491 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.496 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.243 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; +; 6.271 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1004: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|a_reg_data[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.129 ; +; Data Required Time ; 5.442 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.131 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.670 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.340 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.129 ; 3.131 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.129 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|sclr ; +; 6.129 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.442 ; 0.054 ; ; uTsu ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1005: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_f_d_reg|curr_PC[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.152 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.154 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.730 ; 87 ; 0.119 ; 1.297 ; +; Cell ; ; 10 ; 0.302 ; 10 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.152 ; 3.154 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.488 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.822 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.850 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.855 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.152 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|ena ; +; 6.152 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N38 ; ; vx_f_d_reg|curr_PC[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1006: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_f_d_reg|curr_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.152 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.154 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.730 ; 87 ; 0.119 ; 1.297 ; +; Cell ; ; 10 ; 0.302 ; 10 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.152 ; 3.154 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.488 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.822 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.850 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.855 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.152 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|ena ; +; 6.152 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N32 ; ; vx_f_d_reg|curr_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1007: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.859 ; 87 ; 0.104 ; 1.366 ; +; Cell ; ; 12 ; 0.303 ; 9 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.254 ; 1.366 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|dataf ; +; 6.282 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|combout ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|d ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1008: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.150 ; +; Data Required Time ; 5.463 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.152 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.648 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.150 ; 3.152 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.150 ; 0.240 ; FF ; IC ; 1 ; FF_X71_Y159_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[18]|sload ; +; 6.150 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y159_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[18] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y159_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y159_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.463 ; 0.018 ; ; uTsu ; 1 ; FF_X71_Y159_N32 ; ; vx_fetch|VX_Warp_zero|real_PC[18] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1009: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.276 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.041 ; ; ; ; ; ; +; Data Delay ; 3.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.768 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.276 ; 3.278 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.398 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; +; 5.476 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; +; 5.481 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[11] ; +; 6.249 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y163_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~613|dataf ; +; 6.276 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y163_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~613|combout ; +; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5]|d ; +; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5]|clk ; +; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; +; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.162 ; ; uTsu ; 1 ; FF_X99_Y163_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1010: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.276 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.758 ; 84 ; 0.106 ; 1.228 ; +; Cell ; ; 12 ; 0.399 ; 12 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.276 ; 3.278 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.156 ; 1.228 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~79|datab ; +; 6.276 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~79|combout ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15]|d ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.168 ; ; uTsu ; 1 ; FF_X92_Y163_N1 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1011: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.150 ; +; Data Required Time ; 5.463 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.152 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.648 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.150 ; 3.152 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.150 ; 0.240 ; FF ; IC ; 1 ; FF_X71_Y159_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[2]|sload ; +; 6.150 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y159_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[2] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X71_Y159_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[2]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y159_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[2] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.463 ; 0.018 ; ; uTsu ; 1 ; FF_X71_Y159_N44 ; ; vx_fetch|VX_Warp_zero|real_PC[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1012: Setup slack is -0.687 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|csr_address[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.237 ; +; Data Required Time ; 5.550 ; +; Slack ; -0.687 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.239 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.643 ; 82 ; 0.192 ; 0.922 ; +; Cell ; ; 12 ; 0.475 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.237 ; 3.239 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.210 ; 0.922 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; +; 6.237 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; +; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; +; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1013: Setup slack is -0.686 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.292 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.686 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.294 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.770 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.292 ; 3.294 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.493 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.524 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.528 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.200 ; 0.672 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|datad ; +; 6.292 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|combout ; +; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|d ; +; 6.292 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1014: Setup slack is -0.686 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.686 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.769 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.406 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.483 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.487 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.255 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; +; 6.282 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1015: Setup slack is -0.686 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.287 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.686 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.289 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.778 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.287 ; 3.289 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.415 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.447 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.195 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.287 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; +; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1016: Setup slack is -0.686 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.258 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.686 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.745 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.258 ; 3.260 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.333 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.413 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.417 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.231 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; +; 6.258 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1017: Setup slack is -0.686 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.286 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.686 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.288 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.807 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.286 ; 3.288 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.469 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.497 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.503 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.203 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; +; 6.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; +; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; +; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1018: Setup slack is -0.686 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.686 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.884 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.270 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.378 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.405 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.411 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.246 ; 0.835 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|dataf ; +; 6.272 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~744|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1019: Setup slack is -0.686 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.240 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.686 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.076 ; ; ; ; ; ; +; Data Delay ; 3.242 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.780 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.147 ; 79 ; 0.000 ; 2.147 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.240 ; 3.242 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.377 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; +; 5.407 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; +; 5.411 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; +; 6.213 ; 0.802 ; RR ; IC ; 1 ; LABCELL_X83_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~488|dataf ; +; 6.240 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X83_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~488|combout ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8]|d ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.422 ; 2.922 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.212 ; 2.147 ; RR ; IC ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8]|clk ; +; 5.212 ; 0.000 ; RR ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; +; 5.422 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.392 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.162 ; ; uTsu ; 1 ; FF_X83_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1020: Setup slack is -0.686 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.274 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.686 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.276 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.813 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.274 ; 3.276 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.246 ; 0.703 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~687|dataf ; +; 6.274 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~687|combout ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15]|d ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.167 ; ; uTsu ; 1 ; FF_X92_Y163_N13 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1021: Setup slack is -0.686 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.279 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.686 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.281 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.749 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.411 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.279 ; 3.281 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.190 ; 0.264 ; RR ; IC ; 1 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11|dataf ; +; 5.218 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11|combout ; +; 5.224 ; 0.006 ; FF ; CELL ; 29 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11~la_mlab/laboutt[1] ; +; 6.201 ; 0.977 ; FF ; IC ; 1 ; LABCELL_X102_Y162_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~366|datac ; +; 6.279 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X102_Y162_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~366|combout ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14]|d ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.162 ; ; uTsu ; 1 ; FF_X102_Y162_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1022: Setup slack is -0.686 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|csr_address[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.550 ; +; Slack ; -0.686 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.113 ; ; ; ; ; ; +; Data Delay ; 3.244 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.658 ; 82 ; 0.192 ; 0.922 ; +; Cell ; ; 12 ; 0.459 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.236 ; 3.244 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.287 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.209 ; 0.922 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; +; 6.236 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1023: Setup slack is -0.685 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.685 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.816 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.244 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; +; 6.272 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1024: Setup slack is -0.685 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.685 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.816 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.660 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.244 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; +; 6.272 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1025: Setup slack is -0.685 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.284 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.685 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.286 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.820 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.284 ; 3.286 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.433 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.460 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.466 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.256 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; +; 6.284 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; +; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; +; 6.284 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1026: Setup slack is -0.685 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.278 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.685 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.280 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.868 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.292 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.278 ; 3.280 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.418 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.449 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.453 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.251 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; +; 6.278 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1027: Setup slack is -0.685 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.291 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.685 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.293 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.900 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.273 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.291 ; 3.293 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.263 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|dataf ; +; 6.291 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~778|combout ; +; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|d ; +; 6.291 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1028: Setup slack is -0.685 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|PC_next_out[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.100 ; +; Data Required Time ; 5.415 ; +; Slack ; -0.685 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.102 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.694 ; 87 ; 0.108 ; 0.829 ; +; Cell ; ; 10 ; 0.286 ; 9 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.100 ; 3.102 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.100 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; +; 6.100 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.415 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1029: Setup slack is -0.685 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.267 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.685 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.048 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.810 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.267 ; 3.269 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.486 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.513 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.517 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.239 ; 0.722 ; RR ; IC ; 1 ; MLABCELL_X92_Y160_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~561|dataf ; +; 6.267 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y160_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~561|combout ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17]|d ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17]|clk ; +; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; +; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.162 ; ; uTsu ; 1 ; FF_X92_Y160_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1030: Setup slack is -0.685 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|warp_num[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.238 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.685 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.240 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.648 ; 82 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.471 ; 15 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.238 ; 3.240 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.117 ; 0.702 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N6 ; High Speed ; vx_d_e_reg|i602~4|datab ; +; 6.238 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N6 ; High Speed ; vx_d_e_reg|i602~4|combout ; +; 6.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N8 ; High Speed ; vx_d_e_reg|warp_num[4]|d ; +; 6.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N8 ; High Speed ; vx_d_e_reg|warp_num[4] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X80_Y153_N8 ; High Speed ; vx_d_e_reg|warp_num[4]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N8 ; High Speed ; vx_d_e_reg|warp_num[4] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.165 ; ; uTsu ; 1 ; FF_X80_Y153_N8 ; ; vx_d_e_reg|warp_num[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1031: Setup slack is -0.685 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.290 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.685 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.292 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.831 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.290 ; 3.292 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.262 ; 0.665 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|dataf ; +; 6.290 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|combout ; +; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE|d ; +; 6.290 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y150_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1032: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.577 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.263 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.854 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.261 ; 3.263 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.511 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.233 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|dataf ; +; 6.261 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|combout ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|d ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.577 ; 0.163 ; ; uTsu ; 1 ; FF_X93_Y162_N53 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1033: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.712 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.441 ; 13 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.371 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.451 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.455 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.191 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; +; 6.273 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|d ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y164_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1034: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.298 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.300 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.784 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.298 ; 3.300 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.557 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.212 ; 0.655 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|datac ; +; 6.298 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|combout ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|d ; +; 6.298 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X103_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1035: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.278 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.280 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.769 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.278 ; 3.280 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.227 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; +; 5.254 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; +; 5.259 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; +; 6.196 ; 0.937 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|datad ; +; 6.278 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|combout ; +; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|d ; +; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1036: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.232 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.234 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.634 ; 81 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.478 ; 15 ; 0.000 ; 0.127 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.232 ; 3.234 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.105 ; 0.751 ; FF ; IC ; 1 ; LABCELL_X79_Y151_N6 ; High Speed ; vx_d_e_reg|i385~6|dataa ; +; 6.232 ; 0.127 ; FR ; CELL ; 1 ; LABCELL_X79_Y151_N6 ; High Speed ; vx_d_e_reg|i385~6|combout ; +; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|d ; +; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1037: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.280 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.788 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.373 ; 11 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.280 ; 3.282 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.404 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.481 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.485 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.253 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; +; 6.280 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1038: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.277 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.812 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.275 ; 3.277 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.248 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; +; 6.275 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1039: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.262 ; +; Data Required Time ; 5.578 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.264 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.800 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.262 ; 3.264 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.235 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; +; 6.262 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1040: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.677 ; 82 ; 0.133 ; 0.712 ; +; Cell ; ; 14 ; 0.474 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.270 ; 3.278 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.722 ; 0.540 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; +; 3.750 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.754 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.887 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.970 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.975 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.326 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.419 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.424 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.081 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.174 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.180 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.464 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.490 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.496 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.208 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.270 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1041: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|PC_next_out[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.100 ; +; Data Required Time ; 5.416 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.102 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.694 ; 87 ; 0.108 ; 0.829 ; +; Cell ; ; 10 ; 0.286 ; 9 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.100 ; 3.102 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.100 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; +; 6.100 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.416 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1042: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.764 ; 84 ; 0.110 ; 1.302 ; +; Cell ; ; 12 ; 0.400 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.166 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; +; 6.283 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1043: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[24] ; +; To Node ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.097 ; +; Data Required Time ; 5.413 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.126 ; ; ; ; ; ; +; Data Delay ; 3.120 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.350 ; 79 ; 0.000 ; 2.350 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 4 ; 2.747 ; 88 ; 0.541 ; 0.817 ; +; Cell ; ; 8 ; 0.250 ; 8 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.158 ; 79 ; 0.000 ; 2.158 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.977 ; 2.977 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.977 ; 2.350 ; RR ; IC ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]|clk ; +; 2.977 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24] ; +; 6.097 ; 3.120 ; ; ; ; ; ; data path ; +; 3.100 ; 0.123 ; RR ; uTco ; 1 ; FF_X91_Y153_N23 ; ; vx_f_d_reg|instruction[24]|q ; +; 3.189 ; 0.089 ; RR ; CELL ; 138 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]~la_lab/laboutt[15] ; +; 3.730 ; 0.541 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|datac ; +; 3.821 ; 0.091 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; +; 3.827 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; +; 4.504 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; +; 4.531 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; +; 4.535 ; 0.004 ; RR ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; +; 5.247 ; 0.712 ; RR ; IC ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|dataf ; +; 5.275 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|combout ; +; 5.280 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4~la_lab/laboutb[19] ; +; 6.097 ; 0.817 ; FF ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|d ; +; 6.097 ; 0.000 ; FF ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.351 ; 2.851 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.223 ; 2.158 ; RR ; IC ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE|clk ; +; 5.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N16 ; High Speed ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; +; 5.351 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.321 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.413 ; 0.092 ; ; uTsu ; 1 ; FF_X38_Y157_N16 ; ; vx_csr_handler|decode_csr_address[4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1044: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.758 ; 84 ; 0.106 ; 1.228 ; +; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.156 ; 1.228 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~47|datab ; +; 6.273 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~47|combout ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15]|d ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.168 ; ; uTsu ; 1 ; FF_X92_Y163_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1045: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.284 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.286 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.860 ; 87 ; 0.106 ; 1.317 ; +; Cell ; ; 12 ; 0.305 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.284 ; 3.286 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.258 ; 1.317 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~363|dataf ; +; 6.284 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~363|combout ; +; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11]|d ; +; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1046: Setup slack is -0.684 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.684 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.708 ; 82 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.456 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.494 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.190 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|datad ; +; 6.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|combout ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]|d ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N50 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1047: Setup slack is -0.683 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.232 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.683 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.234 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.597 ; 80 ; 0.127 ; 0.668 ; +; Cell ; ; 14 ; 0.516 ; 16 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.232 ; 3.234 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; +; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.077 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.157 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.162 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.289 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.410 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.415 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.072 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.165 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.171 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.537 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.565 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.569 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.204 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.232 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1048: Setup slack is -0.683 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.231 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.683 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.233 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.596 ; 80 ; 0.127 ; 0.668 ; +; Cell ; ; 14 ; 0.516 ; 16 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.231 ; 3.233 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; +; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.077 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.157 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.162 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.289 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.410 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.415 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.072 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.165 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.171 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.537 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.565 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.569 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.203 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.231 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1049: Setup slack is -0.683 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.287 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.683 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.289 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.881 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.287 ; 3.289 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.334 ; 0.437 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|dataf ; +; 5.363 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|combout ; +; 5.367 ; 0.004 ; RR ; CELL ; 16 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14~la_lab/laboutt[4] ; +; 6.260 ; 0.893 ; RR ; IC ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|dataf ; +; 6.287 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|combout ; +; 6.287 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|d ; +; 6.287 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y159_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1050: Setup slack is -0.683 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.683 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.804 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.332 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.429 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.505 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.509 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.229 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|dataf ; +; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|combout ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|d ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1051: Setup slack is -0.683 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.683 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.825 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.469 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.501 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.505 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.256 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|dataf ; +; 6.282 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|combout ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|d ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1052: Setup slack is -0.683 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.683 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.712 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.441 ; 13 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.371 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.451 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.455 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.191 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; +; 6.273 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|d ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1053: Setup slack is -0.683 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.683 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.810 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.239 ; 0.681 ; RR ; IC ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|dataf ; +; 6.266 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|combout ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|d ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1054: Setup slack is -0.683 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|csr_address[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.234 ; +; Data Required Time ; 5.551 ; +; Slack ; -0.683 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.236 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.800 ; 87 ; 0.108 ; 0.935 ; +; Cell ; ; 12 ; 0.314 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.234 ; 3.236 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.206 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; +; 6.234 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; +; 6.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; +; 6.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1055: Setup slack is -0.683 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.153 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.683 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.155 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.731 ; 87 ; 0.116 ; 1.398 ; +; Cell ; ; 10 ; 0.303 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.153 ; 3.155 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.388 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.722 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.750 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.755 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.153 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.153 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1056: Setup slack is -0.683 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.278 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.683 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.280 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.905 ; 89 ; 0.114 ; 1.354 ; +; Cell ; ; 12 ; 0.253 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.278 ; 3.280 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.250 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; +; 6.278 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; +; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|d ; +; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1057: Setup slack is -0.683 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.683 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.859 ; 87 ; 0.106 ; 1.316 ; +; Cell ; ; 12 ; 0.305 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.257 ; 1.316 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|dataf ; +; 6.283 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|combout ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|d ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1058: Setup slack is -0.683 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.287 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.683 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.289 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.826 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.287 ; 3.289 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.259 ; 0.716 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~692|dataf ; +; 6.287 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X99_Y145_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~692|combout ; +; 6.287 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20]|d ; +; 6.287 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X99_Y145_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1059: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.229 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.231 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.594 ; 80 ; 0.127 ; 0.668 ; +; Cell ; ; 14 ; 0.516 ; 16 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.229 ; 3.231 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; +; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.077 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.157 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.162 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.289 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.410 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.415 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.072 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.165 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.171 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.537 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.565 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.569 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.201 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.229 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1060: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.159 ; +; Data Required Time ; 5.477 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.161 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.721 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.159 ; 3.161 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.159 ; 0.346 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|sload ; +; 6.159 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.477 ; 0.034 ; ; uTsu ; 1 ; FF_X73_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1061: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.295 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.297 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.772 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.403 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.295 ; 3.297 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.469 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.501 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.505 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.203 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|datac ; +; 6.295 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|combout ; +; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|d ; +; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1062: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.853 ; 87 ; 0.119 ; 1.046 ; +; Cell ; ; 14 ; 0.299 ; 9 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.604 ; 0.119 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.631 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.636 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.682 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.708 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.712 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.837 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.861 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.867 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.271 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.297 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.303 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.243 ; 0.940 ; FF ; IC ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|dataf ; +; 6.272 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|combout ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|d ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.162 ; ; uTsu ; 1 ; FF_X109_Y154_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1063: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_address[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.187 ; +; Data Required Time ; 5.505 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.125 ; ; ; ; ; ; +; Data Delay ; 3.189 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.661 ; 83 ; 0.119 ; 0.821 ; +; Cell ; ; 12 ; 0.406 ; 13 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.187 ; 3.189 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.362 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.114 ; 0.752 ; RR ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datae ; +; 6.187 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; +; 6.187 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; +; 6.187 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; +; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1064: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.286 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.288 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.760 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.286 ; 3.288 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.313 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; +; 5.343 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; +; 5.347 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; +; 6.200 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; +; 6.286 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; +; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; +; 6.286 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1065: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.295 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.297 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.771 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.405 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.295 ; 3.297 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.433 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.464 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.468 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.208 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; +; 6.295 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; +; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; +; 6.295 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1066: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.276 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.760 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.276 ; 3.278 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.437 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.464 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.469 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.194 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; +; 6.276 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1067: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.230 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.627 ; 81 ; 0.133 ; 0.657 ; +; Cell ; ; 14 ; 0.485 ; 15 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.230 ; 3.238 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.687 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; +; 3.763 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.767 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.900 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.983 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.988 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.339 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.432 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.437 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.094 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.187 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.193 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.559 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.587 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.591 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.203 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.230 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1068: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++----------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+-------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.821 ; 87 ; 0.108 ; 0.910 ; +; Cell ; ; 12 ; 0.297 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.208 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; +; 6.236 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; +; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|d ; +; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1069: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.288 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.296 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.644 ; 80 ; 0.142 ; 0.755 ; +; Cell ; ; 14 ; 0.527 ; 16 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.288 ; 3.296 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.253 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.008 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.035 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.041 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.212 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.288 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1070: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.809 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.555 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; +; 6.243 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|dataf ; +; 6.271 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|combout ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]|d ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y147_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1071: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|csr_address[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.231 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.233 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.637 ; 82 ; 0.192 ; 0.916 ; +; Cell ; ; 12 ; 0.475 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.231 ; 3.233 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.204 ; 0.916 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; +; 6.231 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; +; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; +; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.200 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1072: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.289 ; +; Data Required Time ; 5.607 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.291 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.711 ; 82 ; 0.108 ; 0.868 ; +; Cell ; ; 14 ; 0.459 ; 14 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.289 ; 3.291 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.057 ; 0.642 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~35|dataf ; +; 6.083 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~35|combout ; +; 6.089 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~35~la_mlab/laboutb[7] ; +; 6.212 ; 0.123 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|datae ; +; 6.289 ; 0.077 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|combout ; +; 6.289 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|d ; +; 6.289 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.607 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y158_N49 ; ; vx_fetch|VX_Warp_three|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1073: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.764 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.543 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.196 ; 0.653 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1002|datac ; +; 6.282 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1002|combout ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10]|d ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y157_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1074: Setup slack is -0.682 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.682 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.807 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.357 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.494 ; 0.006 ; FF ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.257 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X90_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~924|dataf ; +; 6.283 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X90_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~924|combout ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28]|d ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.182 ; ; uTsu ; 1 ; FF_X90_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1075: Setup slack is -0.681 (VIOLATED) +=============================================================================== ++----------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------+ +; Property ; Value ; ++--------------------+-------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.681 (VIOLATED) ; ++--------------------+-------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.583 ; 79 ; 0.192 ; 0.657 ; +; Cell ; ; 14 ; 0.565 ; 17 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; +; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.530 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.556 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.562 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.161 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.268 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1076: Setup slack is -0.681 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.280 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.681 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.288 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.662 ; 81 ; 0.118 ; 0.734 ; +; Cell ; ; 14 ; 0.499 ; 15 ; 0.000 ; 0.111 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.280 ; 3.288 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; +; 3.942 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.946 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.085 ; 0.139 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.164 ; 0.079 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.169 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.287 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.398 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.403 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.086 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.177 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.183 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.891 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.919 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.925 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.205 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.280 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1077: Setup slack is -0.681 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[12] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.159 ; +; Data Required Time ; 5.478 ; +; Slack ; -0.681 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.161 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.721 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.159 ; 3.161 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.159 ; 0.346 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|sload ; +; 6.159 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.478 ; 0.035 ; ; uTsu ; 1 ; FF_X73_Y161_N46 ; ; vx_fetch|VX_Warp_zero|real_PC[12] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1078: Setup slack is -0.681 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.258 ; +; Data Required Time ; 5.577 ; +; Slack ; -0.681 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.058 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.804 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.165 ; 79 ; 0.000 ; 2.165 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.258 ; 3.260 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.355 ; 0.454 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|dataf ; +; 5.384 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|combout ; +; 5.388 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29~la_lab/laboutb[14] ; +; 6.232 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|dataf ; +; 6.258 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|combout ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|d ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.440 ; 2.940 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.230 ; 2.165 ; RR ; IC ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|clk ; +; 5.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; +; 5.440 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.410 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.577 ; 0.167 ; ; uTsu ; 1 ; FF_X88_Y164_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1079: Setup slack is -0.681 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.681 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.762 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.192 ; 0.304 ; FF ; IC ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|dataf ; +; 5.221 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|combout ; +; 5.225 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9~la_lab/laboutb[16] ; +; 6.190 ; 0.965 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|datad ; +; 6.281 ; 0.091 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|combout ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|d ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1080: Setup slack is -0.681 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.579 ; +; Slack ; -0.681 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.802 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.479 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.508 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.514 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; +; 6.233 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|dataf ; +; 6.260 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1081: Setup slack is -0.681 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.681 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.808 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.244 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; +; 6.271 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1082: Setup slack is -0.681 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|b_reg_data[28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.234 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.681 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.236 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.800 ; 87 ; 0.119 ; 0.877 ; +; Cell ; ; 12 ; 0.316 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.234 ; 3.236 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.207 ; 0.877 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|dataf ; +; 6.234 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|combout ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|d ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1083: Setup slack is -0.681 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|b_reg_data[24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.681 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.821 ; 87 ; 0.108 ; 0.910 ; +; Cell ; ; 12 ; 0.297 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.208 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; +; 6.236 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; +; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|d ; +; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N17 ; ; vx_d_e_reg|b_reg_data[24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1084: Setup slack is -0.681 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.278 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.681 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.280 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.905 ; 89 ; 0.114 ; 1.354 ; +; Cell ; ; 12 ; 0.253 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.278 ; 3.280 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.250 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; +; 6.278 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; +; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|d ; +; 6.278 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1085: Setup slack is -0.681 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|csr_address[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.230 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.681 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.113 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.652 ; 82 ; 0.192 ; 0.916 ; +; Cell ; ; 12 ; 0.459 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.230 ; 3.238 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.287 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.203 ; 0.916 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; +; 6.230 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; +; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; +; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.200 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1086: Setup slack is -0.681 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.681 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.809 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.555 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; +; 6.243 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|dataf ; +; 6.271 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|combout ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE|d ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1087: Setup slack is -0.681 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.579 ; +; Slack ; -0.681 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.783 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.493 ; 0.005 ; FF ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.232 ; 0.739 ; FF ; IC ; 1 ; LABCELL_X93_Y162_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~904|dataf ; +; 6.260 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X93_Y162_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~904|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1088: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++---------------------------------------------+ +; Path Summary ; ++--------------------+------------------------+ +; Property ; Value ; ++--------------------+------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.267 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.583 ; 79 ; 0.192 ; 0.657 ; +; Cell ; ; 14 ; 0.564 ; 17 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.267 ; 3.269 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; +; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.246 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.530 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.556 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.562 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.161 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.267 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1089: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.290 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.667 ; 81 ; 0.117 ; 0.714 ; +; Cell ; ; 14 ; 0.498 ; 15 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.282 ; 3.290 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.895 ; 0.710 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.018 ; 0.123 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.024 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.141 ; 0.117 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; +; 4.167 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.172 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.355 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.412 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.417 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.100 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.191 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.197 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.911 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.941 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.947 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.207 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.282 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1090: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.267 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.674 ; 82 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.473 ; 14 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.267 ; 3.269 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.529 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.555 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.561 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.160 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.267 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1091: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.794 ; 85 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.354 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.355 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.143 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.170 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.176 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.460 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.486 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.492 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.204 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.266 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1092: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.159 ; +; Data Required Time ; 5.479 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.161 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.721 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.159 ; 3.161 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.159 ; 0.346 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|sload ; +; 6.159 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.479 ; 0.036 ; ; uTsu ; 1 ; FF_X73_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1093: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.263 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.856 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.261 ; 3.263 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.515 ; 0.006 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[3] ; +; 6.234 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|dataf ; +; 6.261 ; 0.027 ; RR ; CELL ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|combout ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|d ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y159_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1094: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.284 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.286 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.820 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.284 ; 3.286 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.481 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.198 ; 0.717 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|datac ; +; 6.284 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|combout ; +; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|d ; +; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X107_Y157_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1095: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.284 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.286 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.779 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.284 ; 3.286 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.311 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; +; 5.341 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; +; 5.345 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; +; 6.198 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; +; 6.284 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; +; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; +; 6.284 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1096: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|csr_address[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.192 ; +; Data Required Time ; 5.512 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.121 ; ; ; ; ; ; +; Data Delay ; 3.194 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.677 ; 84 ; 0.119 ; 0.821 ; +; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.192 ; 3.194 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.336 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.119 ; 0.783 ; RR ; IC ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|datae ; +; 6.192 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|combout ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|d ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.377 ; 2.877 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; +; 5.377 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.347 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.512 ; 0.165 ; ; uTsu ; 1 ; FF_X49_Y149_N28 ; ; vx_d_e_reg|csr_address[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1097: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.849 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.304 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.413 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.444 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.448 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.246 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; +; 6.273 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1098: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.280 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 85 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.370 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.280 ; 3.282 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.463 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.491 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.497 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.197 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; +; 6.280 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; +; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; +; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1099: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|b_reg_data[19] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.234 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.236 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.819 ; 87 ; 0.108 ; 0.908 ; +; Cell ; ; 12 ; 0.297 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.234 ; 3.236 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.206 ; 0.908 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|dataf ; +; 6.234 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|combout ; +; 6.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|d ; +; 6.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N22 ; ; vx_d_e_reg|b_reg_data[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1100: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.277 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.902 ; 89 ; 0.114 ; 1.351 ; +; Cell ; ; 12 ; 0.253 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.275 ; 3.277 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.247 ; 1.351 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|dataf ; +; 6.275 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|combout ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|d ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1101: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.288 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.296 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.644 ; 80 ; 0.142 ; 0.755 ; +; Cell ; ; 14 ; 0.527 ; 16 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.288 ; 3.296 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.253 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.008 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.035 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.041 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.212 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.288 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1102: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|b_reg_data[15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.238 ; +; Data Required Time ; 5.558 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.240 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.740 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.379 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.238 ; 3.240 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.414 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.208 ; 0.794 ; FF ; IC ; 1 ; MLABCELL_X80_Y152_N57 ; High Speed ; vx_d_e_reg|i385~48|dataf ; +; 6.238 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X80_Y152_N57 ; High Speed ; vx_d_e_reg|i385~48|combout ; +; 6.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y152_N59 ; High Speed ; vx_d_e_reg|b_reg_data[15]|d ; +; 6.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y152_N59 ; High Speed ; vx_d_e_reg|b_reg_data[15] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X80_Y152_N59 ; High Speed ; vx_d_e_reg|b_reg_data[15]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y152_N59 ; High Speed ; vx_d_e_reg|b_reg_data[15] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.558 ; 0.170 ; ; uTsu ; 1 ; FF_X80_Y152_N59 ; ; vx_d_e_reg|b_reg_data[15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1103: Setup slack is -0.680 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|PC_next_out[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.082 ; +; Data Required Time ; 5.402 ; +; Slack ; -0.680 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.073 ; ; ; ; ; ; +; Data Delay ; 3.090 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.547 ; 82 ; 0.142 ; 0.829 ; +; Cell ; ; 10 ; 0.418 ; 14 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.082 ; 3.090 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.253 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.082 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; +; 6.082 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; +; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.402 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1104: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.674 ; 82 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.472 ; 14 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.245 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.529 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.555 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.561 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.160 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.266 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1105: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.280 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.874 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.280 ; 3.282 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.253 ; 0.687 ; RR ; IC ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|dataf ; +; 6.280 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|combout ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|d ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y144_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1106: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.279 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.281 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.872 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.279 ; 3.281 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.478 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.509 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.513 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.252 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|dataf ; +; 6.279 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|combout ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|d ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X102_Y161_N4 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1107: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.278 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.280 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.824 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.278 ; 3.280 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.527 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.554 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.559 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.251 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|dataf ; +; 6.278 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|combout ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|d ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1108: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.277 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.279 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.825 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.332 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.277 ; 3.279 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.438 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.515 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.519 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.251 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|dataf ; +; 6.277 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|combout ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|d ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1109: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.274 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.276 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.755 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.274 ; 3.276 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.455 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.484 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.489 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.195 ; 0.706 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; +; 6.274 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; +; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; +; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1110: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_mask[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.564 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.745 ; 85 ; 0.108 ; 0.862 ; +; Cell ; ; 12 ; 0.378 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.215 ; 0.862 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N33 ; High Speed ; vx_d_e_reg|i531~3|dataf ; +; 6.243 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N33 ; High Speed ; vx_d_e_reg|i531~3|combout ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3]|d ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N35 ; ; vx_d_e_reg|csr_mask[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1111: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_mask[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.564 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.744 ; 85 ; 0.108 ; 0.861 ; +; Cell ; ; 12 ; 0.379 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.214 ; 0.861 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N36 ; High Speed ; vx_d_e_reg|i531~2|dataf ; +; 6.243 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N36 ; High Speed ; vx_d_e_reg|i531~2|combout ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2]|d ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N38 ; ; vx_d_e_reg|csr_mask[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1112: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.798 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.434 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.467 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.233 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; +; 6.260 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1113: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.821 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.491 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.517 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.523 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.255 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; +; 6.281 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1114: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|b_reg_data[31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.232 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.234 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.816 ; 87 ; 0.108 ; 0.905 ; +; Cell ; ; 12 ; 0.298 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.232 ; 3.234 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.203 ; 0.905 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|dataf ; +; 6.232 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|combout ; +; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|d ; +; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N25 ; ; vx_d_e_reg|b_reg_data[31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1115: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.285 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.287 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.764 ; 84 ; 0.110 ; 1.302 ; +; Cell ; ; 12 ; 0.402 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.285 ; 3.287 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.166 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; +; 6.285 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; +; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; +; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1116: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.227 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.235 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.659 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.227 ; 3.235 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.143 ; 0.136 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.234 ; 0.091 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.240 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.355 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.381 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.386 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.106 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.184 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.190 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.556 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.584 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.588 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.200 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.227 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1117: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.280 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.820 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.280 ; 3.282 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.253 ; 0.710 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|dataf ; +; 6.280 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|combout ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]|d ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y145_N29 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1118: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_address[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.229 ; +; Data Required Time ; 5.550 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.113 ; ; ; ; ; ; +; Data Delay ; 3.237 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.644 ; 82 ; 0.138 ; 0.922 ; +; Cell ; ; 12 ; 0.468 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.229 ; 3.237 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.280 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.202 ; 0.922 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; +; 6.229 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; +; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; +; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1119: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|PC_next_out[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.082 ; +; Data Required Time ; 5.403 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.073 ; ; ; ; ; ; +; Data Delay ; 3.090 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.547 ; 82 ; 0.142 ; 0.829 ; +; Cell ; ; 10 ; 0.418 ; 14 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.082 ; 3.090 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.253 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.082 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; +; 6.082 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; +; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.403 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1120: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.285 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.287 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.774 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.285 ; 3.287 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.541 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.205 ; 0.664 ; RR ; IC ; 1 ; LABCELL_X104_Y147_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~978|datad ; +; 6.285 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y147_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~978|combout ; +; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18]|d ; +; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.167 ; ; uTsu ; 1 ; FF_X104_Y147_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1121: Setup slack is -0.679 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.679 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.277 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.817 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.275 ; 3.277 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.481 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.508 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.514 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.249 ; 0.735 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~927|dataf ; +; 6.275 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~927|combout ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31]|d ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X98_Y143_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1122: Setup slack is -0.678 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.678 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.818 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.256 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; +; 6.283 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1123: Setup slack is -0.678 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.678 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.741 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.373 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; +; 5.453 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; +; 5.458 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; +; 6.231 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; +; 6.259 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1124: Setup slack is -0.678 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.280 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.678 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.288 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.698 ; 82 ; 0.136 ; 0.714 ; +; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.280 ; 3.288 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.712 ; 0.549 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; +; 3.740 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.744 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.880 ; 0.136 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.959 ; 0.079 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.964 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.320 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.410 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.415 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.098 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.189 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.195 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.909 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.939 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.945 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.205 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.280 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1125: Setup slack is -0.678 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|csr_address[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.228 ; +; Data Required Time ; 5.550 ; +; Slack ; -0.678 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.230 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.795 ; 87 ; 0.108 ; 0.930 ; +; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.228 ; 3.230 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.201 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; +; 6.228 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; +; 6.228 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; +; 6.228 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1126: Setup slack is -0.678 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.678 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.837 ; 87 ; 0.114 ; 1.378 ; +; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.242 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.272 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1127: Setup slack is -0.678 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.280 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.678 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.820 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.280 ; 3.282 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.253 ; 0.685 ; RR ; IC ; 1 ; LABCELL_X102_Y147_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1013|dataf ; +; 6.280 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y147_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1013|combout ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21]|d ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y147_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1128: Setup slack is -0.678 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|rs1[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.224 ; +; Data Required Time ; 5.546 ; +; Slack ; -0.678 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.084 ; ; ; ; ; ; +; Data Delay ; 3.226 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.678 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.427 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.139 ; 79 ; 0.000 ; 2.139 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.224 ; 3.226 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.147 ; 0.732 ; FF ; IC ; 1 ; LABCELL_X81_Y156_N33 ; High Speed ; vx_d_e_reg|i316~2|datac ; +; 6.224 ; 0.077 ; FR ; CELL ; 1 ; LABCELL_X81_Y156_N33 ; High Speed ; vx_d_e_reg|i316~2|combout ; +; 6.224 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y156_N35 ; High Speed ; vx_d_e_reg|rs1[2]|d ; +; 6.224 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y156_N35 ; High Speed ; vx_d_e_reg|rs1[2] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.414 ; 2.914 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.204 ; 2.139 ; RR ; IC ; 1 ; FF_X81_Y156_N35 ; High Speed ; vx_d_e_reg|rs1[2]|clk ; +; 5.204 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y156_N35 ; High Speed ; vx_d_e_reg|rs1[2] ; +; 5.414 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.384 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.546 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y156_N35 ; ; vx_d_e_reg|rs1[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1129: Setup slack is -0.678 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.678 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.708 ; 82 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.456 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.494 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.190 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|datad ; +; 6.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|combout ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE|d ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X103_Y161_N49 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1130: Setup slack is -0.678 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.280 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.678 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.820 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.280 ; 3.282 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.253 ; 0.710 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|dataf ; +; 6.280 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|combout ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE|d ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X99_Y145_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1131: Setup slack is -0.678 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[7] ; +; To Node ; vx_e_m_reg|csr_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.277 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.678 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.366 ; 79 ; 0.000 ; 2.366 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.712 ; 83 ; 0.122 ; 1.025 ; +; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.993 ; 2.993 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.993 ; 2.366 ; RR ; IC ; 1 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7]|clk ; +; 2.993 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7] ; +; 6.277 ; 3.284 ; ; ; ; ; ; data path ; +; 3.116 ; 0.123 ; RR ; uTco ; 1 ; FF_X51_Y160_N17 ; ; vx_csr_handler|decode_csr_address[7]|q ; +; 3.212 ; 0.096 ; RR ; CELL ; 224 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7]~la_lab/laboutt[11] ; +; 4.237 ; 1.025 ; RR ; IC ; 1 ; MLABCELL_X39_Y145_N3 ; High Speed ; vx_csr_handler|Mux_3~174|datac ; +; 4.330 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X39_Y145_N3 ; High Speed ; vx_csr_handler|Mux_3~174|combout ; +; 4.336 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X39_Y145_N3 ; High Speed ; vx_csr_handler|Mux_3~174~la_mlab/laboutt[3] ; +; 4.481 ; 0.145 ; RR ; IC ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|datae ; +; 4.556 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|combout ; +; 4.561 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190~la_lab/laboutb[9] ; +; 5.077 ; 0.516 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|dataf ; +; 5.103 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; +; 5.107 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; +; 5.234 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; +; 5.317 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.321 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.098 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.124 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.129 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.251 ; 0.122 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; +; 6.277 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; +; 6.277 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; +; 6.277 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; +; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1132: Setup slack is -0.677 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.276 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.677 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.697 ; 82 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.114 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.276 ; 3.284 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.153 ; 0.145 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataf ; +; 4.180 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.186 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.301 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.327 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.332 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.095 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.173 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.179 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.887 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.915 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.921 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.201 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.276 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1133: Setup slack is -0.677 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.677 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.809 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.433 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.460 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.466 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.245 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; +; 6.273 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1134: Setup slack is -0.677 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.677 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.864 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.284 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.514 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.241 ; 0.727 ; RR ; IC ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|dataf ; +; 6.268 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|combout ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|d ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y162_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1135: Setup slack is -0.677 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.677 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.861 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.511 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.240 ; 0.729 ; RR ; IC ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|dataf ; +; 6.268 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|combout ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|d ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y161_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1136: Setup slack is -0.677 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.677 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.859 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.477 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.509 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.237 ; 0.728 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|dataf ; +; 6.264 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|combout ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|d ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1137: Setup slack is -0.677 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.276 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.677 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.749 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.408 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.276 ; 3.278 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.404 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.431 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.436 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.184 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.276 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1138: Setup slack is -0.677 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.677 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.774 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.379 ; 12 ; 0.000 ; 0.079 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.453 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.482 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.487 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.193 ; 0.706 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; +; 6.272 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1139: Setup slack is -0.677 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.677 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.871 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.378 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.405 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.411 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.233 ; 0.822 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|dataf ; +; 6.260 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~751|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1140: Setup slack is -0.677 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.677 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.755 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.408 ; 12 ; 0.000 ; 0.094 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.519 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.548 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.553 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.188 ; 0.635 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~647|datac ; +; 6.282 ; 0.094 ; RR ; CELL ; 1 ; MLABCELL_X105_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~647|combout ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7]|d ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1141: Setup slack is -0.677 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.577 ; +; Slack ; -0.677 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.053 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.744 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.170 ; 79 ; 0.000 ; 2.170 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.437 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; +; 5.517 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; +; 5.522 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; +; 6.227 ; 0.705 ; RR ; IC ; 1 ; LABCELL_X89_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~744|dataf ; +; 6.254 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~744|combout ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8]|d ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.445 ; 2.945 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.235 ; 2.170 ; RR ; IC ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8]|clk ; +; 5.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; +; 5.445 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.415 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.577 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y162_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1142: Setup slack is -0.677 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.276 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.677 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.033 ; ; ; ; ; ; +; Data Delay ; 3.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.755 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.276 ; 3.278 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.446 ; 0.529 ; RR ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.518 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.522 ; 0.004 ; FF ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.248 ; 0.726 ; FF ; IC ; 1 ; MLABCELL_X105_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~810|dataf ; +; 6.276 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X105_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~810|combout ; +; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10]|d ; +; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10]|clk ; +; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; +; 5.465 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.164 ; ; uTsu ; 1 ; FF_X105_Y157_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1143: Setup slack is -0.677 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.677 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.770 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.201 ; 0.604 ; RR ; IC ; 1 ; LABCELL_X104_Y147_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~978|datad ; +; 6.281 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y147_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~978|combout ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18]|d ; +; 6.281 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y147_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1144: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.857 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.478 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.509 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.513 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.237 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|dataf ; +; 6.264 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|combout ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|d ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1145: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.287 ; +; Data Required Time ; 5.611 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.289 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.781 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.287 ; 3.289 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.438 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.515 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.519 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.207 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|datac ; +; 6.287 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|combout ; +; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|d ; +; 6.287 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1146: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.277 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.870 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.275 ; 3.277 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.477 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.509 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.248 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|dataf ; +; 6.275 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|combout ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|d ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X108_Y157_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1147: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.577 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.796 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.503 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.225 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|dataf ; +; 6.253 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|combout ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|d ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.577 ; 0.163 ; ; uTsu ; 1 ; FF_X93_Y162_N53 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1148: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.758 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.406 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.483 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.488 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; +; 6.245 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; +; 6.272 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1149: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.837 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.254 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; +; 6.281 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1150: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.257 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.760 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.378 ; 12 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.257 ; 3.259 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.371 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; +; 5.451 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; +; 5.456 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; +; 6.229 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; +; 6.257 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1151: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.288 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.290 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.826 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.288 ; 3.290 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.262 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; +; 6.288 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1152: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|b_reg_data[25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.229 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.077 ; ; ; ; ; ; +; Data Delay ; 3.231 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.743 ; 85 ; 0.108 ; 0.876 ; +; Cell ; ; 12 ; 0.367 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.229 ; 3.231 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.202 ; 0.876 ; FF ; IC ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|dataf ; +; 6.229 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|combout ; +; 6.229 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|d ; +; 6.229 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|clk ; +; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; +; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.162 ; ; uTsu ; 1 ; FF_X80_Y149_N44 ; ; vx_d_e_reg|b_reg_data[25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1153: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|b_reg_data[30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.230 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.232 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.794 ; 86 ; 0.108 ; 0.929 ; +; Cell ; ; 12 ; 0.316 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.230 ; 3.232 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.201 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; +; 6.230 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; +; 6.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; +; 6.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1154: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.068 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.070 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.628 ; 86 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.068 ; 3.070 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.068 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|sclr ; +; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N25 ; ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1155: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|a_reg_data[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.068 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.070 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.628 ; 86 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.068 ; 3.070 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.068 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|sclr ; +; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N26 ; ; vx_d_e_reg|a_reg_data[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1156: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|a_reg_data[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.068 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.070 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.628 ; 86 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.068 ; 3.070 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.068 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|sclr ; +; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N16 ; ; vx_d_e_reg|a_reg_data[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1157: Setup slack is -0.676 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.676 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.856 ; 87 ; 0.104 ; 1.378 ; +; Cell ; ; 12 ; 0.295 ; 9 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.240 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.270 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1158: Setup slack is -0.675 (VIOLATED) +=============================================================================== ++----------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------+ +; Property ; Value ; ++--------------------+-------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.675 (VIOLATED) ; ++--------------------+-------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.263 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.592 ; 79 ; 0.127 ; 0.712 ; +; Cell ; ; 14 ; 0.550 ; 17 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.261 ; 3.263 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; +; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.077 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.157 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.162 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.289 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.410 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.415 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.072 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.165 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.171 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.455 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.481 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.487 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.199 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.261 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1159: Setup slack is -0.675 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.675 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.702 ; 82 ; 0.107 ; 0.854 ; +; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.066 ; 0.712 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33|dataf ; +; 6.094 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33|combout ; +; 6.100 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33~la_mlab/laboutt[11] ; +; 6.207 ; 0.107 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|datae ; +; 6.283 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|combout ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|d ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y158_N25 ; ; vx_fetch|VX_Warp_one|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1160: Setup slack is -0.675 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.675 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.710 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.039 ; 0.713 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|dataf ; +; 6.069 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|combout ; +; 6.075 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35~la_mlab/laboutt[9] ; +; 6.205 ; 0.130 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|datae ; +; 6.281 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1161: Setup slack is -0.675 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.279 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.675 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.281 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.823 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.279 ; 3.281 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.326 ; 0.437 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|dataf ; +; 5.355 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|combout ; +; 5.359 ; 0.004 ; RR ; CELL ; 16 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14~la_lab/laboutt[4] ; +; 6.252 ; 0.893 ; RR ; IC ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|dataf ; +; 6.279 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|combout ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|d ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y159_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1162: Setup slack is -0.675 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.675 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.746 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.421 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.497 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.501 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.221 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|dataf ; +; 6.248 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1163: Setup slack is -0.675 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[28] ; +; To Node ; vx_e_m_reg|alu_result[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.176 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.675 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.087 ; ; ; ; ; ; +; Data Delay ; 3.224 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.325 ; 79 ; 0.000 ; 2.325 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.551 ; 79 ; 0.120 ; 0.813 ; +; Cell ; ; 16 ; 0.492 ; 15 ; 0.000 ; 0.132 ; +; uTco ; ; 1 ; 0.181 ; 6 ; 0.181 ; 0.181 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.952 ; 2.952 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.952 ; 2.325 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; +; 2.952 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; +; 6.176 ; 3.224 ; ; ; ; ; ; data path ; +; 3.133 ; 0.181 ; FF ; uTco ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28]|q ; +; 3.177 ; 0.044 ; FF ; CELL ; 4 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]~la_lab/laboutb[14] ; +; 3.990 ; 0.813 ; FF ; IC ; 1 ; LABCELL_X73_Y151_N45 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~41|dataf ; +; 4.017 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X73_Y151_N45 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~41|combout ; +; 4.022 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X73_Y151_N45 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~41~la_lab/laboutb[11] ; +; 4.179 ; 0.157 ; RR ; IC ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43|datac ; +; 4.263 ; 0.084 ; RF ; CELL ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43|combout ; +; 4.269 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43~la_mlab/laboutt[12] ; +; 4.393 ; 0.124 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|datad ; +; 4.483 ; 0.090 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|combout ; +; 4.489 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46~la_mlab/laboutt[8] ; +; 4.609 ; 0.120 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|dataa ; +; 4.741 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.745 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.178 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.205 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.211 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.368 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; +; 5.396 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; +; 5.401 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; +; 6.148 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; +; 6.176 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; +; 6.176 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; +; 6.176 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1164: Setup slack is -0.675 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.276 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.675 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.749 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.408 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.276 ; 3.278 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.404 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.431 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.436 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.184 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.276 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1165: Setup slack is -0.675 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.675 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.847 ; 87 ; 0.104 ; 1.354 ; +; Cell ; ; 12 ; 0.303 ; 9 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.242 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; +; 6.270 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; +; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|d ; +; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1166: Setup slack is -0.675 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.675 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.837 ; 87 ; 0.114 ; 1.378 ; +; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.242 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.272 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1167: Setup slack is -0.675 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.675 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.724 ; 83 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.450 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.276 ; 0.347 ; FF ; IC ; 1 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|datad ; +; 5.355 ; 0.079 ; FR ; CELL ; 2 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|combout ; +; 5.359 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4~la_lab/laboutb[8] ; +; 6.206 ; 0.847 ; RR ; IC ; 1 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|datac ; +; 6.293 ; 0.087 ; RR ; CELL ; 2 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|combout ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]|d ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y148_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1168: Setup slack is -0.675 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.675 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.724 ; 83 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.450 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.276 ; 0.347 ; FF ; IC ; 1 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|datad ; +; 5.355 ; 0.079 ; FR ; CELL ; 2 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|combout ; +; 5.359 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4~la_lab/laboutb[8] ; +; 6.206 ; 0.847 ; RR ; IC ; 1 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|datac ; +; 6.293 ; 0.087 ; RR ; CELL ; 2 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|combout ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE|d ; +; 6.293 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y148_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1169: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.222 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.230 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.640 ; 82 ; 0.127 ; 0.734 ; +; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.222 ; 3.230 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; +; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.091 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.171 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.176 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.303 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.424 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.429 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.086 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.179 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.185 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.551 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.579 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.583 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.195 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.222 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1170: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.281 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.723 ; 83 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.431 ; 13 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.273 ; 3.281 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; +; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.070 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; +; 4.177 ; 0.107 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.183 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.298 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.324 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.329 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.092 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.170 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.176 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.884 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.912 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.918 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.198 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.273 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1171: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.596 ; 79 ; 0.118 ; 0.708 ; +; Cell ; ; 14 ; 0.558 ; 17 ; 0.000 ; 0.111 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; +; 3.935 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.939 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.078 ; 0.139 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.157 ; 0.079 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.162 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.280 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.391 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.396 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.079 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.170 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.176 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.884 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.912 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.918 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.198 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.273 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1172: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.865 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.366 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; +; 5.395 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; +; 5.399 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; +; 6.243 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; +; 6.272 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1173: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.277 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.048 ; ; ; ; ; ; +; Data Delay ; 3.279 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.813 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.277 ; 3.279 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.422 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.449 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.453 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.249 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; +; 6.277 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; +; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1174: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.777 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.374 ; 11 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.404 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.481 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.486 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; +; 6.243 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; +; 6.270 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1175: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.280 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.815 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.280 ; 3.282 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.447 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.474 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.480 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.253 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; +; 6.280 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; +; 6.280 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1176: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.257 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.849 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.257 ; 3.259 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.421 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.448 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.454 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.230 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; +; 6.257 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1177: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.267 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.833 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.315 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.267 ; 3.269 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.407 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.438 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.442 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.240 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; +; 6.267 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1178: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[5]~DUPLICATE ; +; To Node ; vx_e_m_reg|csr_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.001 ; ; ; ; ; ; +; Data Delay ; 3.309 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.336 ; 79 ; 0.000 ; 2.336 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.725 ; 82 ; 0.122 ; 0.789 ; +; Cell ; ; 14 ; 0.457 ; 14 ; 0.000 ; 0.118 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.963 ; 2.963 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.963 ; 2.336 ; RR ; IC ; 1 ; FF_X38_Y157_N43 ; High Speed ; vx_csr_handler|decode_csr_address[5]~DUPLICATE|clk ; +; 2.963 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N43 ; High Speed ; vx_csr_handler|decode_csr_address[5]~DUPLICATE ; +; 6.272 ; 3.309 ; ; ; ; ; ; data path ; +; 3.090 ; 0.127 ; RR ; uTco ; 1 ; FF_X38_Y157_N43 ; ; vx_csr_handler|decode_csr_address[5]~DUPLICATE|q ; +; 3.175 ; 0.085 ; RR ; CELL ; 230 ; FF_X38_Y157_N43 ; High Speed ; vx_csr_handler|decode_csr_address[5]~DUPLICATE~la_lab/laboutb[8] ; +; 3.964 ; 0.789 ; RR ; IC ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|dataa ; +; 4.082 ; 0.118 ; RF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|combout ; +; 4.086 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89~la_lab/laboutb[6] ; +; 4.347 ; 0.261 ; FF ; IC ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|dataf ; +; 4.375 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|combout ; +; 4.380 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105~la_lab/laboutt[15] ; +; 5.035 ; 0.655 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datac ; +; 5.121 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; +; 5.127 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; +; 5.250 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; +; 5.313 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.317 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.092 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.119 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.124 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.246 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; +; 6.272 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; +; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1179: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; +; To Node ; vx_e_m_reg|alu_result[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.177 ; +; Data Required Time ; 5.503 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.083 ; ; ; ; ; ; +; Data Delay ; 3.229 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.659 ; 82 ; 0.124 ; 0.816 ; +; Cell ; ; 14 ; 0.447 ; 14 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|clk ; +; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; +; 6.177 ; 3.229 ; ; ; ; ; ; data path ; +; 3.071 ; 0.123 ; FF ; uTco ; 1 ; FF_X79_Y153_N40 ; ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|q ; +; 3.115 ; 0.044 ; FF ; CELL ; 2 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE~la_lab/laboutb[6] ; +; 3.931 ; 0.816 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|dataf ; +; 3.958 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|combout ; +; 3.964 ; 0.006 ; FF ; CELL ; 70 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20~la_mlab/laboutt[7] ; +; 4.423 ; 0.459 ; FF ; IC ; 1 ; LABCELL_X68_Y152_N48 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~28|datac ; +; 4.509 ; 0.086 ; FF ; CELL ; 1 ; LABCELL_X68_Y152_N48 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~28|combout ; +; 4.513 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X68_Y152_N48 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~28~la_lab/laboutb[12] ; +; 4.741 ; 0.228 ; FF ; IC ; 1 ; MLABCELL_X69_Y151_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~49|datac ; +; 4.828 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X69_Y151_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~49|combout ; +; 4.834 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y151_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~49~la_mlab/laboutt[0] ; +; 4.958 ; 0.124 ; FF ; IC ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50|dataf ; +; 4.983 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50|combout ; +; 4.989 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50~la_mlab/laboutb[15] ; +; 5.205 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|datad ; +; 5.282 ; 0.077 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|combout ; +; 5.288 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52~la_mlab/laboutb[11] ; +; 6.104 ; 0.816 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|datad ; +; 6.177 ; 0.073 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|combout ; +; 6.177 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|d ; +; 6.177 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.503 ; 0.168 ; ; uTsu ; 1 ; FF_X46_Y153_N34 ; ; vx_e_m_reg|alu_result[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1180: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.747 ; 84 ; 0.120 ; 1.275 ; +; Cell ; ; 12 ; 0.405 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.152 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.272 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1181: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.262 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.041 ; ; ; ; ; ; +; Data Delay ; 3.264 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.699 ; 83 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.444 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.262 ; 3.264 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.470 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.547 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.552 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; +; 6.179 ; 0.627 ; RR ; IC ; 1 ; LABCELL_X97_Y165_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~582|datac ; +; 6.262 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X97_Y165_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~582|combout ; +; 6.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6]|d ; +; 6.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6]|clk ; +; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; +; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y165_N49 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1182: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_address[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.223 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.113 ; ; ; ; ; ; +; Data Delay ; 3.231 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.638 ; 82 ; 0.138 ; 0.916 ; +; Cell ; ; 12 ; 0.468 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.223 ; 3.231 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.280 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.196 ; 0.916 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; +; 6.223 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; +; 6.223 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; +; 6.223 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.200 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1183: Setup slack is -0.674 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.674 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.041 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.753 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.408 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.488 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.492 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.235 ; 0.743 ; RR ; IC ; 1 ; LABCELL_X97_Y165_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~838|dataf ; +; 6.263 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y165_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~838|combout ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6]|d ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6]|clk ; +; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; +; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.162 ; ; uTsu ; 1 ; FF_X97_Y165_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1184: Setup slack is -0.673 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.673 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.746 ; 84 ; 0.116 ; 0.788 ; +; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.889 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.915 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.921 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.199 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.272 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1185: Setup slack is -0.673 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.673 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.752 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.378 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.458 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.462 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.181 ; 0.719 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|datad ; +; 6.273 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|combout ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]|d ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y150_N38 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1186: Setup slack is -0.673 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.673 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.263 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.807 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.261 ; 3.263 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.366 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; +; 5.444 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; +; 5.448 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[10] ; +; 6.234 ; 0.786 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~636|dataf ; +; 6.261 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~636|combout ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28]|d ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1187: Setup slack is -0.673 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.673 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.759 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.393 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.470 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.474 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.242 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; +; 6.269 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1188: Setup slack is -0.673 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|csr_address[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.185 ; +; Data Required Time ; 5.512 ; +; Slack ; -0.673 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.121 ; ; ; ; ; ; +; Data Delay ; 3.187 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.706 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.361 ; 11 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.185 ; 3.187 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.329 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.112 ; 0.783 ; RR ; IC ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|datae ; +; 6.185 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|combout ; +; 6.185 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|d ; +; 6.185 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.377 ; 2.877 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; +; 5.377 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.347 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.512 ; 0.165 ; ; uTsu ; 1 ; FF_X49_Y149_N28 ; ; vx_d_e_reg|csr_address[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1189: Setup slack is -0.673 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.245 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.673 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.786 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 11 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.245 ; 3.247 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.320 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.400 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.404 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.218 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; +; 6.245 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1190: Setup slack is -0.673 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|a_reg_data[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.068 ; +; Data Required Time ; 5.395 ; +; Slack ; -0.673 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.070 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.628 ; 86 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.068 ; 3.070 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.068 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|sclr ; +; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N32 ; ; vx_d_e_reg|a_reg_data[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1191: Setup slack is -0.673 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|a_reg_data[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.068 ; +; Data Required Time ; 5.395 ; +; Slack ; -0.673 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.070 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.628 ; 86 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.068 ; 3.070 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.068 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|sclr ; +; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N38 ; ; vx_d_e_reg|a_reg_data[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1192: Setup slack is -0.673 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.673 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.847 ; 87 ; 0.104 ; 1.354 ; +; Cell ; ; 12 ; 0.303 ; 9 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.242 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; +; 6.270 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; +; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|d ; +; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1193: Setup slack is -0.673 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.673 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.856 ; 87 ; 0.104 ; 1.378 ; +; Cell ; ; 12 ; 0.295 ; 9 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.240 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.270 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1194: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.046 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.852 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.177 ; 79 ; 0.000 ; 2.177 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.635 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.663 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.669 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.231 ; 0.562 ; RR ; IC ; 1 ; LABCELL_X93_Y149_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~798|dataf ; +; 6.259 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y149_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~798|combout ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30]|d ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.452 ; 2.952 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.242 ; 2.177 ; RR ; IC ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30]|clk ; +; 5.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; +; 5.452 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.422 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y149_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1195: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.798 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.507 ; 0.006 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[3] ; +; 6.226 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|dataf ; +; 6.253 ; 0.027 ; RR ; CELL ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|combout ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|d ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y159_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1196: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.276 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.762 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.276 ; 3.278 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.473 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.190 ; 0.717 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|datac ; +; 6.276 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|combout ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|d ; +; 6.276 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X107_Y157_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1197: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.262 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.264 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.805 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.262 ; 3.264 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.296 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.323 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.329 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.234 ; 0.905 ; RR ; IC ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|dataf ; +; 6.262 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|combout ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|d ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.162 ; ; uTsu ; 1 ; FF_X109_Y154_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1198: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.048 ; ; ; ; ; ; +; Data Delay ; 3.277 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.832 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.324 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.275 ; 3.277 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.420 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.447 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.451 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.247 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; +; 6.275 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; +; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1199: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.278 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.280 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.834 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.278 ; 3.280 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.445 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.478 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.251 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; +; 6.278 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1200: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.861 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.292 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.420 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.447 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.453 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.243 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; +; 6.271 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1201: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.267 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.844 ; 87 ; 0.104 ; 1.351 ; +; Cell ; ; 12 ; 0.303 ; 9 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.267 ; 3.269 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.239 ; 1.351 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|dataf ; +; 6.267 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|combout ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|d ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1202: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.766 ; 85 ; 0.104 ; 1.275 ; +; Cell ; ; 12 ; 0.385 ; 12 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.150 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.270 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; +; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1203: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[24] ; +; To Node ; vx_d_e_reg|csr_address[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.177 ; +; Data Required Time ; 5.505 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.104 ; ; ; ; ; ; +; Data Delay ; 3.200 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.350 ; 79 ; 0.000 ; 2.350 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 4 ; 2.767 ; 86 ; 0.555 ; 0.986 ; +; Cell ; ; 10 ; 0.310 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.977 ; 2.977 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.977 ; 2.350 ; RR ; IC ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]|clk ; +; 2.977 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24] ; +; 6.177 ; 3.200 ; ; ; ; ; ; data path ; +; 3.100 ; 0.123 ; FF ; uTco ; 1 ; FF_X91_Y153_N23 ; ; vx_f_d_reg|instruction[24]|q ; +; 3.169 ; 0.069 ; FF ; CELL ; 138 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]~la_lab/laboutt[15] ; +; 3.724 ; 0.555 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|datac ; +; 3.817 ; 0.093 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; +; 3.823 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; +; 4.459 ; 0.636 ; RR ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; +; 4.486 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; +; 4.490 ; 0.004 ; FF ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; +; 5.476 ; 0.986 ; FF ; IC ; 1 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1|dataf ; +; 5.503 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1|combout ; +; 5.508 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X40_Y149_N3 ; High Speed ; vx_decode|out_csr_address[0]~1~la_lab/laboutt[3] ; +; 6.098 ; 0.590 ; FF ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datac ; +; 6.177 ; 0.079 ; FF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; +; 6.177 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; +; 6.177 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; +; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1204: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++---------------------------------------------+ +; Path Summary ; ++--------------------+------------------------+ +; Property ; Value ; ++--------------------+------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|csr_mask[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.632 ; 81 ; 0.192 ; 0.667 ; +; Cell ; ; 14 ; 0.509 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.573 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.599 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.605 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.232 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; +; 6.260 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1205: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++---------------------------------------------+ +; Path Summary ; ++--------------------+------------------------+ +; Property ; Value ; ++--------------------+------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|csr_mask[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.632 ; 81 ; 0.192 ; 0.667 ; +; Cell ; ; 14 ; 0.509 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.573 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.599 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.605 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.232 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; +; 6.260 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1206: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|b_reg_data[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.227 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.235 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.662 ; 82 ; 0.142 ; 0.944 ; +; Cell ; ; 12 ; 0.448 ; 14 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.227 ; 3.235 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.254 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.198 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; +; 6.227 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; +; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; +; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1207: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.621 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.833 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.543 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.265 ; 0.722 ; RR ; IC ; 1 ; MLABCELL_X107_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~996|dataf ; +; 6.293 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~996|combout ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y153_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE|d ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y153_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y153_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y153_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.621 ; 0.182 ; ; uTsu ; 1 ; FF_X107_Y153_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1208: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|b_reg_data[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.227 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.235 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.661 ; 82 ; 0.142 ; 0.943 ; +; Cell ; ; 12 ; 0.449 ; 14 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.227 ; 3.235 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.254 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.197 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; +; 6.227 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; +; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; +; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1209: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[25] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.305 ; +; Data Required Time ; 5.633 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.108 ; ; ; ; ; ; +; Data Delay ; 2.233 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.329 ; 76 ; 0.000 ; 2.329 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.911 ; 86 ; 0.336 ; 0.887 ; +; Cell ; ; 8 ; 0.189 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.072 ; 3.072 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.072 ; 2.329 ; FF ; IC ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|clk ; +; 4.072 ; 0.000 ; FR ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25] ; +; 6.305 ; 2.233 ; ; ; ; ; ; data path ; +; 4.205 ; 0.133 ; FF ; uTco ; 1 ; FF_X108_Y149_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]|q ; +; 4.249 ; 0.044 ; FF ; CELL ; 1 ; FF_X108_Y149_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[25]~la_lab/laboutb[6] ; +; 4.937 ; 0.688 ; FF ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|datae ; +; 5.021 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; +; 5.025 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; +; 5.912 ; 0.887 ; FF ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; +; 5.937 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; +; 5.942 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; +; 6.278 ; 0.336 ; FF ; IC ; 1 ; LABCELL_X75_Y157_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~20|dataf ; +; 6.305 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X75_Y157_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~20|combout ; +; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N17 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[25]|d ; +; 6.305 ; 0.000 ; FF ; CELL ; 1 ; FF_X75_Y157_N17 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[25] ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X75_Y157_N17 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[25]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y157_N17 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[25] ; +; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.633 ; 0.199 ; ; uTsu ; 1 ; FF_X75_Y157_N17 ; ; vx_fetch|VX_Warp_one|real_PC[25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1210: Setup slack is -0.672 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.293 ; +; Data Required Time ; 5.621 ; +; Slack ; -0.672 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.295 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.833 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.293 ; 3.295 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.543 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.265 ; 0.722 ; RR ; IC ; 1 ; MLABCELL_X107_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~996|dataf ; +; 6.293 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~996|combout ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y153_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]|d ; +; 6.293 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y153_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y153_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y153_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.621 ; 0.182 ; ; uTsu ; 1 ; FF_X107_Y153_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][4] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1211: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.799 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.352 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.178 ; 0.612 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|datac ; +; 6.271 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|combout ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|d ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1212: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.814 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.470 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.501 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.505 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.244 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|dataf ; +; 6.271 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|combout ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|d ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X102_Y161_N4 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1213: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.816 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.245 ; 0.687 ; RR ; IC ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|dataf ; +; 6.272 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y144_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1214: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.767 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.430 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.507 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.243 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|dataf ; +; 6.269 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|combout ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|d ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1215: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.262 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.264 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.853 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.291 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.262 ; 3.264 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.235 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; +; 6.262 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1216: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.249 ; +; Data Required Time ; 5.578 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.251 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.841 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.249 ; 3.251 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.610 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.222 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; +; 6.249 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; +; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; +; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1217: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.805 ; 86 ; 0.106 ; 1.302 ; +; Cell ; ; 12 ; 0.347 ; 11 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.153 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; +; 6.270 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; +; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; +; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1218: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|csr_mask[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.267 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.647 ; 81 ; 0.192 ; 0.682 ; +; Cell ; ; 14 ; 0.493 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.259 ; 3.267 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.572 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.598 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.604 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.231 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; +; 6.259 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1219: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|csr_mask[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.267 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.647 ; 81 ; 0.192 ; 0.682 ; +; Cell ; ; 14 ; 0.493 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.259 ; 3.267 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.572 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.598 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.604 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.231 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; +; 6.259 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1220: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.746 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.388 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.398 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; +; 5.476 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; +; 5.480 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[10] ; +; 6.226 ; 0.746 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~617|dataf ; +; 6.253 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~617|combout ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9]|d ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y160_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1221: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.751 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.184 ; 0.616 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1003|datac ; +; 6.271 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1003|combout ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11]|d ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1222: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.748 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.405 ; 12 ; 0.000 ; 0.094 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.599 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.178 ; 0.579 ; RR ; IC ; 1 ; MLABCELL_X94_Y145_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~536|datac ; +; 6.272 ; 0.094 ; RR ; CELL ; 1 ; MLABCELL_X94_Y145_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~536|combout ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y145_N59 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24]|d ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y145_N59 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X94_Y145_N59 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y145_N59 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X94_Y145_N59 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][24] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1223: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++-----------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------+ +; Property ; Value ; ++--------------------+--------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[1] ; +; To Node ; vx_e_m_reg|alu_result[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.134 ; +; Data Required Time ; 5.463 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+--------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.190 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.317 ; 79 ; 0.000 ; 2.317 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.540 ; 80 ; 0.187 ; 0.673 ; +; Cell ; ; 14 ; 0.467 ; 15 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.183 ; 6 ; 0.183 ; 0.183 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.170 ; 79 ; 0.000 ; 2.170 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.944 ; 2.944 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.944 ; 2.317 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; +; 2.944 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; +; 6.134 ; 3.190 ; ; ; ; ; ; data path ; +; 3.127 ; 0.183 ; FF ; uTco ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1]|q ; +; 3.195 ; 0.068 ; FF ; CELL ; 4 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]~la_lab/laboutt[4] ; +; 3.820 ; 0.625 ; FF ; IC ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|dataf ; +; 3.848 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|combout ; +; 3.852 ; 0.004 ; FF ; CELL ; 71 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22~la_lab/laboutb[2] ; +; 4.254 ; 0.402 ; FF ; IC ; 1 ; MLABCELL_X72_Y154_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~25|datac ; +; 4.341 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X72_Y154_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~25|combout ; +; 4.347 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X72_Y154_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~25~la_mlab/laboutb[17] ; +; 4.794 ; 0.447 ; FF ; IC ; 1 ; MLABCELL_X69_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~26|datac ; +; 4.881 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X69_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~26|combout ; +; 4.887 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~26~la_mlab/laboutt[8] ; +; 5.074 ; 0.187 ; FF ; IC ; 1 ; LABCELL_X68_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~27|dataf ; +; 5.100 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X68_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~27|combout ; +; 5.105 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~27~la_lab/laboutt[9] ; +; 5.311 ; 0.206 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~28|datae ; +; 5.373 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~28|combout ; +; 5.377 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N12 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~28~la_lab/laboutt[8] ; +; 6.050 ; 0.673 ; FF ; IC ; 1 ; MLABCELL_X45_Y153_N21 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~30|datae ; +; 6.134 ; 0.084 ; FF ; CELL ; 1 ; MLABCELL_X45_Y153_N21 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~30|combout ; +; 6.134 ; 0.000 ; FF ; CELL ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3]|d ; +; 6.134 ; 0.000 ; FF ; CELL ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.363 ; 2.863 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.235 ; 2.170 ; RR ; IC ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3]|clk ; +; 5.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3] ; +; 5.363 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.333 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.463 ; 0.130 ; ; uTsu ; 1 ; FF_X45_Y153_N22 ; ; vx_e_m_reg|alu_result[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1224: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.805 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.542 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; +; 6.237 ; 0.695 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~991|dataf ; +; 6.266 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~991|combout ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31]|d ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X98_Y143_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1225: Setup slack is -0.671 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.671 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.729 ; 83 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.423 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.493 ; 0.575 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.519 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.525 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; +; 6.179 ; 0.654 ; FF ; IC ; 1 ; MLABCELL_X107_Y152_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~964|datac ; +; 6.271 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X107_Y152_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~964|combout ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4]|d ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1226: Setup slack is -0.670 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[3] ; +; To Node ; vx_e_m_reg|csr_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.286 ; +; Data Required Time ; 5.616 ; +; Slack ; -0.670 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.009 ; ; ; ; ; ; +; Data Delay ; 3.297 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.769 ; 84 ; 0.122 ; 0.775 ; +; Cell ; ; 16 ; 0.407 ; 12 ; 0.000 ; 0.081 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]|clk ; +; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3] ; +; 6.286 ; 3.297 ; ; ; ; ; ; data path ; +; 3.110 ; 0.121 ; RR ; uTco ; 1 ; FF_X51_Y153_N38 ; ; vx_csr_handler|decode_csr_address[3]|q ; +; 3.173 ; 0.063 ; RR ; CELL ; 686 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]~la_lab/laboutb[5] ; +; 3.863 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|dataf ; +; 3.891 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|combout ; +; 3.897 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145~la_mlab/laboutb[9] ; +; 4.338 ; 0.441 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|datac ; +; 4.419 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; +; 4.424 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; +; 4.779 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; +; 4.807 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; +; 4.813 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; +; 5.076 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; +; 5.135 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; +; 5.141 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; +; 5.264 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; +; 5.327 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.331 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.106 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.133 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.138 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.260 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; +; 6.286 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; +; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; +; 6.286 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; +; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; +; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.616 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1227: Setup slack is -0.670 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.279 ; +; Data Required Time ; 5.609 ; +; Slack ; -0.670 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.281 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.762 ; 84 ; 0.108 ; 0.787 ; +; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.279 ; 3.281 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.040 ; 0.769 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; +; 6.069 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; +; 6.075 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; +; 6.203 ; 0.128 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; +; 6.279 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1228: Setup slack is -0.670 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|a_reg_data[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.111 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.670 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.113 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.671 ; 86 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.111 ; 3.113 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.111 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|sclr ; +; 6.111 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1229: Setup slack is -0.670 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|a_reg_data[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.111 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.670 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.113 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.671 ; 86 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.111 ; 3.113 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.111 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|sclr ; +; 6.111 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N40 ; ; vx_d_e_reg|a_reg_data[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1230: Setup slack is -0.670 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|a_reg_data[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.111 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.670 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.113 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.671 ; 86 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.111 ; 3.113 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.111 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|sclr ; +; 6.111 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N43 ; ; vx_d_e_reg|a_reg_data[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1231: Setup slack is -0.670 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.285 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.670 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.287 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.759 ; 84 ; 0.114 ; 1.300 ; +; Cell ; ; 12 ; 0.406 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.285 ; 3.287 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.164 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.285 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; +; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1232: Setup slack is -0.670 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.670 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.747 ; 84 ; 0.120 ; 1.275 ; +; Cell ; ; 12 ; 0.402 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.152 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; +; 6.269 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1233: Setup slack is -0.670 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.285 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.670 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.287 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.759 ; 84 ; 0.114 ; 1.300 ; +; Cell ; ; 12 ; 0.406 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.285 ; 3.287 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.164 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.285 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; +; 6.285 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1234: Setup slack is -0.670 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.670 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.831 ; 87 ; 0.114 ; 1.372 ; +; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.236 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; +; 6.266 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1235: Setup slack is -0.670 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.670 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.779 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.362 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.501 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.530 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.535 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.231 ; 0.696 ; FF ; IC ; 1 ; LABCELL_X93_Y147_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~664|dataf ; +; 6.260 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X93_Y147_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~664|combout ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24]|d ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1236: Setup slack is -0.670 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|b_reg_data[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.224 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.670 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.232 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.658 ; 82 ; 0.142 ; 0.940 ; +; Cell ; ; 12 ; 0.449 ; 14 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.224 ; 3.232 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.254 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.194 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; +; 6.224 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; +; 6.224 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; +; 6.224 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1237: Setup slack is -0.670 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.288 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.670 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.290 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.811 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.288 ; 3.290 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.494 ; 0.006 ; FF ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.261 ; 0.767 ; FF ; IC ; 1 ; MLABCELL_X105_Y151_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~921|dataf ; +; 6.288 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X105_Y151_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~921|combout ; +; 6.288 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y151_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25]|d ; +; 6.288 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y151_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y151_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y151_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X105_Y151_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1238: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.279 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.281 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.762 ; 84 ; 0.108 ; 0.787 ; +; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.279 ; 3.281 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.271 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.030 ; 0.759 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; +; 6.057 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; +; 6.063 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; +; 6.201 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; +; 6.279 ; 0.078 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1239: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.130 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.132 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.130 ; 3.132 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|sload ; +; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N4 ; ; vx_fetch|VX_Warp_zero|real_PC[14] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1240: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.130 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.132 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.130 ; 3.132 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|sload ; +; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N10 ; ; vx_fetch|VX_Warp_zero|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1241: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.801 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.469 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.496 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.501 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.229 ; 0.728 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|dataf ; +; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|combout ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|d ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1242: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.812 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.331 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.429 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.505 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.509 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.237 ; 0.728 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~831|dataf ; +; 6.263 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~831|combout ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31]|d ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1243: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.848 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.477 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.509 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.513 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.229 ; 0.716 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~796|dataf ; +; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~796|combout ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28]|d ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N38 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1244: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.262 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.264 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.856 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.262 ; 3.264 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.535 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.562 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.568 ; 0.006 ; RR ; CELL ; 6 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[11] ; +; 6.234 ; 0.666 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~540|dataf ; +; 6.262 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~540|combout ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28]|d ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1245: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.803 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.503 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.232 ; 0.729 ; RR ; IC ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|dataf ; +; 6.260 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y161_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1246: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.806 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.506 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.233 ; 0.727 ; RR ; IC ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|dataf ; +; 6.260 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y162_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1247: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.758 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.397 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.473 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.477 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.243 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; +; 6.270 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1248: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.750 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.300 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; +; 5.330 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; +; 5.334 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; +; 6.187 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; +; 6.273 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1249: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.250 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.252 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.785 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.250 ; 3.252 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.417 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.444 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.449 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.223 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; +; 6.250 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1250: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.812 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.352 ; 11 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.420 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.451 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.455 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.195 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; +; 6.282 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1251: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.801 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.082 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.424 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.451 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.456 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.181 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; +; 6.263 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1252: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.830 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.416 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.443 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.449 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.225 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; +; 6.252 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1253: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|b_reg_data[28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.223 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.225 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.756 ; 85 ; 0.108 ; 0.888 ; +; Cell ; ; 12 ; 0.347 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.223 ; 3.225 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.196 ; 0.888 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|dataf ; +; 6.223 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N51 ; High Speed ; vx_d_e_reg|i385~87|combout ; +; 6.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|d ; +; 6.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1254: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[5]~DUPLICATE ; +; To Node ; vx_e_m_reg|alu_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.001 ; ; ; ; ; ; +; Data Delay ; 3.301 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.336 ; 79 ; 0.000 ; 2.336 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.717 ; 82 ; 0.114 ; 0.789 ; +; Cell ; ; 14 ; 0.457 ; 14 ; 0.000 ; 0.118 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.963 ; 2.963 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.963 ; 2.336 ; RR ; IC ; 1 ; FF_X38_Y157_N43 ; High Speed ; vx_csr_handler|decode_csr_address[5]~DUPLICATE|clk ; +; 2.963 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N43 ; High Speed ; vx_csr_handler|decode_csr_address[5]~DUPLICATE ; +; 6.264 ; 3.301 ; ; ; ; ; ; data path ; +; 3.090 ; 0.127 ; RR ; uTco ; 1 ; FF_X38_Y157_N43 ; ; vx_csr_handler|decode_csr_address[5]~DUPLICATE|q ; +; 3.175 ; 0.085 ; RR ; CELL ; 230 ; FF_X38_Y157_N43 ; High Speed ; vx_csr_handler|decode_csr_address[5]~DUPLICATE~la_lab/laboutb[8] ; +; 3.964 ; 0.789 ; RR ; IC ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|dataa ; +; 4.082 ; 0.118 ; RF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89|combout ; +; 4.086 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X58_Y163_N39 ; High Speed ; vx_csr_handler|Mux_3~89~la_lab/laboutb[6] ; +; 4.347 ; 0.261 ; FF ; IC ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|dataf ; +; 4.375 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105|combout ; +; 4.380 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X58_Y159_N21 ; High Speed ; vx_csr_handler|Mux_3~105~la_lab/laboutt[15] ; +; 5.035 ; 0.655 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datac ; +; 5.121 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; +; 5.127 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; +; 5.250 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; +; 5.313 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.317 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.092 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.119 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.124 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.238 ; 0.114 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; +; 6.264 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; +; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.163 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1255: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.217 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.225 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.659 ; 82 ; 0.133 ; 0.657 ; +; Cell ; ; 14 ; 0.439 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.217 ; 3.225 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.722 ; 0.540 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|dataf ; +; 3.750 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.754 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.887 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.970 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.975 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.326 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.419 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.424 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.081 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.174 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.180 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.546 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.574 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.578 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.190 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.217 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.217 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.217 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1256: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.894 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.795 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.534 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.562 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.568 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.257 ; 0.689 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|dataf ; +; 6.283 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y151_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~772|combout ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|d ; +; 6.283 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1257: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|a_reg_data[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.111 ; +; Data Required Time ; 5.442 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.113 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.671 ; 86 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.320 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.111 ; 3.113 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.111 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|sclr ; +; 6.111 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.442 ; 0.054 ; ; uTsu ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1258: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_f_d_reg|curr_PC[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.137 ; +; Data Required Time ; 5.468 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.028 ; ; ; ; ; ; +; Data Delay ; 3.139 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.715 ; 86 ; 0.119 ; 1.282 ; +; Cell ; ; 10 ; 0.302 ; 10 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.137 ; 3.139 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.488 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.822 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.850 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.855 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.137 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|ena ; +; 6.137 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N44 ; High Speed ; vx_f_d_reg|curr_PC[0] ; +; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N44 ; ; vx_f_d_reg|curr_PC[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1259: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_f_d_reg|curr_PC[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.137 ; +; Data Required Time ; 5.468 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.028 ; ; ; ; ; ; +; Data Delay ; 3.139 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.715 ; 86 ; 0.119 ; 1.282 ; +; Cell ; ; 10 ; 0.302 ; 10 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.137 ; 3.139 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.488 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.822 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.850 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.855 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.137 ; 1.282 ; FF ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|ena ; +; 6.137 ; 0.000 ; FF ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X68_Y156_N25 ; High Speed ; vx_f_d_reg|curr_PC[1] ; +; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.468 ; 0.028 ; ; uTsu ; 1 ; FF_X68_Y156_N25 ; ; vx_f_d_reg|curr_PC[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1260: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.687 ; 82 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.475 ; 14 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.252 ; 0.326 ; RR ; IC ; 1 ; LABCELL_X93_Y153_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~19|datac ; +; 5.331 ; 0.079 ; RF ; CELL ; 2 ; LABCELL_X93_Y153_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~19|combout ; +; 5.336 ; 0.005 ; FF ; CELL ; 9 ; LABCELL_X93_Y153_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~19~la_lab/laboutb[17] ; +; 6.189 ; 0.853 ; FF ; IC ; 1 ; MLABCELL_X101_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~610|datad ; +; 6.281 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X101_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~610|combout ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2]|d ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.175 ; ; uTsu ; 1 ; FF_X101_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][2] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1261: Setup slack is -0.669 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.669 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.753 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.563 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; +; 6.188 ; 0.625 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~590|datad ; +; 6.268 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X102_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~590|combout ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14]|d ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1262: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-----------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------+ +; Property ; Value ; ++--------------------+--------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[4] ; +; To Node ; vx_e_m_reg|alu_result[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.169 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+--------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.083 ; ; ; ; ; ; +; Data Delay ; 3.221 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.584 ; 80 ; 0.125 ; 0.747 ; +; Cell ; ; 16 ; 0.515 ; 16 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N43 ; High Speed ; vx_d_e_reg|b_reg_data[4]|clk ; +; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N43 ; High Speed ; vx_d_e_reg|b_reg_data[4] ; +; 6.169 ; 3.221 ; ; ; ; ; ; data path ; +; 3.070 ; 0.122 ; FF ; uTco ; 1 ; FF_X79_Y153_N43 ; ; vx_d_e_reg|b_reg_data[4]|q ; +; 3.138 ; 0.068 ; FF ; CELL ; 4 ; FF_X79_Y153_N43 ; High Speed ; vx_d_e_reg|b_reg_data[4]~la_lab/laboutb[8] ; +; 3.884 ; 0.746 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~18|dataf ; +; 3.911 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~18|combout ; +; 3.915 ; 0.004 ; FF ; CELL ; 42 ; LABCELL_X73_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~18~la_lab/laboutb[2] ; +; 4.074 ; 0.159 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~29|datab ; +; 4.183 ; 0.109 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~29|combout ; +; 4.187 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X73_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~29~la_lab/laboutt[16] ; +; 4.312 ; 0.125 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datab ; +; 4.438 ; 0.126 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; +; 4.442 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; +; 4.659 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; +; 4.734 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.738 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.171 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.198 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.204 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.361 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; +; 5.389 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; +; 5.394 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; +; 6.141 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; +; 6.169 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; +; 6.169 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; +; 6.169 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1263: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.130 ; +; Data Required Time ; 5.462 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.132 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.130 ; 3.132 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|sload ; +; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N5 ; ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1264: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.130 ; +; Data Required Time ; 5.462 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.132 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.130 ; 3.132 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|sload ; +; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N14 ; ; vx_fetch|VX_Warp_zero|real_PC[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1265: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.274 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.506 ; 76 ; 0.118 ; 0.755 ; +; Cell ; ; 14 ; 0.650 ; 20 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.274 ; 3.282 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.239 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 5.994 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.021 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.027 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.198 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.274 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1266: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.752 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.378 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.458 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.462 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.181 ; 0.719 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|datad ; +; 6.273 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|combout ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE|d ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y150_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1267: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.865 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.366 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; +; 5.395 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; +; 5.399 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; +; 6.243 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; +; 6.272 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1268: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.262 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.264 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.856 ; 88 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.262 ; 3.264 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.511 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.235 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1020|dataf ; +; 6.262 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1020|combout ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28]|d ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y144_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1269: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.799 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.470 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.501 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.505 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.229 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|dataf ; +; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|combout ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|d ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1270: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.279 ; +; Data Required Time ; 5.611 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.281 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.723 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.436 ; 13 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.279 ; 3.281 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.430 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.507 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.199 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|datac ; +; 6.279 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|combout ; +; 6.279 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|d ; +; 6.279 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1271: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.267 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.812 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.267 ; 3.269 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.469 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.496 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.501 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.240 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|dataf ; +; 6.267 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|combout ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|d ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X108_Y157_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1272: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.250 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.252 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.781 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.349 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.250 ; 3.252 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.462 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.494 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.499 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; +; 6.223 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; +; 6.250 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1273: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.795 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.450 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.477 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.482 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.232 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; +; 6.259 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1274: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.746 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.456 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.485 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.490 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.186 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; +; 6.273 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1275: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.258 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.849 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.291 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.258 ; 3.260 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.231 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; +; 6.258 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1276: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.240 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.242 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.767 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.353 ; 11 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.240 ; 3.242 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.315 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.395 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.399 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.213 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; +; 6.240 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1277: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.267 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.768 ; 85 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.381 ; 12 ; 0.000 ; 0.134 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.267 ; 3.269 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.377 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.408 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.413 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.133 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|datab ; +; 6.267 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~922|combout ; +; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|d ; +; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1278: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.799 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.353 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.380 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.384 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.159 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|datad ; +; 6.252 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~559|combout ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|d ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y165_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1279: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.747 ; 84 ; 0.120 ; 1.275 ; +; Cell ; ; 12 ; 0.405 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.152 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.272 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1280: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.778 ; 85 ; 0.104 ; 1.300 ; +; Cell ; ; 12 ; 0.386 ; 12 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.162 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.283 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1281: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.267 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.766 ; 85 ; 0.104 ; 1.275 ; +; Cell ; ; 12 ; 0.382 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.267 ; 3.269 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.150 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; +; 6.267 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; +; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; +; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1282: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.778 ; 85 ; 0.104 ; 1.300 ; +; Cell ; ; 12 ; 0.386 ; 12 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.162 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.283 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1283: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.850 ; 87 ; 0.104 ; 1.372 ; +; Cell ; ; 12 ; 0.295 ; 9 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.234 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; +; 6.264 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1284: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_csr_handler|decode_csr_address[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.166 ; +; Data Required Time ; 5.498 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.141 ; ; ; ; ; ; +; Data Delay ; 3.174 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 4 ; 2.836 ; 89 ; 0.630 ; 0.817 ; +; Cell ; ; 8 ; 0.211 ; 7 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.158 ; 79 ; 0.000 ; 2.158 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.166 ; 3.174 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.810 ; 0.630 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|datad ; +; 3.890 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0|combout ; +; 3.896 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N39 ; High Speed ; vx_forwarding|reduce_or_6~0~la_mlab/laboutb[7] ; +; 4.573 ; 0.677 ; FF ; IC ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|dataf ; +; 4.600 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853|combout ; +; 4.604 ; 0.004 ; RR ; CELL ; 12 ; LABCELL_X77_Y153_N39 ; High Speed ; vx_decode|i853~la_lab/laboutb[6] ; +; 5.316 ; 0.712 ; RR ; IC ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|dataf ; +; 5.344 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4|combout ; +; 5.349 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X53_Y152_N57 ; High Speed ; vx_decode|out_csr_address[0]~4~la_lab/laboutb[19] ; +; 6.166 ; 0.817 ; FF ; IC ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4]|d ; +; 6.166 ; 0.000 ; FF ; CELL ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.351 ; 2.851 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.223 ; 2.158 ; RR ; IC ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4]|clk ; +; 5.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X38_Y157_N17 ; High Speed ; vx_csr_handler|decode_csr_address[4] ; +; 5.351 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.321 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.498 ; 0.177 ; ; uTsu ; 1 ; FF_X38_Y157_N17 ; ; vx_csr_handler|decode_csr_address[4] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1285: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.046 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.749 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.177 ; 79 ; 0.000 ; 2.177 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.568 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.594 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.179 ; 0.579 ; RR ; IC ; 1 ; MLABCELL_X94_Y160_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~877|datad ; +; 6.266 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X94_Y160_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~877|combout ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y160_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13]|d ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y160_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.452 ; 2.952 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.242 ; 2.177 ; RR ; IC ; 1 ; FF_X94_Y160_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13]|clk ; +; 5.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y160_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13] ; +; 5.452 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.422 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.176 ; ; uTsu ; 1 ; FF_X94_Y160_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1286: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.290 ; +; Data Required Time ; 5.622 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.027 ; ; ; ; ; ; +; Data Delay ; 3.292 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.811 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.360 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.290 ; 3.292 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.261 ; 0.738 ; FF ; IC ; 1 ; MLABCELL_X107_Y149_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~761|dataf ; +; 6.290 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X107_Y149_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~761|combout ; +; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25]|d ; +; 6.290 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25] ; +; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.622 ; 0.181 ; ; uTsu ; 1 ; FF_X107_Y149_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1287: Setup slack is -0.668 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[22] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.297 ; +; Data Required Time ; 5.629 ; +; Slack ; -0.668 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.101 ; ; ; ; ; ; +; Data Delay ; 2.237 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.317 ; 76 ; 0.000 ; 2.317 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.849 ; 83 ; 0.403 ; 0.782 ; +; Cell ; ; 8 ; 0.226 ; 10 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.162 ; 7 ; 0.162 ; 0.162 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.060 ; 3.060 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.060 ; 2.317 ; FF ; IC ; 1 ; FF_X92_Y142_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[22]|clk ; +; 4.060 ; 0.000 ; FR ; CELL ; 1 ; FF_X92_Y142_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[22] ; +; 6.297 ; 2.237 ; ; ; ; ; ; data path ; +; 4.222 ; 0.162 ; FF ; uTco ; 1 ; FF_X92_Y142_N38 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[22]|q ; +; 4.265 ; 0.043 ; FF ; CELL ; 1 ; FF_X92_Y142_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[22]~la_mlab/laboutb[5] ; +; 5.047 ; 0.782 ; FF ; IC ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|datac ; +; 5.132 ; 0.085 ; FF ; CELL ; 1 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49|combout ; +; 5.138 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X80_Y150_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~49~la_mlab/laboutt[13] ; +; 5.802 ; 0.664 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|dataf ; +; 5.830 ; 0.028 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50|combout ; +; 5.835 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X76_Y150_N48 ; High Speed ; vx_decode|out_a_reg_data[0]~50~la_mlab/laboutb[12] ; +; 6.238 ; 0.403 ; FF ; IC ; 1 ; MLABCELL_X76_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~19|datae ; +; 6.297 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X76_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~19|combout ; +; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22]|d ; +; 6.297 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22] ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22]|clk ; +; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X76_Y158_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[22] ; +; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X76_Y158_N14 ; ; vx_fetch|VX_Warp_three|real_PC[22] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1288: Setup slack is -0.667 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.667 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.654 ; 81 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.493 ; 15 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; +; 4.064 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; +; 4.170 ; 0.106 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.176 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.291 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.317 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.322 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.085 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.163 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.169 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.905 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.911 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.191 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.266 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1289: Setup slack is -0.667 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.667 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.664 ; 82 ; 0.110 ; 0.788 ; +; Cell ; ; 14 ; 0.471 ; 14 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.516 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.542 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.548 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.147 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.254 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1290: Setup slack is -0.667 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.667 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.740 ; 84 ; 0.116 ; 0.788 ; +; Cell ; ; 14 ; 0.410 ; 13 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.898 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.927 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.933 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.196 ; 0.263 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.269 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1291: Setup slack is -0.667 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.667 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.866 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.536 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.562 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.568 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.243 ; 0.675 ; RR ; IC ; 1 ; LABCELL_X108_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~868|dataf ; +; 6.271 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X108_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~868|combout ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4]|d ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1292: Setup slack is -0.667 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.667 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.777 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.372 ; 11 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.395 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.471 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.475 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.241 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; +; 6.268 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1293: Setup slack is -0.667 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.667 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.804 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.415 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.447 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.221 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; +; 6.248 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1294: Setup slack is -0.667 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|b_reg_data[16] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.218 ; +; Data Required Time ; 5.551 ; +; Slack ; -0.667 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.078 ; ; ; ; ; ; +; Data Delay ; 3.220 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.631 ; 82 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.468 ; 15 ; 0.000 ; 0.128 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.218 ; 3.220 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.090 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|datab ; +; 6.218 ; 0.128 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|combout ; +; 6.218 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|d ; +; 6.218 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|clk ; +; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; +; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.551 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y152_N32 ; ; vx_d_e_reg|b_reg_data[16] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1295: Setup slack is -0.667 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.667 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.842 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.304 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.834 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.415 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.448 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.238 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; +; 6.266 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1296: Setup slack is -0.667 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.667 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.808 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.765 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.790 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.796 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.230 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; +; 5.259 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; +; 5.263 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; +; 6.171 ; 0.908 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|datad ; +; 6.263 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1297: Setup slack is -0.667 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.667 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.759 ; 84 ; 0.114 ; 1.300 ; +; Cell ; ; 12 ; 0.403 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.164 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|datab ; +; 6.282 ; 0.118 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1298: Setup slack is -0.667 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.667 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.617 ; 80 ; 0.150 ; 0.746 ; +; Cell ; ; 14 ; 0.537 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.034 ; 0.746 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.060 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.066 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.216 ; 0.150 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.273 ; 0.057 ; FF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1299: Setup slack is -0.667 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.250 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.667 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.252 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.793 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.250 ; 3.252 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.568 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.594 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.223 ; 0.623 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~873|dataf ; +; 6.250 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~873|combout ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9]|d ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1300: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.276 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.648 ; 81 ; 0.118 ; 0.734 ; +; Cell ; ; 14 ; 0.501 ; 15 ; 0.000 ; 0.111 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.268 ; 3.276 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; +; 3.942 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.946 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.085 ; 0.139 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.164 ; 0.079 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.169 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.287 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.398 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.403 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.086 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.177 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.183 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.897 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.927 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.933 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.193 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.268 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1301: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.265 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.669 ; 82 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.477 ; 15 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.265 ; 3.273 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.942 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; +; 4.063 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; +; 4.169 ; 0.106 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.175 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.290 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.316 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.321 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.084 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.162 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.168 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.876 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.904 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.910 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.190 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.265 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1302: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.664 ; 82 ; 0.110 ; 0.788 ; +; Cell ; ; 14 ; 0.470 ; 14 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.184 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.210 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.215 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.334 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.407 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.411 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.199 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.226 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.232 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.516 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.542 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.548 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.147 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.253 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1303: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.130 ; +; Data Required Time ; 5.464 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.132 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.130 ; 3.132 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|sload ; +; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[20] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1304: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.130 ; +; Data Required Time ; 5.464 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.132 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.130 ; 3.132 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|sload ; +; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N44 ; ; vx_fetch|VX_Warp_zero|real_PC[17] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1305: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[16] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.130 ; +; Data Required Time ; 5.464 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.132 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.638 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.130 ; 3.132 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.788 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.815 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.821 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.130 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|sload ; +; 6.130 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N32 ; ; vx_fetch|VX_Warp_zero|real_PC[16] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1306: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.274 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.506 ; 76 ; 0.118 ; 0.755 ; +; Cell ; ; 14 ; 0.650 ; 20 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.274 ; 3.282 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.239 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 5.994 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.021 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.027 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.198 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.274 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1307: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.845 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.494 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.526 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.530 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; +; 6.226 ; 0.696 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~604|dataf ; +; 6.253 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~604|combout ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28]|d ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1308: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.861 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.488 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.517 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.522 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.241 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X104_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~718|dataf ; +; 6.268 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~718|combout ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14]|d ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.166 ; ; uTsu ; 1 ; FF_X104_Y160_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1309: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.829 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.332 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.438 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.515 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.519 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.255 ; 0.736 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|dataf ; +; 6.281 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1310: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.807 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.358 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; +; 5.387 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; +; 5.391 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; +; 6.235 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; +; 6.264 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1311: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.276 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.809 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.276 ; 3.278 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.417 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.444 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.450 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.248 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|dataf ; +; 6.276 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|combout ; +; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|d ; +; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.164 ; ; uTsu ; 1 ; FF_X104_Y146_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1312: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.277 ; +; Data Required Time ; 5.611 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.279 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.809 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.348 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.277 ; 3.279 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.444 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.479 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.249 ; 0.770 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|dataf ; +; 6.277 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|combout ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|d ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1313: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.740 ; 84 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.534 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.179 ; 0.645 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|datad ; +; 6.266 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1314: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.797 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.456 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.485 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.490 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.237 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|dataf ; +; 6.264 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|combout ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|d ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1315: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.794 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.637 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.233 ; 0.596 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|dataf ; +; 6.260 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1316: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.800 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.329 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.460 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.492 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.497 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; +; 6.221 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; +; 6.248 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1317: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.257 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.814 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.324 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.257 ; 3.259 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.448 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.475 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.480 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.230 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; +; 6.257 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1318: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.765 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.454 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.483 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.488 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.184 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; +; 6.271 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1319: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.839 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.421 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.448 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.454 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.220 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; +; 6.247 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1320: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.257 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.834 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.303 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.257 ; 3.259 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.230 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; +; 6.257 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1321: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.578 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.822 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.605 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.217 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; +; 6.244 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; +; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; +; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1322: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.263 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.745 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.261 ; 3.263 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.442 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.471 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.476 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.182 ; 0.706 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; +; 6.261 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1323: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.862 ; 88 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.478 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.504 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.510 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.242 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; +; 6.268 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1324: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.877 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.431 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.459 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.464 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.239 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.266 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|d ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X107_Y152_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1325: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++---------------------------------------------+ +; Path Summary ; ++--------------------+------------------------+ +; Property ; Value ; ++--------------------+------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.136 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.138 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.604 ; 83 ; 0.163 ; 1.398 ; +; Cell ; ; 10 ; 0.412 ; 13 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.136 ; 3.138 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; +; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 4.653 ; 0.163 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|datac ; +; 4.733 ; 0.080 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.738 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.136 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.136 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1326: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.058 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.060 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.671 ; 87 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.058 ; 3.060 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.058 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|sclr ; +; 6.058 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N25 ; High Speed ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N25 ; ; vx_d_e_reg|a_reg_data[1]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1327: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|a_reg_data[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.058 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.060 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.671 ; 87 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.058 ; 3.060 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.058 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|sclr ; +; 6.058 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N26 ; High Speed ; vx_d_e_reg|a_reg_data[1] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N26 ; ; vx_d_e_reg|a_reg_data[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1328: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|a_reg_data[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.058 ; +; Data Required Time ; 5.392 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.060 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.671 ; 87 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.058 ; 3.060 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.058 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|sclr ; +; 6.058 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N16 ; High Speed ; vx_d_e_reg|a_reg_data[11] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.392 ; 0.013 ; ; uTsu ; 1 ; FF_X79_Y154_N16 ; ; vx_d_e_reg|a_reg_data[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1329: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.766 ; 85 ; 0.104 ; 1.275 ; +; Cell ; ; 12 ; 0.385 ; 12 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.150 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.270 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; +; 6.270 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1330: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.805 ; 86 ; 0.106 ; 1.302 ; +; Cell ; ; 12 ; 0.349 ; 11 ; 0.000 ; 0.119 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.153 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; +; 6.272 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1331: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.265 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.267 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.786 ; 85 ; 0.104 ; 1.302 ; +; Cell ; ; 12 ; 0.359 ; 11 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.265 ; 3.267 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.148 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; +; 6.265 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; +; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; +; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1332: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|PC_next_out[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.068 ; +; Data Required Time ; 5.402 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.073 ; ; ; ; ; ; +; Data Delay ; 3.076 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.409 ; 78 ; 0.118 ; 0.829 ; +; Cell ; ; 10 ; 0.541 ; 18 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.068 ; 3.076 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.239 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.068 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; +; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; +; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.402 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1333: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.280 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.632 ; 80 ; 0.150 ; 0.746 ; +; Cell ; ; 14 ; 0.521 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.272 ; 3.280 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.287 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.033 ; 0.746 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.059 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.065 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.215 ; 0.150 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.272 ; 0.057 ; FF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1334: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.735 ; 84 ; 0.106 ; 1.205 ; +; Cell ; ; 12 ; 0.398 ; 12 ; 0.000 ; 0.119 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.133 ; 1.205 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~111|datab ; +; 6.252 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~111|combout ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15]|d ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N38 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[3][15] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1335: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.249 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.251 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.788 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.249 ; 3.251 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.221 ; 0.653 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1007|dataf ; +; 6.249 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1007|combout ; +; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15]|d ; +; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X94_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1336: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.810 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.568 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.594 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.599 ; 0.005 ; RR ; CELL ; 12 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[10] ; +; 6.239 ; 0.640 ; RR ; IC ; 1 ; LABCELL_X95_Y145_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~888|dataf ; +; 6.266 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y145_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~888|combout ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24]|d ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y145_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][24] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1337: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.811 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.514 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.541 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.547 ; 0.006 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[3] ; +; 6.242 ; 0.695 ; RR ; IC ; 1 ; LABCELL_X108_Y152_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~836|dataf ; +; 6.270 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X108_Y152_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~836|combout ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4]|d ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X108_Y152_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y152_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y152_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1338: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.807 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; +; 6.241 ; 0.679 ; RR ; IC ; 1 ; LABCELL_X108_Y152_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~580|dataf ; +; 6.268 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X108_Y152_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~580|combout ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4]|d ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X108_Y152_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y152_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X108_Y152_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1339: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|warp_num[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.219 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.221 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.657 ; 82 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.443 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.219 ; 3.221 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.126 ; 0.711 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N9 ; High Speed ; vx_d_e_reg|i602~2|datac ; +; 6.219 ; 0.093 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N9 ; High Speed ; vx_d_e_reg|i602~2|combout ; +; 6.219 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N10 ; High Speed ; vx_d_e_reg|warp_num[2]|d ; +; 6.219 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N10 ; High Speed ; vx_d_e_reg|warp_num[2] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X80_Y153_N10 ; High Speed ; vx_d_e_reg|warp_num[2]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N10 ; High Speed ; vx_d_e_reg|warp_num[2] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.165 ; ; uTsu ; 1 ; FF_X80_Y153_N10 ; ; vx_d_e_reg|warp_num[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1340: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.033 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.790 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.357 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.493 ; 0.005 ; FF ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.239 ; 0.746 ; FF ; IC ; 1 ; MLABCELL_X105_Y157_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~907|dataf ; +; 6.266 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X105_Y157_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~907|combout ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y157_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11]|d ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y157_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X105_Y157_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11]|clk ; +; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y157_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11] ; +; 5.465 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.165 ; ; uTsu ; 1 ; FF_X105_Y157_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1341: Setup slack is -0.666 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.666 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.356 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.493 ; 0.005 ; FF ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.240 ; 0.747 ; FF ; IC ; 1 ; MLABCELL_X107_Y157_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~906|dataf ; +; 6.266 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X107_Y157_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~906|combout ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10]|d ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y157_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1342: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[3] ; +; To Node ; vx_e_m_reg|alu_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.278 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.009 ; ; ; ; ; ; +; Data Delay ; 3.289 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.761 ; 84 ; 0.114 ; 0.775 ; +; Cell ; ; 16 ; 0.407 ; 12 ; 0.000 ; 0.081 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]|clk ; +; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3] ; +; 6.278 ; 3.289 ; ; ; ; ; ; data path ; +; 3.110 ; 0.121 ; RR ; uTco ; 1 ; FF_X51_Y153_N38 ; ; vx_csr_handler|decode_csr_address[3]|q ; +; 3.173 ; 0.063 ; RR ; CELL ; 686 ; FF_X51_Y153_N38 ; High Speed ; vx_csr_handler|decode_csr_address[3]~la_lab/laboutb[5] ; +; 3.863 ; 0.690 ; RR ; IC ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|dataf ; +; 3.891 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145|combout ; +; 3.897 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X50_Y166_N42 ; High Speed ; vx_csr_handler|Mux_3~145~la_mlab/laboutb[9] ; +; 4.338 ; 0.441 ; FF ; IC ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|datac ; +; 4.419 ; 0.081 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146|combout ; +; 4.424 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X46_Y164_N27 ; High Speed ; vx_csr_handler|Mux_3~146~la_lab/laboutt[19] ; +; 4.779 ; 0.355 ; FF ; IC ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|dataf ; +; 4.807 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147|combout ; +; 4.813 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X45_Y157_N18 ; High Speed ; vx_csr_handler|Mux_3~147~la_mlab/laboutt[12] ; +; 5.076 ; 0.263 ; FF ; IC ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|datae ; +; 5.135 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169|combout ; +; 5.141 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X39_Y157_N36 ; High Speed ; vx_csr_handler|Mux_3~169~la_mlab/laboutb[5] ; +; 5.264 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datae ; +; 5.327 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.331 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.106 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.133 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.138 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.252 ; 0.114 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; +; 6.278 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; +; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; +; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.163 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1343: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.213 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.215 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.776 ; 86 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.319 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.213 ; 3.215 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.355 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.143 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.170 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.176 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.542 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.570 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.574 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.186 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.213 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1344: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.801 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.348 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.454 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.481 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.485 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.177 ; 0.692 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~555|datad ; +; 6.269 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X105_Y159_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~555|combout ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11]|d ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1345: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.265 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.267 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.694 ; 82 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.265 ; 3.267 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.370 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.450 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.454 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.173 ; 0.719 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|datad ; +; 6.265 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|combout ; +; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]|d ; +; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N38 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y150_N38 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1346: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.749 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.384 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.358 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; +; 5.436 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; +; 5.440 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[10] ; +; 6.226 ; 0.786 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~636|dataf ; +; 6.253 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~636|combout ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28]|d ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1347: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.798 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.236 ; 0.600 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|dataf ; +; 6.264 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|combout ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|d ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1348: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.808 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.243 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; +; 6.270 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1349: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.731 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.360 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; +; 5.440 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; +; 5.445 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; +; 6.218 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; +; 6.246 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1350: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++--------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+-----------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.877 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.431 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.459 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.464 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.239 ; 0.775 ; RR ; IC ; 1 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|dataf ; +; 6.266 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X107_Y152_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~964|combout ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|d ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y152_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y152_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][4]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1351: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.747 ; 84 ; 0.120 ; 1.275 ; +; Cell ; ; 12 ; 0.402 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.152 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; +; 6.269 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|d ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N11 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1352: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.280 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.778 ; 85 ; 0.104 ; 1.300 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.118 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.280 ; 3.282 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.162 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|datab ; +; 6.280 ; 0.118 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; +; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; +; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1353: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.827 ; 87 ; 0.110 ; 1.378 ; +; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.229 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.259 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1354: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|PC_next_out[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.068 ; +; Data Required Time ; 5.403 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.073 ; ; ; ; ; ; +; Data Delay ; 3.076 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.409 ; 78 ; 0.118 ; 0.829 ; +; Cell ; ; 10 ; 0.541 ; 18 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.068 ; 3.076 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.239 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.068 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; +; 6.068 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; +; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.403 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1355: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.277 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.616 ; 80 ; 0.147 ; 0.748 ; +; Cell ; ; 14 ; 0.540 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.275 ; 3.277 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.036 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; +; 6.062 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; +; 6.068 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; +; 6.215 ; 0.147 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; +; 6.275 ; 0.060 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; +; 6.275 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; +; 6.275 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1356: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.617 ; 80 ; 0.150 ; 0.746 ; +; Cell ; ; 14 ; 0.537 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.034 ; 0.746 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.060 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.066 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.216 ; 0.150 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.273 ; 0.057 ; FF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1357: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.839 ; 87 ; 0.106 ; 1.296 ; +; Cell ; ; 12 ; 0.306 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.237 ; 1.296 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|dataf ; +; 6.264 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1358: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.807 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.554 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.240 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~711|dataf ; +; 6.269 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~711|combout ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7]|d ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1359: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.046 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.804 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.177 ; 79 ; 0.000 ; 2.177 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.511 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.538 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.544 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.235 ; 0.691 ; RR ; IC ; 1 ; MLABCELL_X94_Y160_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~749|dataf ; +; 6.263 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X94_Y160_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~749|combout ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y160_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13]|d ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y160_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.452 ; 2.952 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.242 ; 2.177 ; RR ; IC ; 1 ; FF_X94_Y160_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13]|clk ; +; 5.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y160_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13] ; +; 5.452 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.422 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.176 ; ; uTsu ; 1 ; FF_X94_Y160_N38 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1360: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.279 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.281 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.753 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.279 ; 3.281 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; +; 6.187 ; 0.625 ; RR ; IC ; 1 ; MLABCELL_X107_Y153_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~577|datad ; +; 6.279 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X107_Y153_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~577|combout ; +; 6.279 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y153_N49 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1]|d ; +; 6.279 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y153_N49 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y153_N49 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y153_N49 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y153_N49 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][1] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1361: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|b_reg_data[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.220 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.222 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.624 ; 81 ; 0.192 ; 0.903 ; +; Cell ; ; 12 ; 0.477 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.220 ; 3.222 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.192 ; 0.903 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; +; 6.220 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; +; 6.220 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; +; 6.220 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1362: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++-----------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------+ +; Property ; Value ; ++--------------------+--------------------------+ +; From Node ; vx_d_e_reg|a_reg_data[0] ; +; To Node ; vx_e_m_reg|alu_result[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.167 ; +; Data Required Time ; 5.502 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+--------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.220 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.320 ; 79 ; 0.000 ; 2.320 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.526 ; 78 ; 0.132 ; 0.955 ; +; Cell ; ; 14 ; 0.467 ; 15 ; 0.000 ; 0.124 ; +; uTco ; ; 1 ; 0.227 ; 7 ; 0.227 ; 0.227 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.947 ; 2.947 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.947 ; 2.320 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; +; 2.947 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; +; 6.167 ; 3.220 ; ; ; ; ; ; data path ; +; 3.174 ; 0.227 ; FF ; uTco ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0]|q ; +; 3.221 ; 0.047 ; FF ; CELL ; 12 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]~la_lab/laboutb[1] ; +; 4.176 ; 0.955 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|dataa ; +; 4.300 ; 0.124 ; FR ; CELL ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|combout ; +; 4.305 ; 0.005 ; RR ; CELL ; 2 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28~la_mlab/laboutt[2] ; +; 4.437 ; 0.132 ; RR ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datae ; +; 4.510 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; +; 4.514 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; +; 4.729 ; 0.215 ; FF ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; +; 4.792 ; 0.063 ; FF ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.796 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.244 ; 0.448 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.272 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.278 ; 0.006 ; RR ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.413 ; 0.135 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|dataf ; +; 5.439 ; 0.026 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|combout ; +; 5.444 ; 0.005 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41~la_mlab/laboutb[0] ; +; 6.085 ; 0.641 ; RR ; IC ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|datac ; +; 6.167 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|combout ; +; 6.167 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|d ; +; 6.167 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.502 ; 0.167 ; ; uTsu ; 1 ; FF_X46_Y153_N31 ; ; vx_e_m_reg|alu_result[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1363: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.784 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.493 ; 0.575 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.519 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.525 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; +; 6.234 ; 0.709 ; FF ; IC ; 1 ; LABCELL_X95_Y144_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~979|dataf ; +; 6.264 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X95_Y144_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~979|combout ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19]|d ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y144_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y144_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1364: Setup slack is -0.665 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.579 ; +; Slack ; -0.665 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.053 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.784 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.170 ; 79 ; 0.000 ; 2.170 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.542 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; +; 6.216 ; 0.674 ; RR ; IC ; 1 ; LABCELL_X89_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~968|dataf ; +; 6.244 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~968|combout ; +; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8]|d ; +; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.445 ; 2.945 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.235 ; 2.170 ; RR ; IC ; 1 ; FF_X89_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8]|clk ; +; 5.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8] ; +; 5.445 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.415 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.579 ; 0.164 ; ; uTsu ; 1 ; FF_X89_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1365: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.212 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.220 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.641 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.212 ; 3.220 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.946 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; +; 4.070 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; +; 4.196 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.317 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.343 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.348 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.068 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.146 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.152 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.518 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.546 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.550 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.184 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.212 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.212 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.212 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1366: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.213 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.221 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.642 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.213 ; 3.221 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.946 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; +; 4.070 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; +; 4.196 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.317 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.343 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.348 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.068 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.146 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.152 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.518 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.546 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.550 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.185 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.213 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1367: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.671 ; 81 ; 0.128 ; 0.755 ; +; Cell ; ; 14 ; 0.482 ; 15 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.270 ; 3.278 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.235 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 5.990 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.017 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.023 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.194 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.270 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1368: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.046 ; ; ; ; ; ; +; Data Delay ; 3.253 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.794 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.177 ; 79 ; 0.000 ; 2.177 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.251 ; 3.253 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.627 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.655 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.661 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.223 ; 0.562 ; RR ; IC ; 1 ; LABCELL_X93_Y149_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~798|dataf ; +; 6.251 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y149_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~798|combout ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30]|d ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.452 ; 2.952 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.242 ; 2.177 ; RR ; IC ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30]|clk ; +; 5.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y149_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; +; 5.452 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.422 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y149_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1369: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.284 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.750 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.412 ; 13 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.282 ; 3.284 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.417 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.444 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.450 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.189 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|datac ; +; 6.282 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|combout ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|d ; +; 6.282 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y142_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1370: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.281 ; +; Data Required Time ; 5.617 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.027 ; ; ; ; ; ; +; Data Delay ; 3.283 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.814 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.281 ; 3.283 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.446 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.473 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.479 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.253 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|dataf ; +; 6.281 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|combout ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|d ; +; 6.281 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; +; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.617 ; 0.176 ; ; uTsu ; 1 ; FF_X107_Y149_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1371: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.274 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.276 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.828 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.274 ; 3.276 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.415 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.448 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.246 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|dataf ; +; 6.274 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|combout ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|d ; +; 6.274 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.164 ; ; uTsu ; 1 ; FF_X104_Y146_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1372: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.611 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.277 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.828 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.328 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.275 ; 3.277 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.442 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.473 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.477 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.247 ; 0.770 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|dataf ; +; 6.275 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|combout ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|d ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1373: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.759 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.532 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.177 ; 0.645 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|datad ; +; 6.264 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1374: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.262 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.264 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.816 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.262 ; 3.264 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.454 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.483 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.488 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.235 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|dataf ; +; 6.262 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|combout ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|d ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1375: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.258 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.813 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.258 ; 3.260 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.635 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.231 ; 0.596 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|dataf ; +; 6.258 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|combout ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|d ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1376: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|b_reg_data[17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.216 ; +; Data Required Time ; 5.552 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.078 ; ; ; ; ; ; +; Data Delay ; 3.218 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.631 ; 82 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.466 ; 14 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.216 ; 3.218 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.090 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|datab ; +; 6.216 ; 0.126 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|combout ; +; 6.216 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|d ; +; 6.216 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|clk ; +; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; +; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.552 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y152_N34 ; ; vx_d_e_reg|b_reg_data[17] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1377: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.790 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.355 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.391 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.418 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.423 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.171 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.263 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1378: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.850 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.292 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.420 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.447 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.453 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.232 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; +; 6.260 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1379: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.277 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.279 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.793 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.364 ; 11 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.277 ; 3.279 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.415 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.446 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.450 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.190 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; +; 6.277 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; +; 6.277 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; +; 6.277 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1380: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.258 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.782 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.356 ; 11 ; 0.000 ; 0.082 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.258 ; 3.260 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.419 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.446 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.451 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.176 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; +; 6.258 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; +; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; +; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1381: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.274 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.631 ; 80 ; 0.147 ; 0.748 ; +; Cell ; ; 14 ; 0.524 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.274 ; 3.282 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.287 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.035 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; +; 6.061 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; +; 6.067 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; +; 6.214 ; 0.147 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; +; 6.274 ; 0.060 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; +; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; +; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1382: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.280 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.632 ; 80 ; 0.150 ; 0.746 ; +; Cell ; ; 14 ; 0.521 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.272 ; 3.280 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.287 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.033 ; 0.746 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.059 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.065 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.215 ; 0.150 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.272 ; 0.057 ; FF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1383: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_mask[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.633 ; 81 ; 0.138 ; 0.722 ; +; Cell ; ; 14 ; 0.502 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.252 ; 3.260 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.565 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.591 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.597 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.224 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; +; 6.252 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1384: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_mask[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.633 ; 81 ; 0.138 ; 0.722 ; +; Cell ; ; 14 ; 0.502 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.252 ; 3.260 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.281 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.565 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.591 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.597 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.224 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; +; 6.252 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1385: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.041 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.777 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.360 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.400 ; 0.483 ; RR ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.428 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.433 ; 0.005 ; FF ; CELL ; 18 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[7] ; +; 6.227 ; 0.794 ; FF ; IC ; 1 ; MLABCELL_X98_Y164_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~518|dataf ; +; 6.256 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X98_Y164_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~518|combout ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y164_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6]|d ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y164_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X98_Y164_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6]|clk ; +; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y164_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6] ; +; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.165 ; ; uTsu ; 1 ; FF_X98_Y164_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1386: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.250 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.252 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.735 ; 84 ; 0.106 ; 1.205 ; +; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.250 ; 3.252 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.133 ; 1.205 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~15|datab ; +; 6.250 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~15|combout ; +; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15]|d ; +; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.165 ; ; uTsu ; 1 ; FF_X92_Y163_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[0][15] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1387: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.440 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N28 ; High Speed ; vx_d_e_reg|PC_next_out[11]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N28 ; High Speed ; vx_d_e_reg|PC_next_out[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N28 ; High Speed ; vx_d_e_reg|PC_next_out[11]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N28 ; High Speed ; vx_d_e_reg|PC_next_out[11] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.440 ; 0.054 ; ; uTsu ; 1 ; FF_X80_Y156_N28 ; ; vx_d_e_reg|PC_next_out[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1388: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.802 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.544 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[11] ; +; 6.236 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~686|dataf ; +; 6.263 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~686|combout ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14]|d ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1389: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.440 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N16 ; High Speed ; vx_d_e_reg|PC_next_out[7]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N16 ; High Speed ; vx_d_e_reg|PC_next_out[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N16 ; High Speed ; vx_d_e_reg|PC_next_out[7]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N16 ; High Speed ; vx_d_e_reg|PC_next_out[7] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.440 ; 0.054 ; ; uTsu ; 1 ; FF_X80_Y156_N16 ; ; vx_d_e_reg|PC_next_out[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1390: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|rs1[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.227 ; +; Data Required Time ; 5.563 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.229 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.682 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.426 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.227 ; 3.229 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.151 ; 0.736 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N51 ; High Speed ; vx_d_e_reg|i316~3|datad ; +; 6.227 ; 0.076 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N51 ; High Speed ; vx_d_e_reg|i316~3|combout ; +; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N53 ; High Speed ; vx_d_e_reg|rs1[3]|d ; +; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N53 ; High Speed ; vx_d_e_reg|rs1[3] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N53 ; High Speed ; vx_d_e_reg|rs1[3]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N53 ; High Speed ; vx_d_e_reg|rs1[3] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.563 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y155_N53 ; ; vx_d_e_reg|rs1[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1391: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.440 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N10 ; High Speed ; vx_d_e_reg|PC_next_out[5]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N10 ; High Speed ; vx_d_e_reg|PC_next_out[5] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N10 ; High Speed ; vx_d_e_reg|PC_next_out[5]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N10 ; High Speed ; vx_d_e_reg|PC_next_out[5] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.440 ; 0.054 ; ; uTsu ; 1 ; FF_X80_Y156_N10 ; ; vx_d_e_reg|PC_next_out[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1392: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|b_reg_data[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.219 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.227 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.639 ; 82 ; 0.192 ; 0.903 ; +; Cell ; ; 12 ; 0.461 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.219 ; 3.227 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.191 ; 0.903 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; +; 6.219 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; +; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; +; 6.219 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1393: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|b_reg_data[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.218 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.220 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.622 ; 81 ; 0.192 ; 0.901 ; +; Cell ; ; 12 ; 0.477 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.218 ; 3.220 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.190 ; 0.901 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; +; 6.218 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; +; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; +; 6.218 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1394: Setup slack is -0.664 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.664 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.684 ; 82 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.457 ; 14 ; 0.000 ; 0.094 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.408 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.488 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.492 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.166 ; 0.674 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~863|datac ; +; 6.260 ; 0.094 ; RR ; CELL ; 1 ; MLABCELL_X98_Y143_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~863|combout ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31]|d ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X98_Y143_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1395: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.210 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.218 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.639 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.210 ; 3.218 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.946 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; +; 4.070 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; +; 4.196 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.317 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.343 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.348 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.068 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.146 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.152 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.518 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.546 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.550 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.182 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.210 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.210 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.210 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1396: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[6] ; +; To Node ; vx_e_m_reg|csr_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.366 ; 79 ; 0.000 ; 2.366 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.736 ; 84 ; 0.119 ; 1.072 ; +; Cell ; ; 14 ; 0.411 ; 13 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.993 ; 2.993 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.993 ; 2.366 ; RR ; IC ; 1 ; FF_X51_Y160_N26 ; High Speed ; vx_csr_handler|decode_csr_address[6]|clk ; +; 2.993 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N26 ; High Speed ; vx_csr_handler|decode_csr_address[6] ; +; 6.261 ; 3.268 ; ; ; ; ; ; data path ; +; 3.114 ; 0.121 ; RR ; uTco ; 1 ; FF_X51_Y160_N26 ; ; vx_csr_handler|decode_csr_address[6]|q ; +; 3.183 ; 0.069 ; RR ; CELL ; 326 ; FF_X51_Y160_N26 ; High Speed ; vx_csr_handler|decode_csr_address[6]~la_lab/laboutt[17] ; +; 4.255 ; 1.072 ; RR ; IC ; 1 ; LABCELL_X38_Y145_N12 ; High Speed ; vx_csr_handler|Mux_3~189|datae ; +; 4.328 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X38_Y145_N12 ; High Speed ; vx_csr_handler|Mux_3~189|combout ; +; 4.332 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y145_N12 ; High Speed ; vx_csr_handler|Mux_3~189~la_lab/laboutt[8] ; +; 4.451 ; 0.119 ; FF ; IC ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|datac ; +; 4.535 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|combout ; +; 4.540 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190~la_lab/laboutb[9] ; +; 5.064 ; 0.524 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|dataf ; +; 5.090 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; +; 5.094 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; +; 5.218 ; 0.124 ; FF ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; +; 5.302 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.306 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.081 ; 0.775 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.108 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.113 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.235 ; 0.122 ; FF ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; +; 6.261 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; +; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1397: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.798 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.511 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.177 ; 0.666 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1003|datad ; +; 6.264 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1003|combout ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11]|d ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1398: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.741 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.170 ; 0.612 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|datac ; +; 6.263 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|combout ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|d ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1399: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_address[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.175 ; +; Data Required Time ; 5.512 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.122 ; ; ; ; ; ; +; Data Delay ; 3.177 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.695 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 12 ; 0.360 ; 11 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.175 ; 3.177 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.362 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.148 ; 0.786 ; RR ; IC ; 1 ; LABCELL_X51_Y152_N21 ; High Speed ; vx_d_e_reg|i498~4|dataf ; +; 6.175 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y152_N21 ; High Speed ; vx_d_e_reg|i498~4|combout ; +; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4]|d ; +; 6.175 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.376 ; 2.876 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y152_N22 ; High Speed ; vx_d_e_reg|csr_address[4] ; +; 5.376 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.346 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.512 ; 0.166 ; ; uTsu ; 1 ; FF_X51_Y152_N22 ; ; vx_d_e_reg|csr_address[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1400: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.051 ; ; ; ; ; ; +; Data Delay ; 3.263 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.798 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.261 ; 3.263 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.504 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.530 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.536 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.235 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|dataf ; +; 6.261 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|combout ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|d ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.447 ; 2.947 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; +; 5.447 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.417 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y163_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1401: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.262 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.264 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.817 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.262 ; 3.264 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.234 ; 0.600 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|dataf ; +; 6.262 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|combout ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|d ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1402: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.740 ; 84 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.203 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; +; 5.230 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; +; 5.235 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; +; 6.177 ; 0.942 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|datad ; +; 6.259 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|combout ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|d ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y162_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1403: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.748 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.393 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.470 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.475 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; +; 6.232 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; +; 6.259 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1404: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.275 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.277 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.867 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.275 ; 3.277 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.611 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.249 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; +; 6.275 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; +; 6.275 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1405: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.830 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.303 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.226 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; +; 6.253 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1406: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.814 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.410 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.437 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.443 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.219 ; 0.776 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|dataf ; +; 6.246 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~753|combout ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|d ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1407: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|a_reg_data[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.058 ; +; Data Required Time ; 5.395 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.060 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.671 ; 87 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.058 ; 3.060 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.058 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|sclr ; +; 6.058 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N32 ; ; vx_d_e_reg|a_reg_data[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1408: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|a_reg_data[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.058 ; +; Data Required Time ; 5.395 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.089 ; ; ; ; ; ; +; Data Delay ; 3.060 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.671 ; 87 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.134 ; 79 ; 0.000 ; 2.134 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.058 ; 3.060 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.058 ; 0.760 ; FF ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|sclr ; +; 6.058 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.409 ; 2.909 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.199 ; 2.134 ; RR ; IC ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10]|clk ; +; 5.199 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N38 ; High Speed ; vx_d_e_reg|a_reg_data[10] ; +; 5.409 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.379 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.395 ; 0.016 ; ; uTsu ; 1 ; FF_X79_Y154_N38 ; ; vx_d_e_reg|a_reg_data[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1409: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.258 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.825 ; 87 ; 0.114 ; 1.366 ; +; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.258 ; 3.260 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.230 ; 1.366 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|dataf ; +; 6.258 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|combout ; +; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|d ; +; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1410: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.267 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.766 ; 85 ; 0.104 ; 1.275 ; +; Cell ; ; 12 ; 0.382 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.267 ; 3.269 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.150 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; +; 6.267 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; +; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|d ; +; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N11 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1411: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[23] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.122 ; +; Data Required Time ; 5.459 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.124 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.122 ; 3.124 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; +; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[23]|sload ; +; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[23] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[23]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[23] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.459 ; 0.016 ; ; uTsu ; 1 ; FF_X72_Y160_N4 ; ; vx_fetch|VX_Warp_zero|real_PC[23] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1412: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.787 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.362 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.502 ; 0.584 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.531 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.536 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.239 ; 0.703 ; FF ; IC ; 1 ; LABCELL_X108_Y151_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~729|dataf ; +; 6.268 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X108_Y151_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~729|combout ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25]|d ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X108_Y151_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.166 ; ; uTsu ; 1 ; FF_X108_Y151_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1413: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.277 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.279 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.815 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.277 ; 3.279 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.555 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; +; 6.249 ; 0.694 ; RR ; IC ; 1 ; MLABCELL_X96_Y144_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~730|dataf ; +; 6.277 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X96_Y144_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~730|combout ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X96_Y144_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26]|d ; +; 6.277 ; 0.000 ; FF ; CELL ; 1 ; FF_X96_Y144_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X96_Y144_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y144_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.182 ; ; uTsu ; 1 ; FF_X96_Y144_N1 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1414: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.262 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.264 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.800 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.262 ; 3.264 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.509 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.541 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.546 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[17] ; +; 6.235 ; 0.689 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~790|dataf ; +; 6.262 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y144_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~790|combout ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y144_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22]|d ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y144_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y144_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1415: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.283 ; +; Data Required Time ; 5.620 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.011 ; ; ; ; ; ; +; Data Delay ; 3.285 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.805 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.199 ; 80 ; 0.000 ; 2.199 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.283 ; 3.285 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.255 ; 0.732 ; FF ; IC ; 1 ; LABCELL_X108_Y155_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~746|dataf ; +; 6.283 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X108_Y155_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~746|combout ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y155_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10]|d ; +; 6.283 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y155_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.487 ; 2.987 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.264 ; 2.199 ; RR ; IC ; 1 ; FF_X108_Y155_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10]|clk ; +; 5.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y155_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10] ; +; 5.487 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.457 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.620 ; 0.163 ; ; uTsu ; 1 ; FF_X108_Y155_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][10] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1416: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|b_reg_data[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.217 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.225 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.637 ; 82 ; 0.192 ; 0.901 ; +; Cell ; ; 12 ; 0.461 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.217 ; 3.225 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.189 ; 0.901 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; +; 6.217 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; +; 6.217 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; +; 6.217 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1417: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.122 ; +; Data Required Time ; 5.459 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.124 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.122 ; 3.124 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; +; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N16 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE|sload ; +; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N16 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N16 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N16 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.459 ; 0.016 ; ; uTsu ; 1 ; FF_X72_Y160_N16 ; ; vx_fetch|VX_Warp_zero|real_PC[27]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1418: Setup slack is -0.663 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.663 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.743 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.393 ; 0.476 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.467 ; 0.074 ; RF ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.471 ; 0.004 ; FF ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.238 ; 0.767 ; FF ; IC ; 1 ; MLABCELL_X101_Y161_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~878|dataf ; +; 6.263 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X101_Y161_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~878|combout ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14]|d ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X101_Y161_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1419: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.249 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.673 ; 82 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.459 ; 14 ; 0.000 ; 0.114 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.249 ; 3.257 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.153 ; 0.145 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataf ; +; 4.180 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.186 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.301 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.327 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.332 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.095 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.173 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.179 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.455 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.481 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.487 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.175 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.249 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1420: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.683 ; 82 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.464 ; 14 ; 0.000 ; 0.114 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.264 ; 3.272 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.153 ; 0.145 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataf ; +; 4.180 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.186 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.301 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.327 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.332 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.095 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.173 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.179 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.893 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.923 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.929 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.189 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.264 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1421: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.671 ; 81 ; 0.128 ; 0.755 ; +; Cell ; ; 14 ; 0.482 ; 15 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.270 ; 3.278 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.235 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 5.990 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.017 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.023 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.194 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.270 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1422: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.459 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.463 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.220 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X95_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~870|dataf ; +; 6.248 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X95_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~870|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.163 ; ; uTsu ; 1 ; FF_X95_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1423: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.736 ; 84 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.412 ; 13 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.469 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.500 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.504 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.176 ; 0.672 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|datad ; +; 6.268 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|combout ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|d ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1424: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.280 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.282 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.769 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.280 ; 3.282 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.415 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.448 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.187 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|datac ; +; 6.280 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|combout ; +; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|d ; +; 6.280 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y142_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1425: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.279 ; +; Data Required Time ; 5.617 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.027 ; ; ; ; ; ; +; Data Delay ; 3.281 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.833 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.279 ; 3.281 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.444 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.471 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.477 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.251 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|dataf ; +; 6.279 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|combout ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|d ; +; 6.279 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; +; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.617 ; 0.176 ; ; uTsu ; 1 ; FF_X107_Y149_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1426: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.790 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.355 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.391 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.418 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.423 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.171 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.263 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1427: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.234 ; +; Data Required Time ; 5.572 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.236 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.751 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.364 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.234 ; 3.236 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.309 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.389 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.393 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.207 ; 0.814 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|dataf ; +; 6.234 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~937|combout ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|d ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.572 ; 0.160 ; ; uTsu ; 1 ; FF_X89_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1428: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.245 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.856 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.271 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.245 ; 3.247 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.434 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.466 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.217 ; 0.751 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|dataf ; +; 6.245 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~527|combout ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|d ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y164_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1429: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.768 ; 85 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.377 ; 12 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.377 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.408 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.413 ; 0.005 ; RR ; CELL ; 8 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[15] ; +; 6.133 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|datab ; +; 6.263 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X97_Y144_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~918|combout ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|d ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1430: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|a_reg_data[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.106 ; +; Data Required Time ; 5.444 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.077 ; ; ; ; ; ; +; Data Delay ; 3.108 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.106 ; 3.108 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.106 ; 0.752 ; FF ; IC ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5]|sclr ; +; 6.106 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5]|clk ; +; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5] ; +; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.444 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y157_N46 ; ; vx_d_e_reg|a_reg_data[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1431: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|a_reg_data[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.106 ; +; Data Required Time ; 5.444 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.077 ; ; ; ; ; ; +; Data Delay ; 3.108 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.106 ; 3.108 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.106 ; 0.752 ; FF ; IC ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2]|sclr ; +; 6.106 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2]|clk ; +; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y157_N40 ; High Speed ; vx_d_e_reg|a_reg_data[2] ; +; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.444 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y157_N40 ; ; vx_d_e_reg|a_reg_data[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1432: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.827 ; 87 ; 0.110 ; 1.378 ; +; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.229 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.259 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1433: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|PC_next_out[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.064 ; +; Data Required Time ; 5.402 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.073 ; ; ; ; ; ; +; Data Delay ; 3.072 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.574 ; 84 ; 0.128 ; 0.829 ; +; Cell ; ; 10 ; 0.373 ; 12 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.064 ; 3.072 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.235 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.064 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; +; 6.064 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; +; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.402 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1434: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.263 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.835 ; 87 ; 0.106 ; 1.292 ; +; Cell ; ; 12 ; 0.307 ; 9 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.261 ; 3.263 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.233 ; 1.292 ; FF ; IC ; 1 ; MLABCELL_X107_Y158_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1003|dataf ; +; 6.261 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X107_Y158_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1003|combout ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11]|d ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X107_Y158_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1435: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.122 ; +; Data Required Time ; 5.460 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.124 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.122 ; 3.124 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; +; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N20 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28]|sload ; +; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N20 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N20 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N20 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.460 ; 0.017 ; ; uTsu ; 1 ; FF_X72_Y160_N20 ; ; vx_fetch|VX_Warp_zero|real_PC[28] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1436: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.033 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.804 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.545 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.237 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X97_Y145_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~916|dataf ; +; 6.264 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y145_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~916|combout ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20]|d ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X97_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20]|clk ; +; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20] ; +; 5.465 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y145_N52 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][20] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1437: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.757 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.486 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.513 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.517 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.186 ; 0.669 ; RR ; IC ; 1 ; LABCELL_X108_Y151_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~569|datad ; +; 6.268 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X108_Y151_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~569|combout ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25]|d ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X108_Y151_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N16 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y151_N16 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1438: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.442 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N20 ; High Speed ; vx_d_e_reg|PC_next_out[8]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N20 ; High Speed ; vx_d_e_reg|PC_next_out[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N20 ; High Speed ; vx_d_e_reg|PC_next_out[8]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N20 ; High Speed ; vx_d_e_reg|PC_next_out[8] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.442 ; 0.056 ; ; uTsu ; 1 ; FF_X80_Y156_N20 ; ; vx_d_e_reg|PC_next_out[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1439: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_mask[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.225 ; +; Data Required Time ; 5.563 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.227 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.683 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.423 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.225 ; 3.227 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.152 ; 0.737 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N42 ; High Speed ; vx_d_e_reg|i531~1|datae ; +; 6.225 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N42 ; High Speed ; vx_d_e_reg|i531~1|combout ; +; 6.225 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N43 ; High Speed ; vx_d_e_reg|csr_mask[1]|d ; +; 6.225 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N43 ; High Speed ; vx_d_e_reg|csr_mask[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N43 ; High Speed ; vx_d_e_reg|csr_mask[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N43 ; High Speed ; vx_d_e_reg|csr_mask[1] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.563 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y155_N43 ; ; vx_d_e_reg|csr_mask[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1440: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.442 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N8 ; High Speed ; vx_d_e_reg|PC_next_out[4]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N8 ; High Speed ; vx_d_e_reg|PC_next_out[4] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N8 ; High Speed ; vx_d_e_reg|PC_next_out[4]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N8 ; High Speed ; vx_d_e_reg|PC_next_out[4] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.442 ; 0.056 ; ; uTsu ; 1 ; FF_X80_Y156_N8 ; ; vx_d_e_reg|PC_next_out[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1441: Setup slack is -0.662 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.442 ; +; Slack ; -0.662 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N2 ; High Speed ; vx_d_e_reg|PC_next_out[2]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N2 ; High Speed ; vx_d_e_reg|PC_next_out[2] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N2 ; High Speed ; vx_d_e_reg|PC_next_out[2]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N2 ; High Speed ; vx_d_e_reg|PC_next_out[2] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.442 ; 0.056 ; ; uTsu ; 1 ; FF_X80_Y156_N2 ; ; vx_d_e_reg|PC_next_out[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1442: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.785 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.482 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.509 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.514 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.162 ; 0.648 ; RR ; IC ; 1 ; LABCELL_X93_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~845|datac ; +; 6.244 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X93_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~845|combout ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13]|d ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.162 ; ; uTsu ; 1 ; FF_X93_Y160_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1443: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.754 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.381 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.421 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.497 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.501 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.229 ; 0.728 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~831|dataf ; +; 6.255 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~831|combout ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31]|d ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1444: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.798 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.527 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.554 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.560 ; 0.006 ; RR ; CELL ; 6 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[11] ; +; 6.226 ; 0.666 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~540|dataf ; +; 6.254 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~540|combout ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28]|d ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1445: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.790 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.469 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.501 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.505 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.221 ; 0.716 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~796|dataf ; +; 6.248 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~796|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N38 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1446: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.782 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.220 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; +; 6.248 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1447: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.782 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.603 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.631 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.636 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.220 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; +; 6.248 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1448: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.051 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.817 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.323 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.502 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.528 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.534 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.233 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|dataf ; +; 6.259 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|combout ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|d ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.447 ; 2.947 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; +; 5.447 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.417 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y163_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1449: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.257 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.759 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.379 ; 12 ; 0.000 ; 0.082 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.257 ; 3.259 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.201 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; +; 5.228 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; +; 5.233 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; +; 6.175 ; 0.942 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|datad ; +; 6.257 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|combout ; +; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|d ; +; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y162_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1450: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.048 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.803 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.409 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.436 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.440 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.236 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; +; 6.264 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; +; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1451: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.267 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.805 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.267 ; 3.269 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.434 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.461 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.467 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.240 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; +; 6.267 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1452: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.242 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.244 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.820 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.242 ; 3.244 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.416 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.443 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.449 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.215 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; +; 6.242 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1453: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.826 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.315 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.409 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.436 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.442 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.232 ; 0.790 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|dataf ; +; 6.260 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1018|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y142_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1454: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.843 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.300 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.473 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.499 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.505 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.237 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; +; 6.263 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1455: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.844 ; 87 ; 0.104 ; 1.366 ; +; Cell ; ; 12 ; 0.293 ; 9 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.228 ; 1.366 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|dataf ; +; 6.256 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|combout ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|d ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1456: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.737 ; 84 ; 0.110 ; 1.275 ; +; Cell ; ; 12 ; 0.403 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.139 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.259 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1457: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.267 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.786 ; 85 ; 0.104 ; 1.302 ; +; Cell ; ; 12 ; 0.361 ; 11 ; 0.000 ; 0.119 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.267 ; 3.269 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.148 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; +; 6.267 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; +; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; +; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1458: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|PC_next_out[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.064 ; +; Data Required Time ; 5.403 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.073 ; ; ; ; ; ; +; Data Delay ; 3.072 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.574 ; 84 ; 0.128 ; 0.829 ; +; Cell ; ; 10 ; 0.373 ; 12 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.064 ; 3.072 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.235 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.064 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; +; 6.064 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; +; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.403 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1459: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.727 ; 83 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.420 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.501 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.530 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.535 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.179 ; 0.644 ; FF ; IC ; 1 ; MLABCELL_X96_Y142_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~662|datac ; +; 6.266 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X96_Y142_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~662|combout ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X96_Y142_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22]|d ; +; 6.266 ; 0.000 ; FF ; CELL ; 1 ; FF_X96_Y142_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X96_Y142_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y142_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.175 ; ; uTsu ; 1 ; FF_X96_Y142_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1460: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.122 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.124 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.122 ; 3.124 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; +; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N2 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[22]|sload ; +; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N2 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[22] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N2 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[22]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N2 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[22] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.018 ; ; uTsu ; 1 ; FF_X72_Y160_N2 ; ; vx_fetch|VX_Warp_zero|real_PC[22] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1461: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.787 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.438 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.442 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.216 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~527|dataf ; +; 6.243 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X94_Y164_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~527|combout ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]|d ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.164 ; ; uTsu ; 1 ; FF_X94_Y164_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1462: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.803 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.568 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.594 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.599 ; 0.005 ; RR ; CELL ; 12 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[10] ; +; 6.232 ; 0.633 ; RR ; IC ; 1 ; LABCELL_X95_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~895|dataf ; +; 6.259 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~895|combout ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31]|d ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.164 ; ; uTsu ; 1 ; FF_X95_Y145_N29 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][31] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1463: Setup slack is -0.661 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.661 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.253 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.739 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.251 ; 3.253 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.599 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.169 ; 0.570 ; RR ; IC ; 1 ; LABCELL_X97_Y158_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~512|datac ; +; 6.251 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X97_Y158_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~512|combout ; +; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0]|d ; +; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y158_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y158_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][0] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1464: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.208 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.210 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.574 ; 80 ; 0.127 ; 0.668 ; +; Cell ; ; 14 ; 0.515 ; 16 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.208 ; 3.210 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; +; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.077 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.157 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.162 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.289 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.410 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.415 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.072 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.165 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.171 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.537 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.565 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.569 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.181 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.208 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.208 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.208 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1465: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.208 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.210 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.626 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.208 ; 3.210 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.938 ; 0.084 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.942 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; +; 4.066 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; +; 4.192 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.198 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.313 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.339 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.344 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.064 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.142 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.148 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.514 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.542 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.546 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.180 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.208 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.208 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.208 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1466: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.209 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.211 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.627 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.209 ; 3.211 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.938 ; 0.084 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.942 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; +; 4.066 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; +; 4.192 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.198 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.313 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.339 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.344 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.064 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.142 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.148 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.514 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.542 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.546 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.181 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.209 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.209 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.209 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1467: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.657 ; 81 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.483 ; 15 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; +; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.056 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; +; 4.163 ; 0.107 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.169 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.284 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.310 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.315 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.078 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.156 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.162 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.870 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.898 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.904 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.184 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.259 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1468: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.267 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.644 ; 81 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.497 ; 15 ; 0.000 ; 0.113 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.259 ; 3.267 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.919 ; 0.113 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.925 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[4] ; +; 4.076 ; 0.151 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datac ; +; 4.163 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.169 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.284 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.310 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.315 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.078 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.156 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.162 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.870 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.898 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.904 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.184 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.259 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1469: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-----------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------+ +; Property ; Value ; ++--------------------+--------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[4] ; +; To Node ; vx_e_m_reg|alu_result[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.161 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+--------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.083 ; ; ; ; ; ; +; Data Delay ; 3.213 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.575 ; 80 ; 0.109 ; 0.747 ; +; Cell ; ; 16 ; 0.516 ; 16 ; 0.000 ; 0.127 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N43 ; High Speed ; vx_d_e_reg|b_reg_data[4]|clk ; +; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N43 ; High Speed ; vx_d_e_reg|b_reg_data[4] ; +; 6.161 ; 3.213 ; ; ; ; ; ; data path ; +; 3.070 ; 0.122 ; FF ; uTco ; 1 ; FF_X79_Y153_N43 ; ; vx_d_e_reg|b_reg_data[4]|q ; +; 3.138 ; 0.068 ; FF ; CELL ; 4 ; FF_X79_Y153_N43 ; High Speed ; vx_d_e_reg|b_reg_data[4]~la_lab/laboutb[8] ; +; 3.884 ; 0.746 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~18|dataf ; +; 3.911 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~18|combout ; +; 3.915 ; 0.004 ; FF ; CELL ; 42 ; LABCELL_X73_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~18~la_lab/laboutb[2] ; +; 4.081 ; 0.166 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N6 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~27|datab ; +; 4.189 ; 0.108 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N6 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~27|combout ; +; 4.194 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X73_Y153_N6 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~27~la_lab/laboutt[5] ; +; 4.303 ; 0.109 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|dataa ; +; 4.430 ; 0.127 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; +; 4.434 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; +; 4.651 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; +; 4.726 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.730 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.163 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.190 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.196 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.353 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; +; 5.381 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; +; 5.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; +; 6.133 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; +; 6.161 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; +; 6.161 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; +; 6.161 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1470: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|csr_mask[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.794 ; 86 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.561 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.587 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.593 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.220 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|dataf ; +; 6.248 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N45 ; High Speed ; vx_d_e_reg|i531~6|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N47 ; High Speed ; vx_d_e_reg|csr_mask[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N47 ; ; vx_d_e_reg|csr_mask[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1471: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|csr_mask[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.794 ; 86 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.456 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.244 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.271 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.277 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.561 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.587 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.593 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.220 ; 0.627 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|dataf ; +; 6.248 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N36 ; High Speed ; vx_d_e_reg|i531~8|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N37 ; High Speed ; vx_d_e_reg|csr_mask[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N37 ; ; vx_d_e_reg|csr_mask[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1472: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.835 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.494 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.526 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.530 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; +; 6.216 ; 0.686 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~585|dataf ; +; 6.243 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~585|combout ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9]|d ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1473: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.795 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.477 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.510 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; +; 6.174 ; 0.664 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~971|datad ; +; 6.260 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~971|combout ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11]|d ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1474: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.265 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.267 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.694 ; 82 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.265 ; 3.267 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.370 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.450 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.454 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.173 ; 0.719 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|datad ; +; 6.265 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y150_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~953|combout ; +; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE|d ; +; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y150_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1475: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.807 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.358 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; +; 5.387 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; +; 5.391 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; +; 6.235 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; +; 6.264 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1476: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.798 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.503 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.227 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1020|dataf ; +; 6.254 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1020|combout ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28]|d ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y144_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1477: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.242 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.244 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.823 ; 87 ; 0.119 ; 1.046 ; +; Cell ; ; 14 ; 0.299 ; 9 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.242 ; 3.244 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.604 ; 0.119 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.631 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.636 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.682 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.708 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.712 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.837 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.861 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.867 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.450 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.479 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.485 ; 0.006 ; FF ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; +; 6.216 ; 0.731 ; FF ; IC ; 1 ; MLABCELL_X94_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~655|dataf ; +; 6.242 ; 0.026 ; FF ; CELL ; 1 ; MLABCELL_X94_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~655|combout ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15]|d ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.164 ; ; uTsu ; 1 ; FF_X94_Y164_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1478: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|rs1[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.224 ; +; Data Required Time ; 5.564 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.226 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.726 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.378 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.224 ; 3.226 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.196 ; 0.843 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N0 ; High Speed ; vx_d_e_reg|i316~1|dataf ; +; 6.224 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N0 ; High Speed ; vx_d_e_reg|i316~1|combout ; +; 6.224 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1]|d ; +; 6.224 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N2 ; High Speed ; vx_d_e_reg|rs1[1] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N2 ; ; vx_d_e_reg|rs1[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1479: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.249 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.251 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.678 ; 82 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.249 ; 3.251 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.347 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.427 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.431 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.167 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; +; 6.249 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; +; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|d ; +; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y164_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1480: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.274 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.276 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.750 ; 84 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.274 ; 3.276 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.533 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.188 ; 0.655 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|datac ; +; 6.274 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|combout ; +; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|d ; +; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X103_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1481: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.755 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.467 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.498 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.502 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.174 ; 0.672 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|datad ; +; 6.266 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|combout ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|d ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1482: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.735 ; 84 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.399 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.203 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; +; 5.230 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; +; 5.235 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; +; 6.172 ; 0.937 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|datad ; +; 6.254 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|combout ; +; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|d ; +; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1483: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.253 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.818 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.314 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.251 ; 3.253 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.224 ; 0.624 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|dataf ; +; 6.251 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~781|combout ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|d ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1484: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.238 ; +; Data Required Time ; 5.578 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.240 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.806 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.238 ; 3.240 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.599 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.211 ; 0.612 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|dataf ; +; 6.238 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~776|combout ; +; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|d ; +; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.578 ; 0.164 ; ; uTsu ; 1 ; FF_X93_Y162_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1485: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|b_reg_data[25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.213 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.077 ; ; ; ; ; ; +; Data Delay ; 3.215 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.778 ; 86 ; 0.119 ; 0.855 ; +; Cell ; ; 12 ; 0.317 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.213 ; 3.215 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.185 ; 0.855 ; RR ; IC ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|dataf ; +; 6.213 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|combout ; +; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|d ; +; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|clk ; +; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; +; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.162 ; ; uTsu ; 1 ; FF_X80_Y149_N44 ; ; vx_d_e_reg|b_reg_data[25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1486: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.800 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.380 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.457 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.461 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.229 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; +; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1487: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|a_reg_data[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.101 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.103 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.714 ; 87 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.101 ; 3.103 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.101 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|sclr ; +; 6.101 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N40 ; High Speed ; vx_d_e_reg|a_reg_data[8] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N40 ; ; vx_d_e_reg|a_reg_data[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1488: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|a_reg_data[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.101 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.103 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.714 ; 87 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.101 ; 3.103 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.101 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|sclr ; +; 6.101 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1489: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|a_reg_data[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.101 ; +; Data Required Time ; 5.441 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.103 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.714 ; 87 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.101 ; 3.103 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.101 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|sclr ; +; 6.101 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N43 ; High Speed ; vx_d_e_reg|a_reg_data[6] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.441 ; 0.053 ; ; uTsu ; 1 ; FF_X79_Y156_N43 ; ; vx_d_e_reg|a_reg_data[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1490: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.770 ; 85 ; 0.116 ; 1.302 ; +; Cell ; ; 12 ; 0.370 ; 11 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.142 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|datab ; +; 6.259 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~942|combout ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|d ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1491: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.747 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.413 ; 0.485 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~17|datad ; +; 5.489 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~17|combout ; +; 5.493 ; 0.004 ; RR ; CELL ; 15 ; LABCELL_X99_Y153_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~17~la_lab/laboutb[2] ; +; 6.225 ; 0.732 ; RR ; IC ; 1 ; LABCELL_X95_Y142_N45 ; Mixed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~566|dataf ; +; 6.253 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X95_Y142_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~566|combout ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y142_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22]|d ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y142_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X95_Y142_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y142_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.163 ; ; uTsu ; 1 ; FF_X95_Y142_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1492: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.748 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.470 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.547 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.551 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.227 ; 0.676 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~604|dataf ; +; 6.254 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~604|combout ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28]|d ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y144_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1493: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.444 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N50 ; High Speed ; vx_d_e_reg|PC_next_out[18]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N50 ; High Speed ; vx_d_e_reg|PC_next_out[18] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N50 ; High Speed ; vx_d_e_reg|PC_next_out[18]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N50 ; High Speed ; vx_d_e_reg|PC_next_out[18] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.444 ; 0.058 ; ; uTsu ; 1 ; FF_X80_Y156_N50 ; ; vx_d_e_reg|PC_next_out[18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1494: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.444 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N38 ; High Speed ; vx_d_e_reg|PC_next_out[14]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N38 ; High Speed ; vx_d_e_reg|PC_next_out[14] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N38 ; High Speed ; vx_d_e_reg|PC_next_out[14]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N38 ; High Speed ; vx_d_e_reg|PC_next_out[14] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.444 ; 0.058 ; ; uTsu ; 1 ; FF_X80_Y156_N38 ; ; vx_d_e_reg|PC_next_out[14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1495: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[12] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.444 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N32 ; High Speed ; vx_d_e_reg|PC_next_out[12]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N32 ; High Speed ; vx_d_e_reg|PC_next_out[12] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N32 ; High Speed ; vx_d_e_reg|PC_next_out[12]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N32 ; High Speed ; vx_d_e_reg|PC_next_out[12] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.444 ; 0.058 ; ; uTsu ; 1 ; FF_X80_Y156_N32 ; ; vx_d_e_reg|PC_next_out[12] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1496: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.792 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.362 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.190 ; 0.264 ; RR ; IC ; 1 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11|dataf ; +; 5.218 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11|combout ; +; 5.224 ; 0.006 ; FF ; CELL ; 3 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11~la_mlab/laboutt[0] ; +; 6.244 ; 1.020 ; FF ; IC ; 1 ; MLABCELL_X101_Y160_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~354|dataf ; +; 6.273 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X101_Y160_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~354|combout ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2]|d ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y160_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][2] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1497: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.289 ; +; Data Required Time ; 5.629 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.111 ; ; ; ; ; ; +; Data Delay ; 2.219 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.327 ; 76 ; 0.000 ; 2.327 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.834 ; 83 ; 0.422 ; 0.843 ; +; Cell ; ; 8 ; 0.252 ; 11 ; 0.000 ; 0.132 ; +; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.070 ; 3.070 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.070 ; 2.327 ; FF ; IC ; 1 ; FF_X104_Y149_N40 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25]|clk ; +; 4.070 ; 0.000 ; FR ; CELL ; 1 ; FF_X104_Y149_N40 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25] ; +; 6.289 ; 2.219 ; ; ; ; ; ; data path ; +; 4.203 ; 0.133 ; RR ; uTco ; 1 ; FF_X104_Y149_N40 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25]|q ; +; 4.264 ; 0.061 ; RR ; CELL ; 1 ; FF_X104_Y149_N40 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25]~la_lab/laboutb[6] ; +; 4.833 ; 0.569 ; RR ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|dataa ; +; 4.965 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; +; 4.969 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; +; 5.812 ; 0.843 ; RR ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; +; 5.836 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; +; 5.841 ; 0.005 ; RR ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; +; 6.263 ; 0.422 ; RR ; IC ; 1 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|dataf ; +; 6.289 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|combout ; +; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE|d ; +; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE|clk ; +; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N37 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; +; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X75_Y158_N37 ; ; vx_fetch|VX_Warp_three|real_PC[25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1498: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|b_reg_data[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.214 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.216 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.618 ; 81 ; 0.192 ; 0.897 ; +; Cell ; ; 12 ; 0.477 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.214 ; 3.216 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.186 ; 0.897 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; +; 6.214 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; +; 6.214 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; +; 6.214 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1499: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[25] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.289 ; +; Data Required Time ; 5.629 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.111 ; ; ; ; ; ; +; Data Delay ; 2.219 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.327 ; 76 ; 0.000 ; 2.327 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.834 ; 83 ; 0.422 ; 0.843 ; +; Cell ; ; 8 ; 0.252 ; 11 ; 0.000 ; 0.132 ; +; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.070 ; 3.070 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.070 ; 2.327 ; FF ; IC ; 1 ; FF_X104_Y149_N40 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25]|clk ; +; 4.070 ; 0.000 ; FR ; CELL ; 1 ; FF_X104_Y149_N40 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25] ; +; 6.289 ; 2.219 ; ; ; ; ; ; data path ; +; 4.203 ; 0.133 ; RR ; uTco ; 1 ; FF_X104_Y149_N40 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25]|q ; +; 4.264 ; 0.061 ; RR ; CELL ; 1 ; FF_X104_Y149_N40 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[25]~la_lab/laboutb[6] ; +; 4.833 ; 0.569 ; RR ; IC ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|dataa ; +; 4.965 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55|combout ; +; 4.969 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X79_Y150_N15 ; High Speed ; vx_decode|out_a_reg_data[0]~55~la_lab/laboutt[10] ; +; 5.812 ; 0.843 ; RR ; IC ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|dataf ; +; 5.836 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56|combout ; +; 5.841 ; 0.005 ; RR ; CELL ; 4 ; MLABCELL_X76_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~56~la_mlab/laboutt[2] ; +; 6.263 ; 0.422 ; RR ; IC ; 1 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|dataf ; +; 6.289 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X75_Y158_N36 ; High Speed ; vx_fetch|VX_Warp_three|i199~22|combout ; +; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]|d ; +; 6.289 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25] ; ++---------+---------+----+------+--------+----------------------+------------+--------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25]|clk ; +; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X75_Y158_N38 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[25] ; +; 5.459 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.629 ; 0.200 ; ; uTsu ; 1 ; FF_X75_Y158_N38 ; ; vx_fetch|VX_Warp_three|real_PC[25] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1500: Setup slack is -0.660 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.660 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.754 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.408 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.488 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.492 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.236 ; 0.744 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~839|dataf ; +; 6.264 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~839|combout ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7]|d ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N49 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1501: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.206 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.208 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.624 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.463 ; 14 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.206 ; 3.208 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.938 ; 0.084 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.942 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; +; 4.066 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; +; 4.192 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.198 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.313 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.339 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.344 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.064 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.142 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.148 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.514 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.542 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.546 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.178 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.206 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.206 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.206 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1502: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.699 ; 83 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.428 ; 13 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.246 ; 3.254 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; +; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.070 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; +; 4.177 ; 0.107 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.183 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.298 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.324 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.329 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.092 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.170 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.176 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.452 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.478 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.484 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.172 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.246 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1503: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.709 ; 83 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.433 ; 13 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.261 ; 3.269 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; +; 3.943 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.947 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.070 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; +; 4.177 ; 0.107 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.183 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.298 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.324 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.329 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.092 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.170 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.176 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.890 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.920 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.926 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.186 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.261 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1504: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.263 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.582 ; 79 ; 0.118 ; 0.714 ; +; Cell ; ; 14 ; 0.560 ; 17 ; 0.000 ; 0.111 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.261 ; 3.263 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; +; 3.935 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.939 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.078 ; 0.139 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.157 ; 0.079 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.162 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.280 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.391 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.396 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.079 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.170 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.176 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.890 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.920 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.926 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.186 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.261 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1505: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.258 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.852 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.258 ; 3.260 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.230 ; 0.665 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|dataf ; +; 6.258 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|combout ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]|d ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1506: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.863 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.477 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.509 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.514 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[17] ; +; 6.245 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~786|dataf ; +; 6.271 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~786|combout ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18]|d ; +; 6.271 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1507: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.808 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.528 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.554 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.560 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.235 ; 0.675 ; RR ; IC ; 1 ; LABCELL_X108_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~868|dataf ; +; 6.263 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X108_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~868|combout ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4]|d ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1508: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_mask[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.223 ; +; Data Required Time ; 5.564 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.225 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.725 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.378 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.223 ; 3.225 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.353 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.195 ; 0.842 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N6 ; High Speed ; vx_d_e_reg|i531~0|dataf ; +; 6.223 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N6 ; High Speed ; vx_d_e_reg|i531~0|combout ; +; 6.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0]|d ; +; 6.223 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N7 ; High Speed ; vx_d_e_reg|csr_mask[0] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N7 ; ; vx_d_e_reg|csr_mask[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1509: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.249 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.251 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.678 ; 82 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.249 ; 3.251 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.347 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.427 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.431 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.167 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; +; 6.249 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; +; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|d ; +; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1510: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.258 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.258 ; 3.260 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.445 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.477 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.481 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.232 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|dataf ; +; 6.258 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|combout ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|d ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1511: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.242 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.244 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.776 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.242 ; 3.244 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.534 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.215 ; 0.681 ; RR ; IC ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|dataf ; +; 6.242 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|combout ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|d ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1512: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.801 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.218 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; +; 6.246 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|d ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1513: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.801 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.601 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.629 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.634 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.218 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; +; 6.246 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|d ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1514: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.258 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.771 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.367 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.258 ; 3.260 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.834 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.386 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.413 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.418 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.166 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.258 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; +; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1515: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.831 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.304 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.834 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.415 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.448 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.227 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; +; 6.255 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1516: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|a_reg_data[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.101 ; +; Data Required Time ; 5.442 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.103 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.714 ; 87 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.269 ; 9 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.101 ; 3.103 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.101 ; 0.803 ; FF ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|sclr ; +; 6.101 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N32 ; High Speed ; vx_d_e_reg|a_reg_data[0] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.442 ; 0.054 ; ; uTsu ; 1 ; FF_X79_Y156_N32 ; ; vx_d_e_reg|a_reg_data[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1517: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.803 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.236 ; 0.693 ; RR ; IC ; 1 ; LABCELL_X102_Y147_N0 ; Mixed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~693|dataf ; +; 6.263 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y147_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~693|combout ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y147_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21]|d ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y147_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y147_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y147_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y147_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][21] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1518: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.747 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; +; 6.181 ; 0.619 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~601|datad ; +; 6.273 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y151_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~601|combout ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]|d ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1519: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|b_reg_data[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.213 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.221 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.633 ; 82 ; 0.192 ; 0.897 ; +; Cell ; ; 12 ; 0.461 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.213 ; 3.221 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.185 ; 0.897 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; +; 6.213 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; +; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; +; 6.213 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1520: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.787 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.438 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.442 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.216 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~527|dataf ; +; 6.243 ; 0.027 ; RF ; CELL ; 2 ; MLABCELL_X94_Y164_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~527|combout ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE|d ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y164_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][15]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1521: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.747 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.407 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; +; 6.181 ; 0.619 ; RR ; IC ; 1 ; MLABCELL_X107_Y151_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~601|datad ; +; 6.273 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X107_Y151_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~601|combout ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE|d ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X107_Y151_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y151_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X107_Y151_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1522: Setup slack is -0.659 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.274 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.659 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.276 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.749 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.094 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.274 ; 3.276 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.541 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.180 ; 0.639 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~962|datac ; +; 6.274 ; 0.094 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~962|combout ; +; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2]|d ; +; 6.274 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1523: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[28] ; +; To Node ; vx_e_m_reg|alu_result[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.159 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.087 ; ; ; ; ; ; +; Data Delay ; 3.207 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.325 ; 79 ; 0.000 ; 2.325 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.544 ; 79 ; 0.120 ; 0.813 ; +; Cell ; ; 16 ; 0.482 ; 15 ; 0.000 ; 0.132 ; +; uTco ; ; 1 ; 0.181 ; 6 ; 0.181 ; 0.181 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.952 ; 2.952 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.952 ; 2.325 ; RR ; IC ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]|clk ; +; 2.952 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28] ; +; 6.159 ; 3.207 ; ; ; ; ; ; data path ; +; 3.133 ; 0.181 ; FF ; uTco ; 1 ; FF_X79_Y149_N52 ; ; vx_d_e_reg|b_reg_data[28]|q ; +; 3.177 ; 0.044 ; FF ; CELL ; 4 ; FF_X79_Y149_N52 ; High Speed ; vx_d_e_reg|b_reg_data[28]~la_lab/laboutb[14] ; +; 3.990 ; 0.813 ; FF ; IC ; 1 ; LABCELL_X73_Y151_N45 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~41|dataf ; +; 4.017 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X73_Y151_N45 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~41|combout ; +; 4.022 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X73_Y151_N45 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~41~la_lab/laboutb[11] ; +; 4.164 ; 0.142 ; RR ; IC ; 1 ; MLABCELL_X72_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~45|datae ; +; 4.242 ; 0.078 ; RF ; CELL ; 1 ; MLABCELL_X72_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~45|combout ; +; 4.248 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~45~la_mlab/laboutb[16] ; +; 4.380 ; 0.132 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|datac ; +; 4.466 ; 0.086 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|combout ; +; 4.472 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46~la_mlab/laboutt[8] ; +; 4.592 ; 0.120 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|dataa ; +; 4.724 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.728 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.161 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.188 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.194 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.351 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; +; 5.379 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; +; 5.384 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; +; 6.131 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; +; 6.159 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; +; 6.159 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; +; 6.159 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1524: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.206 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.214 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.685 ; 84 ; 0.115 ; 0.734 ; +; Cell ; ; 14 ; 0.402 ; 13 ; 0.000 ; 0.128 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.206 ; 3.214 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; +; 3.942 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.946 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.062 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; +; 4.190 ; 0.128 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.196 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.311 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.337 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.342 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.062 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.140 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.146 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.512 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.540 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.544 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.178 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.206 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.206 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.206 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1525: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.207 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.215 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.686 ; 84 ; 0.115 ; 0.734 ; +; Cell ; ; 14 ; 0.402 ; 13 ; 0.000 ; 0.128 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.207 ; 3.215 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; +; 3.942 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.946 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.062 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; +; 4.190 ; 0.128 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.196 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.311 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.337 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.342 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.062 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.140 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.146 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.512 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.540 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.544 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.179 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.207 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.207 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.207 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1526: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.240 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.242 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.833 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.240 ; 3.242 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.511 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.212 ; 0.701 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1001|dataf ; +; 6.240 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1001|combout ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9]|d ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y159_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1527: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.276 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.278 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.820 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.276 ; 3.278 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.459 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.463 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.249 ; 0.786 ; RR ; IC ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|dataf ; +; 6.276 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|combout ; +; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|d ; +; 6.276 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.181 ; ; uTsu ; 1 ; FF_X101_Y160_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1528: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.253 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.843 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.251 ; 3.253 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.488 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.517 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.523 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; +; 6.224 ; 0.701 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~732|dataf ; +; 6.251 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~732|combout ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28]|d ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1529: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.240 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.242 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.834 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.240 ; 3.242 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.566 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.213 ; 0.647 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~969|dataf ; +; 6.240 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~969|combout ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9]|d ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y159_N37 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1530: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.853 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.233 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|dataf ; +; 6.260 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.164 ; ; uTsu ; 1 ; FF_X108_Y150_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1531: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.245 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.787 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.245 ; 3.247 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.486 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.518 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.522 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; +; 6.218 ; 0.696 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~604|dataf ; +; 6.245 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~604|combout ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28]|d ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1532: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.803 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.480 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.509 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.514 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.233 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X104_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~718|dataf ; +; 6.260 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y160_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~718|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.166 ; ; uTsu ; 1 ; FF_X104_Y160_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1533: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.771 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.430 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.507 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.247 ; 0.736 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|dataf ; +; 6.273 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; +; 6.273 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1534: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|csr_address[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.170 ; +; Data Required Time ; 5.512 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.122 ; ; ; ; ; ; +; Data Delay ; 3.172 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.689 ; 85 ; 0.119 ; 0.821 ; +; Cell ; ; 12 ; 0.361 ; 11 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.170 ; 3.172 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.258 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.341 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.346 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.465 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.538 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.542 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.330 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.357 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.362 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.142 ; 0.780 ; RR ; IC ; 1 ; LABCELL_X51_Y152_N9 ; High Speed ; vx_d_e_reg|i498~2|dataf ; +; 6.170 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X51_Y152_N9 ; High Speed ; vx_d_e_reg|i498~2|combout ; +; 6.170 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2]|d ; +; 6.170 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.376 ; 2.876 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y152_N11 ; High Speed ; vx_d_e_reg|csr_address[2] ; +; 5.376 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.346 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.512 ; 0.166 ; ; uTsu ; 1 ; FF_X51_Y152_N11 ; ; vx_d_e_reg|csr_address[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1535: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.738 ; 84 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.413 ; 13 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.445 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.477 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.481 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.179 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|datac ; +; 6.271 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|combout ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|d ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1536: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.697 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.431 ; 13 ; 0.000 ; 0.082 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.345 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.425 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.429 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.165 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; +; 6.247 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|d ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y164_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1537: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.769 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.384 ; 12 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.531 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.186 ; 0.655 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|datac ; +; 6.272 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|combout ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|d ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X103_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1538: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.754 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.379 ; 12 ; 0.000 ; 0.082 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.201 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; +; 5.228 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; +; 5.233 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; +; 6.170 ; 0.937 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|datad ; +; 6.252 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|combout ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|d ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1539: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.848 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.606 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.244 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; +; 6.270 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1540: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.271 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.273 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.777 ; 85 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.375 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.271 ; 3.273 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.409 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.440 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.444 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.184 ; 0.740 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|datad ; +; 6.271 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~900|combout ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|d ; +; 6.271 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1541: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.766 ; 85 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.367 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.413 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.440 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.445 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.170 ; 0.725 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|datad ; +; 6.252 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~846|combout ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|d ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1542: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|b_reg_data[25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.211 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.077 ; ; ; ; ; ; +; Data Delay ; 3.213 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.744 ; 85 ; 0.108 ; 0.876 ; +; Cell ; ; 12 ; 0.347 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.146 ; 79 ; 0.000 ; 2.146 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.211 ; 3.213 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.184 ; 0.876 ; FF ; IC ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|dataf ; +; 6.211 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X80_Y149_N42 ; High Speed ; vx_d_e_reg|i385~78|combout ; +; 6.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|d ; +; 6.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.421 ; 2.921 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.211 ; 2.146 ; RR ; IC ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25]|clk ; +; 5.211 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y149_N44 ; High Speed ; vx_d_e_reg|b_reg_data[25] ; +; 5.421 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.391 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.162 ; ; uTsu ; 1 ; FF_X80_Y149_N44 ; ; vx_d_e_reg|b_reg_data[25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1543: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.585 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.790 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.353 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.380 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.384 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.150 ; 0.766 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|datac ; +; 6.243 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~557|combout ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|d ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y165_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1544: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|PC_next_out[29] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.077 ; +; Data Required Time ; 5.419 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.079 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.077 ; 3.079 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29]|sclr ; +; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N22 ; High Speed ; vx_d_e_reg|PC_next_out[29] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.419 ; 0.014 ; ; uTsu ; 1 ; FF_X80_Y155_N22 ; ; vx_d_e_reg|PC_next_out[29] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1545: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|b_reg_data[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.213 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.221 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.524 ; 78 ; 0.118 ; 0.944 ; +; Cell ; ; 12 ; 0.571 ; 18 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.213 ; 3.221 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.184 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; +; 6.213 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; +; 6.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; +; 6.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1546: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|b_reg_data[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.213 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.221 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.523 ; 78 ; 0.118 ; 0.943 ; +; Cell ; ; 12 ; 0.572 ; 18 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.213 ; 3.221 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.183 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; +; 6.213 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; +; 6.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; +; 6.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1547: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.122 ; +; Data Required Time ; 5.464 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.124 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.122 ; 3.124 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; +; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[30]|sload ; +; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[30] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[30]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N25 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[30] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.464 ; 0.021 ; ; uTsu ; 1 ; FF_X72_Y160_N25 ; ; vx_fetch|VX_Warp_zero|real_PC[30] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1548: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.781 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.214 ; 0.646 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1009|dataf ; +; 6.241 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1009|combout ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17]|d ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1549: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.446 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N25 ; High Speed ; vx_d_e_reg|PC_next_out[10]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N25 ; High Speed ; vx_d_e_reg|PC_next_out[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N25 ; High Speed ; vx_d_e_reg|PC_next_out[10]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N25 ; High Speed ; vx_d_e_reg|PC_next_out[10] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.446 ; 0.060 ; ; uTsu ; 1 ; FF_X80_Y156_N25 ; ; vx_d_e_reg|PC_next_out[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1550: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.801 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 6 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[11] ; +; 6.232 ; 0.632 ; RR ; IC ; 1 ; LABCELL_X97_Y144_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~534|dataf ; +; 6.259 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y144_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~534|combout ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y144_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22]|d ; +; 6.259 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y144_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X97_Y144_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y144_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y144_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1551: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|b_reg_data[30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.212 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.220 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.647 ; 82 ; 0.142 ; 0.929 ; +; Cell ; ; 12 ; 0.448 ; 14 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.212 ; 3.220 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.254 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.183 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; +; 6.212 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; +; 6.212 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; +; 6.212 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1552: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++----------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; To Node ; vx_e_m_reg|alu_result[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.159 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+-------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.087 ; ; ; ; ; ; +; Data Delay ; 3.207 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.325 ; 79 ; 0.000 ; 2.325 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.451 ; 76 ; 0.120 ; 0.864 ; +; Cell ; ; 16 ; 0.574 ; 18 ; 0.000 ; 0.132 ; +; uTco ; ; 1 ; 0.182 ; 6 ; 0.182 ; 0.182 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.952 ; 2.952 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.952 ; 2.325 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; +; 2.952 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; 6.159 ; 3.207 ; ; ; ; ; ; data path ; +; 3.134 ; 0.182 ; FF ; uTco ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|q ; +; 3.178 ; 0.044 ; FF ; CELL ; 4 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE~la_lab/laboutt[10] ; +; 4.042 ; 0.864 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~22|dataf ; +; 4.069 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~22|combout ; +; 4.075 ; 0.006 ; RR ; CELL ; 3 ; MLABCELL_X72_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~22~la_mlab/laboutb[3] ; +; 4.196 ; 0.121 ; RR ; IC ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43|datab ; +; 4.307 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43|combout ; +; 4.313 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X72_Y151_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~43~la_mlab/laboutt[12] ; +; 4.437 ; 0.124 ; FF ; IC ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|datad ; +; 4.527 ; 0.090 ; FR ; CELL ; 1 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46|combout ; +; 4.533 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X72_Y151_N12 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~46~la_mlab/laboutt[8] ; +; 4.653 ; 0.120 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|dataa ; +; 4.785 ; 0.132 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.789 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.222 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.249 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.255 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.385 ; 0.130 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|dataf ; +; 5.412 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|combout ; +; 5.417 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41~la_mlab/laboutb[0] ; +; 6.076 ; 0.659 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|datac ; +; 6.159 ; 0.083 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|combout ; +; 6.159 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|d ; +; 6.159 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N31 ; ; vx_e_m_reg|alu_result[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1553: Setup slack is -0.658 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.658 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.751 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.461 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.537 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.541 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.229 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~826|dataf ; +; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~826|combout ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26]|d ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1554: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.204 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.212 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.683 ; 84 ; 0.115 ; 0.734 ; +; Cell ; ; 14 ; 0.402 ; 13 ; 0.000 ; 0.128 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.204 ; 3.212 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.916 ; 0.734 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|dataf ; +; 3.942 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.946 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.062 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; +; 4.190 ; 0.128 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.196 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.311 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.337 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.342 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.062 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.140 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.146 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.512 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.540 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.544 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.176 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.204 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.204 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.204 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1555: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.711 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 14 ; 0.432 ; 13 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.021 ; 0.713 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|dataf ; +; 6.051 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|combout ; +; 6.057 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35~la_mlab/laboutt[9] ; +; 6.187 ; 0.130 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|datae ; +; 6.263 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1556: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.853 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.233 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|dataf ; +; 6.260 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.165 ; ; uTsu ; 1 ; FF_X108_Y150_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1557: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.249 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.251 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.249 ; 3.251 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.477 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.510 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; +; 6.170 ; 0.660 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~986|datac ; +; 6.249 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~986|combout ; +; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26]|d ; +; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y143_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1558: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.263 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.743 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.261 ; 3.263 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.446 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.473 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.477 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.169 ; 0.692 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~555|datad ; +; 6.261 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X105_Y159_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~555|combout ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11]|d ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1559: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.848 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.304 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.337 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.227 ; 0.890 ; RR ; IC ; 1 ; LABCELL_X104_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~263|dataf ; +; 6.254 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~263|combout ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7]|d ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.163 ; ; uTsu ; 1 ; FF_X104_Y159_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1560: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.234 ; +; Data Required Time ; 5.577 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.058 ; ; ; ; ; ; +; Data Delay ; 3.236 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.770 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.165 ; 79 ; 0.000 ; 2.165 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.234 ; 3.236 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.331 ; 0.454 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|dataf ; +; 5.360 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|combout ; +; 5.364 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29~la_lab/laboutb[14] ; +; 6.208 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|dataf ; +; 6.234 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|combout ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|d ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.440 ; 2.940 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.230 ; 2.165 ; RR ; IC ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|clk ; +; 5.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; +; 5.440 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.410 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.577 ; 0.167 ; ; uTsu ; 1 ; FF_X88_Y164_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1561: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.697 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.431 ; 13 ; 0.000 ; 0.082 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.345 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.425 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.429 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.165 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; +; 6.247 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|d ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1562: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.810 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.443 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.475 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.479 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.230 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|dataf ; +; 6.256 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|combout ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|d ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1563: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.240 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.242 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.795 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.240 ; 3.242 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.532 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.213 ; 0.681 ; RR ; IC ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|dataf ; +; 6.240 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|combout ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|d ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1564: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.257 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.728 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.409 ; 13 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.257 ; 3.259 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.168 ; 0.304 ; FF ; IC ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|dataf ; +; 5.197 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|combout ; +; 5.201 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9~la_lab/laboutb[16] ; +; 6.166 ; 0.965 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|datad ; +; 6.257 ; 0.091 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|combout ; +; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|d ; +; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1565: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.579 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.768 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.348 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.455 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.484 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.490 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; +; 6.209 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|dataf ; +; 6.236 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|combout ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|d ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1566: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[16] ; +; To Node ; vx_e_m_reg|alu_result[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.158 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.083 ; ; ; ; ; ; +; Data Delay ; 3.210 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.536 ; 79 ; 0.111 ; 0.747 ; +; Cell ; ; 16 ; 0.491 ; 15 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.183 ; 6 ; 0.183 ; 0.183 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|clk ; +; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; +; 6.158 ; 3.210 ; ; ; ; ; ; data path ; +; 3.131 ; 0.183 ; FF ; uTco ; 1 ; FF_X79_Y152_N32 ; ; vx_d_e_reg|b_reg_data[16]|q ; +; 3.175 ; 0.044 ; FF ; CELL ; 3 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]~la_lab/laboutb[1] ; +; 3.900 ; 0.725 ; FF ; IC ; 1 ; LABCELL_X75_Y152_N15 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~8|datad ; +; 3.974 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X75_Y152_N15 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~8|combout ; +; 3.978 ; 0.004 ; FF ; CELL ; 5 ; LABCELL_X75_Y152_N15 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~8~la_lab/laboutt[10] ; +; 4.111 ; 0.133 ; FF ; IC ; 1 ; LABCELL_X75_Y152_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~5|dataf ; +; 4.137 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y152_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~5|combout ; +; 4.142 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y152_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~5~la_lab/laboutb[5] ; +; 4.372 ; 0.230 ; FF ; IC ; 1 ; MLABCELL_X74_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~38|datab ; +; 4.480 ; 0.108 ; FF ; CELL ; 1 ; MLABCELL_X74_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~38|combout ; +; 4.486 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X74_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~38~la_mlab/laboutb[17] ; +; 4.597 ; 0.111 ; FF ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datab ; +; 4.723 ; 0.126 ; FR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.727 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.160 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.187 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.193 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.350 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; +; 5.378 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; +; 5.383 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; +; 6.130 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; +; 6.158 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; +; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; +; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1567: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.258 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.771 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.367 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.258 ; 3.260 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.834 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.386 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.413 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.418 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.166 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.258 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; +; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1568: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.814 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.314 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.220 ; 0.620 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|dataf ; +; 6.247 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y147_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~792|combout ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|d ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1569: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|PC_next_out[27] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.077 ; +; Data Required Time ; 5.420 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.079 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.077 ; 3.079 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27]|sclr ; +; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N16 ; High Speed ; vx_d_e_reg|PC_next_out[27] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.420 ; 0.015 ; ; uTsu ; 1 ; FF_X80_Y155_N16 ; ; vx_d_e_reg|PC_next_out[27] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1570: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.749 ; 84 ; 0.110 ; 1.300 ; +; Cell ; ; 12 ; 0.404 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.151 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.272 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1571: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.737 ; 84 ; 0.110 ; 1.275 ; +; Cell ; ; 12 ; 0.400 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.139 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; +; 6.256 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1572: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.749 ; 84 ; 0.110 ; 1.300 ; +; Cell ; ; 12 ; 0.404 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.151 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.272 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; +; 6.272 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1573: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.821 ; 87 ; 0.110 ; 1.372 ; +; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.223 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; +; 6.253 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1574: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.267 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.617 ; 80 ; 0.138 ; 0.748 ; +; Cell ; ; 14 ; 0.533 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.267 ; 3.275 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.002 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.140 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.214 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.219 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.424 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.520 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.525 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.182 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.275 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.280 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.028 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|dataf ; +; 6.054 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32|combout ; +; 6.060 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N57 ; High Speed ; vx_fetch|VX_Warp_one|i199~32~la_mlab/laboutb[18] ; +; 6.207 ; 0.147 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|datae ; +; 6.267 ; 0.060 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N0 ; High Speed ; vx_fetch|VX_Warp_one|i199~43|combout ; +; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|d ; +; 6.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N1 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.167 ; ; uTsu ; 1 ; FF_X69_Y159_N1 ; ; vx_fetch|VX_Warp_one|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1575: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.122 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.124 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.122 ; 3.124 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; +; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N13 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[26]|sload ; +; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N13 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[26] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N13 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[26]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N13 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[26] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.022 ; ; uTsu ; 1 ; FF_X72_Y160_N13 ; ; vx_fetch|VX_Warp_zero|real_PC[26] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1576: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.122 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.124 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.122 ; 3.124 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; +; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N29 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[31]|sload ; +; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N29 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[31] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N29 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[31]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N29 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[31] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.022 ; ; uTsu ; 1 ; FF_X72_Y160_N29 ; ; vx_fetch|VX_Warp_zero|real_PC[31] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1577: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.811 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.701 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.243 ; 0.542 ; RR ; IC ; 1 ; MLABCELL_X96_Y146_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~787|dataf ; +; 6.269 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X96_Y146_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~787|combout ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X96_Y146_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19]|d ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X96_Y146_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X96_Y146_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y146_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.176 ; ; uTsu ; 1 ; FF_X96_Y146_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1578: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.447 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N23 ; High Speed ; vx_d_e_reg|PC_next_out[9]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N23 ; High Speed ; vx_d_e_reg|PC_next_out[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N23 ; High Speed ; vx_d_e_reg|PC_next_out[9]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N23 ; High Speed ; vx_d_e_reg|PC_next_out[9] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.447 ; 0.061 ; ; uTsu ; 1 ; FF_X80_Y156_N23 ; ; vx_d_e_reg|PC_next_out[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1579: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.447 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N13 ; High Speed ; vx_d_e_reg|PC_next_out[6]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N13 ; High Speed ; vx_d_e_reg|PC_next_out[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N13 ; High Speed ; vx_d_e_reg|PC_next_out[6]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N13 ; High Speed ; vx_d_e_reg|PC_next_out[6] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.447 ; 0.061 ; ; uTsu ; 1 ; FF_X80_Y156_N13 ; ; vx_d_e_reg|PC_next_out[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1580: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.447 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N5 ; High Speed ; vx_d_e_reg|PC_next_out[3]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N5 ; High Speed ; vx_d_e_reg|PC_next_out[3] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N5 ; High Speed ; vx_d_e_reg|PC_next_out[3]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N5 ; High Speed ; vx_d_e_reg|PC_next_out[3] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.447 ; 0.061 ; ; uTsu ; 1 ; FF_X80_Y156_N5 ; ; vx_d_e_reg|PC_next_out[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1581: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.122 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.124 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.122 ; 3.124 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; +; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N19 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE|sload ; +; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N19 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N19 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N19 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.022 ; ; uTsu ; 1 ; FF_X72_Y160_N19 ; ; vx_fetch|VX_Warp_zero|real_PC[28]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1582: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|PC_next_out[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.059 ; +; Data Required Time ; 5.402 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.073 ; ; ; ; ; ; +; Data Delay ; 3.067 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.547 ; 83 ; 0.170 ; 0.829 ; +; Cell ; ; 10 ; 0.393 ; 13 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.059 ; 3.067 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.947 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.117 ; 0.170 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.201 ; 0.084 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.206 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.389 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.446 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.451 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.134 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.225 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.230 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.059 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; +; 6.059 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; +; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.402 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1583: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++-----------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------+ +; Property ; Value ; ++--------------------+--------------------------+ +; From Node ; vx_d_e_reg|a_reg_data[9] ; +; To Node ; vx_e_m_reg|alu_result[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.158 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+--------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.211 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.320 ; 79 ; 0.000 ; 2.320 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.480 ; 77 ; 0.130 ; 0.774 ; +; Cell ; ; 16 ; 0.497 ; 15 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.234 ; 7 ; 0.234 ; 0.234 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.947 ; 2.947 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.947 ; 2.320 ; RR ; IC ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]|clk ; +; 2.947 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9] ; +; 6.158 ; 3.211 ; ; ; ; ; ; data path ; +; 3.181 ; 0.234 ; RR ; uTco ; 1 ; FF_X79_Y156_N34 ; ; vx_d_e_reg|a_reg_data[9]|q ; +; 3.245 ; 0.064 ; RR ; CELL ; 15 ; FF_X79_Y156_N34 ; High Speed ; vx_d_e_reg|a_reg_data[9]~la_lab/laboutb[2] ; +; 4.019 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30|datae ; +; 4.092 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30|combout ; +; 4.098 ; 0.006 ; RR ; CELL ; 3 ; MLABCELL_X74_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~30~la_mlab/laboutt[13] ; +; 4.234 ; 0.136 ; RR ; IC ; 1 ; MLABCELL_X74_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~32|datad ; +; 4.323 ; 0.089 ; RF ; CELL ; 1 ; MLABCELL_X74_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~32|combout ; +; 4.329 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X74_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~32~la_mlab/laboutt[1] ; +; 4.460 ; 0.131 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|dataf ; +; 4.488 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; +; 4.492 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; +; 4.709 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; +; 4.784 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.788 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.221 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.248 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.254 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.384 ; 0.130 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|dataf ; +; 5.411 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41|combout ; +; 5.416 ; 0.005 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~41~la_mlab/laboutb[0] ; +; 6.075 ; 0.659 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|datac ; +; 6.158 ; 0.083 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|combout ; +; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|d ; +; 6.158 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N31 ; ; vx_e_m_reg|alu_result[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1584: Setup slack is -0.657 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.657 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.041 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.481 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.508 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.513 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.220 ; 0.707 ; RR ; IC ; 1 ; MLABCELL_X98_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~902|dataf ; +; 6.248 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X98_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~902|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X98_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6]|clk ; +; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y164_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6] ; +; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y164_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1585: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.242 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.637 ; 81 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.486 ; 15 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.242 ; 3.250 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.946 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; +; 4.070 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; +; 4.196 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.317 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.343 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.348 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.068 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.146 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.152 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.436 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.462 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.468 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.180 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.242 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1586: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.204 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.206 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.582 ; 81 ; 0.127 ; 0.657 ; +; Cell ; ; 14 ; 0.502 ; 16 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.204 ; 3.206 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.818 ; 0.654 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datac ; +; 3.902 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.906 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.050 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.130 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.135 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.262 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.383 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.510 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.538 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.542 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.176 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.204 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.204 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.204 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1587: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.205 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.207 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.583 ; 81 ; 0.127 ; 0.657 ; +; Cell ; ; 14 ; 0.502 ; 16 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.205 ; 3.207 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.818 ; 0.654 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datac ; +; 3.902 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.906 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.050 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.130 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.135 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.262 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.383 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.510 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.538 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.542 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.177 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.205 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.205 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.205 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1588: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[24] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.205 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.060 ; ; ; ; ; ; +; Data Delay ; 3.228 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.350 ; 79 ; 0.000 ; 2.350 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.633 ; 82 ; 0.192 ; 0.657 ; +; Cell ; ; 14 ; 0.472 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.977 ; 2.977 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.977 ; 2.350 ; RR ; IC ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]|clk ; +; 2.977 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24] ; +; 6.205 ; 3.228 ; ; ; ; ; ; data path ; +; 3.100 ; 0.123 ; RR ; uTco ; 1 ; FF_X91_Y153_N23 ; ; vx_f_d_reg|instruction[24]|q ; +; 3.189 ; 0.089 ; RR ; CELL ; 138 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]~la_lab/laboutt[15] ; +; 3.767 ; 0.578 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|dataf ; +; 3.794 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.799 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 3.991 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.077 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.082 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.287 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.383 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.510 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.538 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.542 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.177 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.205 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.205 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.205 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1589: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[24] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.204 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.060 ; ; ; ; ; ; +; Data Delay ; 3.227 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.350 ; 79 ; 0.000 ; 2.350 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.632 ; 82 ; 0.192 ; 0.657 ; +; Cell ; ; 14 ; 0.472 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.977 ; 2.977 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.977 ; 2.350 ; RR ; IC ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]|clk ; +; 2.977 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24] ; +; 6.204 ; 3.227 ; ; ; ; ; ; data path ; +; 3.100 ; 0.123 ; RR ; uTco ; 1 ; FF_X91_Y153_N23 ; ; vx_f_d_reg|instruction[24]|q ; +; 3.189 ; 0.089 ; RR ; CELL ; 138 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]~la_lab/laboutt[15] ; +; 3.767 ; 0.578 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|dataf ; +; 3.794 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.799 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 3.991 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.077 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.082 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.287 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.383 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.510 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.538 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.542 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.176 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.204 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.204 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.204 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1590: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.113 ; +; Data Required Time ; 5.457 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.115 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.673 ; 86 ; 0.108 ; 0.787 ; +; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.113 ; 3.115 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.734 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.761 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.767 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.113 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|sload ; +; 6.113 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[4] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.457 ; 0.014 ; ; uTsu ; 1 ; FF_X73_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1591: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.278 ; +; Data Required Time ; 5.622 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.027 ; ; ; ; ; ; +; Data Delay ; 3.280 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.871 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.278 ; 3.280 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.501 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.532 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.536 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.251 ; 0.715 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1017|dataf ; +; 6.278 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1017|combout ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25]|d ; +; 6.278 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; +; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.622 ; 0.181 ; ; uTsu ; 1 ; FF_X107_Y149_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1592: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.848 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.375 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; +; 5.404 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; +; 5.408 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; +; 6.226 ; 0.818 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|dataf ; +; 6.255 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|combout ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]|d ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1593: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.757 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.393 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.443 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.475 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.479 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.177 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|datac ; +; 6.269 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|combout ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|d ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1594: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.257 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.748 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.257 ; 3.259 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.384 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.460 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.464 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.230 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; +; 6.257 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1595: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|csr_address[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.161 ; +; Data Required Time ; 5.505 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.125 ; ; ; ; ; ; +; Data Delay ; 3.163 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.646 ; 84 ; 0.119 ; 0.821 ; +; Cell ; ; 12 ; 0.396 ; 13 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.161 ; 3.163 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.232 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.315 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.320 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.439 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.512 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.516 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.304 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.331 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.336 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.088 ; 0.752 ; RR ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datae ; +; 6.161 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; +; 6.161 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; +; 6.161 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; +; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1596: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|b_reg_data[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.204 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.206 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.618 ; 82 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.467 ; 15 ; 0.000 ; 0.127 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.204 ; 3.206 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.077 ; 0.751 ; FF ; IC ; 1 ; LABCELL_X79_Y151_N6 ; High Speed ; vx_d_e_reg|i385~6|dataa ; +; 6.204 ; 0.127 ; FR ; CELL ; 1 ; LABCELL_X79_Y151_N6 ; High Speed ; vx_d_e_reg|i385~6|combout ; +; 6.204 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|d ; +; 6.204 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1597: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.351 ; 11 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.287 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; +; 5.317 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; +; 5.321 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; +; 6.174 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; +; 6.260 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1598: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.237 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.239 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.775 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.237 ; 3.239 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.404 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.431 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.436 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.210 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; +; 6.237 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; +; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; +; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1599: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++----------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.210 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+-------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.212 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.775 ; 86 ; 0.108 ; 0.910 ; +; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.210 ; 3.212 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.182 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; +; 6.210 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; +; 6.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|d ; +; 6.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N16 ; High Speed ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N16 ; ; vx_d_e_reg|b_reg_data[24]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1600: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|PC_next_out[26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.077 ; +; Data Required Time ; 5.421 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.079 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.077 ; 3.079 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26]|sclr ; +; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N14 ; High Speed ; vx_d_e_reg|PC_next_out[26] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.421 ; 0.016 ; ; uTsu ; 1 ; FF_X80_Y155_N14 ; ; vx_d_e_reg|PC_next_out[26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1601: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_f_d_reg|curr_PC[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.121 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.123 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.726 ; 87 ; 0.119 ; 1.297 ; +; Cell ; ; 10 ; 0.275 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.121 ; 3.123 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.457 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.791 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.819 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.824 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.121 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|ena ; +; 6.121 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N38 ; High Speed ; vx_f_d_reg|curr_PC[7] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N38 ; ; vx_f_d_reg|curr_PC[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1602: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_f_d_reg|curr_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.121 ; +; Data Required Time ; 5.465 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.123 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.726 ; 87 ; 0.119 ; 1.297 ; +; Cell ; ; 10 ; 0.275 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.121 ; 3.123 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.229 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.255 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.260 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.379 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.452 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.457 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.791 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.819 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.824 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.121 ; 1.297 ; FF ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|ena ; +; 6.121 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.465 ; 0.028 ; ; uTsu ; 1 ; FF_X71_Y158_N32 ; ; vx_f_d_reg|curr_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1603: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|b_reg_data[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.210 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.218 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.520 ; 78 ; 0.118 ; 0.940 ; +; Cell ; ; 12 ; 0.572 ; 18 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.210 ; 3.218 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.180 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; +; 6.210 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; +; 6.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; +; 6.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1604: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.262 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.664 ; 81 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.481 ; 15 ; 0.000 ; 0.090 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.262 ; 3.270 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.227 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 5.982 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.009 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.015 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.186 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.262 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1605: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.265 ; +; Data Required Time ; 5.609 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.267 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.604 ; 80 ; 0.123 ; 0.760 ; +; Cell ; ; 14 ; 0.542 ; 17 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.265 ; 3.267 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.048 ; 0.760 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; +; 6.077 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; +; 6.083 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; +; 6.206 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; +; 6.265 ; 0.059 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; +; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; +; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1606: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.122 ; +; Data Required Time ; 5.466 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.124 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.122 ; 3.124 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; +; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N11 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[25]|sload ; +; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N11 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[25] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N11 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[25]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N11 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[25] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.466 ; 0.023 ; ; uTsu ; 1 ; FF_X72_Y160_N11 ; ; vx_fetch|VX_Warp_zero|real_PC[25] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1607: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[27] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.122 ; +; Data Required Time ; 5.466 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.124 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.122 ; 3.124 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; +; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27]|sload ; +; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N17 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[27] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.466 ; 0.023 ; ; uTsu ; 1 ; FF_X72_Y160_N17 ; ; vx_fetch|VX_Warp_zero|real_PC[27] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1608: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[29] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.122 ; +; Data Required Time ; 5.466 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.124 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.122 ; 3.124 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; +; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N23 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[29]|sload ; +; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N23 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[29] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N23 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[29]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N23 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[29] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.466 ; 0.023 ; ; uTsu ; 1 ; FF_X72_Y160_N23 ; ; vx_fetch|VX_Warp_zero|real_PC[29] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1609: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.809 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.554 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.242 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~722|dataf ; +; 6.269 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~722|combout ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18]|d ; +; 6.269 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.167 ; ; uTsu ; 1 ; FF_X104_Y146_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1610: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.122 ; +; Data Required Time ; 5.466 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.124 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 84 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.383 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.122 ; 3.124 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.877 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.904 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.910 ; 0.006 ; FF ; CELL ; 12 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[16] ; +; 6.122 ; 0.212 ; FF ; IC ; 1 ; FF_X72_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[24]|sload ; +; 6.122 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[24] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X72_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[24]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[24] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.466 ; 0.023 ; ; uTsu ; 1 ; FF_X72_Y160_N7 ; ; vx_fetch|VX_Warp_zero|real_PC[24] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1611: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[16] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.448 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N43 ; High Speed ; vx_d_e_reg|PC_next_out[16]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N43 ; High Speed ; vx_d_e_reg|PC_next_out[16] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N43 ; High Speed ; vx_d_e_reg|PC_next_out[16]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N43 ; High Speed ; vx_d_e_reg|PC_next_out[16] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.448 ; 0.062 ; ; uTsu ; 1 ; FF_X80_Y156_N43 ; ; vx_d_e_reg|PC_next_out[16] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1612: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.808 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.241 ; 0.673 ; RR ; IC ; 1 ; LABCELL_X104_Y148_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1010|dataf ; +; 6.268 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y148_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1010|combout ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y148_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18]|d ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y148_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y148_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y148_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.166 ; ; uTsu ; 1 ; FF_X104_Y148_N14 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1613: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.796 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.227 ; 0.630 ; RR ; IC ; 1 ; MLABCELL_X94_Y145_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~984|dataf ; +; 6.254 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y145_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~984|combout ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y145_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24]|d ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y145_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X94_Y145_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y145_N56 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.164 ; ; uTsu ; 1 ; FF_X94_Y145_N56 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][24] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1614: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|PC_next_out[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.074 ; +; Data Required Time ; 5.418 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.079 ; ; ; ; ; ; +; Data Delay ; 3.076 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.507 ; 82 ; 0.192 ; 0.786 ; +; Cell ; ; 10 ; 0.448 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.074 ; 3.076 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.074 ; 0.786 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; +; 6.074 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; +; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.418 ; 0.029 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1615: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|PC_next_out[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.059 ; +; Data Required Time ; 5.403 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.073 ; ; ; ; ; ; +; Data Delay ; 3.067 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.547 ; 83 ; 0.170 ; 0.829 ; +; Cell ; ; 10 ; 0.393 ; 13 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.059 ; 3.067 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.947 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.117 ; 0.170 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.201 ; 0.084 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.206 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.389 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.446 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.451 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.134 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.225 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.230 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.059 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; +; 6.059 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; +; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.403 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1616: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|PC_next_out[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.074 ; +; Data Required Time ; 5.418 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.079 ; ; ; ; ; ; +; Data Delay ; 3.076 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.507 ; 82 ; 0.192 ; 0.786 ; +; Cell ; ; 10 ; 0.448 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.074 ; 3.076 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.074 ; 0.786 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; +; 6.074 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; +; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.418 ; 0.029 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1617: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.242 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.244 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.783 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.340 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.242 ; 3.244 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.542 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; +; 6.215 ; 0.673 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~966|dataf ; +; 6.242 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~966|combout ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6]|d ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.160 ; ; uTsu ; 1 ; FF_X97_Y164_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1618: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.242 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.244 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.668 ; 82 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.455 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.242 ; 3.244 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.494 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.150 ; 0.656 ; RR ; IC ; 1 ; MLABCELL_X94_Y165_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~936|datac ; +; 6.242 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X94_Y165_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~936|combout ; +; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8]|d ; +; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X94_Y165_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y165_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.167 ; ; uTsu ; 1 ; FF_X94_Y165_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1619: Setup slack is -0.656 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.656 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.740 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.491 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.495 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.222 ; 0.727 ; RR ; IC ; 1 ; MLABCELL_X90_Y143_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~892|dataf ; +; 6.248 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y143_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~892|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y143_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y143_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X90_Y143_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y143_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.176 ; ; uTsu ; 1 ; FF_X90_Y143_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1620: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.202 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.204 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.580 ; 81 ; 0.127 ; 0.657 ; +; Cell ; ; 14 ; 0.502 ; 16 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.202 ; 3.204 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.818 ; 0.654 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datac ; +; 3.902 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.906 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.050 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.130 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.135 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.262 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.383 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.510 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.538 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.542 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.174 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.202 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.202 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.202 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1621: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[24] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.202 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.060 ; ; ; ; ; ; +; Data Delay ; 3.225 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.350 ; 79 ; 0.000 ; 2.350 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.630 ; 82 ; 0.192 ; 0.657 ; +; Cell ; ; 14 ; 0.472 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.977 ; 2.977 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.977 ; 2.350 ; RR ; IC ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]|clk ; +; 2.977 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24] ; +; 6.202 ; 3.225 ; ; ; ; ; ; data path ; +; 3.100 ; 0.123 ; RR ; uTco ; 1 ; FF_X91_Y153_N23 ; ; vx_f_d_reg|instruction[24]|q ; +; 3.189 ; 0.089 ; RR ; CELL ; 138 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]~la_lab/laboutt[15] ; +; 3.767 ; 0.578 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|dataf ; +; 3.794 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.799 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 3.991 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.077 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.082 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.287 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.383 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.510 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.538 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.542 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.174 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.202 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.202 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.202 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1622: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.041 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.366 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; +; 5.444 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; +; 5.449 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[11] ; +; 6.217 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y163_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~613|dataf ; +; 6.244 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y163_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~613|combout ; +; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5]|d ; +; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5]|clk ; +; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; +; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.162 ; ; uTsu ; 1 ; FF_X99_Y163_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1623: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.740 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.503 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.169 ; 0.666 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1003|datad ; +; 6.256 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1003|combout ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11]|d ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.163 ; ; uTsu ; 1 ; FF_X107_Y158_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1624: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.790 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.503 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.530 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.535 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.227 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|dataf ; +; 6.254 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|combout ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|d ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1625: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.232 ; +; Data Required Time ; 5.577 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.058 ; ; ; ; ; ; +; Data Delay ; 3.234 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.324 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.165 ; 79 ; 0.000 ; 2.165 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.232 ; 3.234 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.329 ; 0.454 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|dataf ; +; 5.358 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|combout ; +; 5.362 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29~la_lab/laboutb[14] ; +; 6.206 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|dataf ; +; 6.232 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|combout ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|d ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.440 ; 2.940 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.230 ; 2.165 ; RR ; IC ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|clk ; +; 5.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; +; 5.440 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.410 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.577 ; 0.167 ; ; uTsu ; 1 ; FF_X88_Y164_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1626: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.237 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.239 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.771 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.237 ; 3.239 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.449 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.481 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.486 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; +; 6.210 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; +; 6.237 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; +; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; +; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1627: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.785 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.437 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.464 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.469 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.219 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; +; 6.246 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1628: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.747 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.166 ; 0.304 ; FF ; IC ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|dataf ; +; 5.195 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|combout ; +; 5.199 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9~la_lab/laboutb[16] ; +; 6.164 ; 0.965 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|datad ; +; 6.255 ; 0.091 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|combout ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|d ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1629: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.234 ; +; Data Required Time ; 5.579 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.236 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.787 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.328 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.234 ; 3.236 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.453 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.482 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.488 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; +; 6.207 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|dataf ; +; 6.234 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|combout ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|d ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1630: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.736 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.405 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.443 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.472 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.477 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.173 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; +; 6.260 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1631: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.253 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.781 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.350 ; 11 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.251 ; 3.253 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.375 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.452 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.456 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.224 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; +; 6.251 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1632: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.804 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.410 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.437 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.443 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.209 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|dataf ; +; 6.236 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~745|combout ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|d ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1633: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.257 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.827 ; 87 ; 0.116 ; 1.094 ; +; Cell ; ; 14 ; 0.311 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.257 ; 3.259 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.467 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.493 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.499 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.231 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|dataf ; +; 6.257 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X92_Y144_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~892|combout ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|d ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y144_N41 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.176 ; ; uTsu ; 1 ; FF_X92_Y144_N41 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1634: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.239 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.241 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.849 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.272 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.239 ; 3.241 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.431 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.459 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.464 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.211 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|dataf ; +; 6.239 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~975|combout ; +; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|d ; +; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y164_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1635: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|b_reg_data[24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.210 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.212 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.775 ; 86 ; 0.108 ; 0.910 ; +; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.210 ; 3.212 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.182 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|dataf ; +; 6.210 ; 0.028 ; FR ; CELL ; 2 ; LABCELL_X79_Y149_N15 ; High Speed ; vx_d_e_reg|i385~75|combout ; +; 6.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|d ; +; 6.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N17 ; High Speed ; vx_d_e_reg|b_reg_data[24] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N17 ; ; vx_d_e_reg|b_reg_data[24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1636: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.779 ; 86 ; 0.114 ; 1.228 ; +; Cell ; ; 12 ; 0.345 ; 11 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.124 ; 1.228 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~79|datab ; +; 6.244 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~79|combout ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15]|d ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.168 ; ; uTsu ; 1 ; FF_X92_Y163_N1 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1637: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.737 ; 84 ; 0.110 ; 1.275 ; +; Cell ; ; 12 ; 0.403 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.139 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.259 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1638: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.263 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.770 ; 85 ; 0.116 ; 1.302 ; +; Cell ; ; 12 ; 0.372 ; 11 ; 0.000 ; 0.119 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.261 ; 3.263 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.810 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.835 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.840 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.142 ; 1.302 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|datab ; +; 6.261 ; 0.119 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~718|combout ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|d ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.169 ; ; uTsu ; 1 ; FF_X103_Y161_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[22][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1639: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.609 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.619 ; 80 ; 0.123 ; 0.760 ; +; Cell ; ; 14 ; 0.526 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.264 ; 3.272 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.287 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.047 ; 0.760 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; +; 6.076 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; +; 6.082 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; +; 6.205 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; +; 6.264 ; 0.059 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; +; 6.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1640: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.449 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N47 ; High Speed ; vx_d_e_reg|PC_next_out[17]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N47 ; High Speed ; vx_d_e_reg|PC_next_out[17] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N47 ; High Speed ; vx_d_e_reg|PC_next_out[17]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N47 ; High Speed ; vx_d_e_reg|PC_next_out[17] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.449 ; 0.063 ; ; uTsu ; 1 ; FF_X80_Y156_N47 ; ; vx_d_e_reg|PC_next_out[17] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1641: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.778 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.228 ; 0.705 ; FF ; IC ; 1 ; LABCELL_X102_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~738|dataf ; +; 6.256 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X102_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~738|combout ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2]|d ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X102_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y160_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][2] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1642: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.273 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.748 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.273 ; 3.275 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.398 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; +; 5.427 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; +; 5.432 ; 0.005 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[7] ; +; 6.180 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X103_Y145_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~658|datac ; +; 6.273 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X103_Y145_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~658|combout ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18]|d ; +; 6.273 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X103_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y145_N52 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y145_N52 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1643: Setup slack is -0.655 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.655 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.747 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.408 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.488 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.492 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.229 ; 0.737 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~842|dataf ; +; 6.255 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X107_Y157_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~842|combout ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE|d ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y157_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1644: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_d_e_reg|rd[1] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.537 ; 78 ; 0.118 ; 0.708 ; +; Cell ; ; 14 ; 0.596 ; 18 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N10 ; ; vx_d_e_reg|rd[1]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]~la_lab/laboutt[6] ; +; 3.760 ; 0.596 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|datad ; +; 3.849 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.855 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.007 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.137 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.142 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.260 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.371 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.376 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.059 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.150 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.156 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.864 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.892 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.898 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.178 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.253 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1645: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.136 ; +; Data Required Time ; 5.482 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.138 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.136 ; 3.138 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|sload ; +; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.482 ; 0.035 ; ; uTsu ; 1 ; FF_X71_Y161_N5 ; ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1646: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.136 ; +; Data Required Time ; 5.482 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.138 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.136 ; 3.138 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|sload ; +; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.482 ; 0.035 ; ; uTsu ; 1 ; FF_X71_Y161_N4 ; ; vx_fetch|VX_Warp_zero|real_PC[14] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1647: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.136 ; +; Data Required Time ; 5.482 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.138 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.136 ; 3.138 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|sload ; +; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.482 ; 0.035 ; ; uTsu ; 1 ; FF_X71_Y161_N10 ; ; vx_fetch|VX_Warp_zero|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1648: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.208 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.076 ; ; ; ; ; ; +; Data Delay ; 3.210 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.801 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.147 ; 79 ; 0.000 ; 2.147 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.208 ; 3.210 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.345 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; +; 5.375 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; +; 5.379 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; +; 6.181 ; 0.802 ; RR ; IC ; 1 ; LABCELL_X83_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~488|dataf ; +; 6.208 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X83_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~488|combout ; +; 6.208 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8]|d ; +; 6.208 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.422 ; 2.922 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.212 ; 2.147 ; RR ; IC ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8]|clk ; +; 5.212 ; 0.000 ; RR ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; +; 5.422 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.392 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.162 ; ; uTsu ; 1 ; FF_X83_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1649: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.242 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.244 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.834 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.242 ; 3.244 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.214 ; 0.703 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~687|dataf ; +; 6.242 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~687|combout ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15]|d ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.167 ; ; uTsu ; 1 ; FF_X92_Y163_N13 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1650: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.240 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.242 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.733 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.240 ; 3.242 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.371 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.451 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.455 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.212 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X95_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~870|dataf ; +; 6.240 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X95_Y163_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~870|combout ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6]|d ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y163_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.163 ; ; uTsu ; 1 ; FF_X95_Y163_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1651: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|b_reg_data[19] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.208 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.210 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.773 ; 86 ; 0.108 ; 0.908 ; +; Cell ; ; 12 ; 0.315 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.208 ; 3.210 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.180 ; 0.908 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|dataf ; +; 6.208 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N21 ; High Speed ; vx_d_e_reg|i385~60|combout ; +; 6.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|d ; +; 6.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N22 ; High Speed ; vx_d_e_reg|b_reg_data[19] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N22 ; ; vx_d_e_reg|b_reg_data[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1652: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|b_reg_data[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.209 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.217 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.689 ; 84 ; 0.128 ; 0.944 ; +; Cell ; ; 12 ; 0.403 ; 13 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.209 ; 3.217 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.236 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.180 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; +; 6.209 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; +; 6.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; +; 6.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1653: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|b_reg_data[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.209 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.217 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.688 ; 84 ; 0.128 ; 0.943 ; +; Cell ; ; 12 ; 0.404 ; 13 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.209 ; 3.217 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.236 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.179 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; +; 6.209 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; +; 6.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; +; 6.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1654: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.262 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.664 ; 81 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.481 ; 15 ; 0.000 ; 0.090 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.262 ; 3.270 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.227 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 5.982 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 6.009 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.015 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.186 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.262 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|d ; +; 6.262 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y159_N49 ; ; vx_fetch|VX_Warp_three|real_PC[9]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1655: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.749 ; 84 ; 0.110 ; 1.300 ; +; Cell ; ; 12 ; 0.401 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.151 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|datab ; +; 6.269 ; 0.118 ; FR ; CELL ; 1 ; MLABCELL_X103_Y160_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~578|combout ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|d ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N46 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N46 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1656: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|PC_next_out[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.056 ; +; Data Required Time ; 5.402 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.073 ; ; ; ; ; ; +; Data Delay ; 3.064 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.567 ; 84 ; 0.115 ; 0.829 ; +; Cell ; ; 10 ; 0.372 ; 12 ; 0.000 ; 0.090 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.056 ; 3.064 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.227 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.056 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|sclr ; +; 6.056 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N23 ; High Speed ; vx_d_e_reg|PC_next_out[0] ; +; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.402 ; 0.013 ; ; uTsu ; 1 ; FF_X81_Y155_N23 ; ; vx_d_e_reg|PC_next_out[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1657: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[7] ; +; To Node ; vx_e_m_reg|alu_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.013 ; ; ; ; ; ; +; Data Delay ; 3.275 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.366 ; 79 ; 0.000 ; 2.366 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.703 ; 83 ; 0.113 ; 1.025 ; +; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.993 ; 2.993 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.993 ; 2.366 ; RR ; IC ; 1 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7]|clk ; +; 2.993 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7] ; +; 6.268 ; 3.275 ; ; ; ; ; ; data path ; +; 3.116 ; 0.123 ; RR ; uTco ; 1 ; FF_X51_Y160_N17 ; ; vx_csr_handler|decode_csr_address[7]|q ; +; 3.212 ; 0.096 ; RR ; CELL ; 224 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7]~la_lab/laboutt[11] ; +; 4.237 ; 1.025 ; RR ; IC ; 1 ; MLABCELL_X39_Y145_N3 ; High Speed ; vx_csr_handler|Mux_3~174|datac ; +; 4.330 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X39_Y145_N3 ; High Speed ; vx_csr_handler|Mux_3~174|combout ; +; 4.336 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X39_Y145_N3 ; High Speed ; vx_csr_handler|Mux_3~174~la_mlab/laboutt[3] ; +; 4.481 ; 0.145 ; RR ; IC ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|datae ; +; 4.556 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|combout ; +; 4.561 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190~la_lab/laboutb[9] ; +; 5.077 ; 0.516 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|dataf ; +; 5.103 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; +; 5.107 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; +; 5.234 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; +; 5.317 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.321 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.098 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.124 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.129 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.242 ; 0.113 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|dataf ; +; 6.268 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N24 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~36|combout ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|d ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N25 ; High Speed ; vx_e_m_reg|alu_result[4] ; +; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; +; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.164 ; ; uTsu ; 1 ; FF_X58_Y153_N25 ; ; vx_e_m_reg|alu_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1658: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.450 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N59 ; High Speed ; vx_d_e_reg|PC_next_out[21]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N59 ; High Speed ; vx_d_e_reg|PC_next_out[21] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N59 ; High Speed ; vx_d_e_reg|PC_next_out[21]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N59 ; High Speed ; vx_d_e_reg|PC_next_out[21] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.450 ; 0.064 ; ; uTsu ; 1 ; FF_X80_Y156_N59 ; ; vx_d_e_reg|PC_next_out[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1659: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.266 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.268 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.788 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.266 ; 3.268 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.400 ; 0.483 ; RR ; IC ; 1 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|dataf ; +; 5.428 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16|combout ; +; 5.432 ; 0.004 ; FF ; CELL ; 14 ; LABCELL_X97_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~16~la_lab/laboutb[6] ; +; 6.237 ; 0.805 ; FF ; IC ; 1 ; MLABCELL_X96_Y163_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~517|dataf ; +; 6.266 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X96_Y163_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~517|combout ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y163_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5]|d ; +; 6.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y163_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X96_Y163_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y163_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.182 ; ; uTsu ; 1 ; FF_X96_Y163_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[16][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1660: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.450 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N55 ; High Speed ; vx_d_e_reg|PC_next_out[20]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N55 ; High Speed ; vx_d_e_reg|PC_next_out[20] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N55 ; High Speed ; vx_d_e_reg|PC_next_out[20]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N55 ; High Speed ; vx_d_e_reg|PC_next_out[20] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.450 ; 0.064 ; ; uTsu ; 1 ; FF_X80_Y156_N55 ; ; vx_d_e_reg|PC_next_out[20] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1661: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[19] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.450 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N53 ; High Speed ; vx_d_e_reg|PC_next_out[19]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N53 ; High Speed ; vx_d_e_reg|PC_next_out[19] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N53 ; High Speed ; vx_d_e_reg|PC_next_out[19]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N53 ; High Speed ; vx_d_e_reg|PC_next_out[19] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.450 ; 0.064 ; ; uTsu ; 1 ; FF_X80_Y156_N53 ; ; vx_d_e_reg|PC_next_out[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1662: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.450 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N41 ; High Speed ; vx_d_e_reg|PC_next_out[15]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N41 ; High Speed ; vx_d_e_reg|PC_next_out[15] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N41 ; High Speed ; vx_d_e_reg|PC_next_out[15]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N41 ; High Speed ; vx_d_e_reg|PC_next_out[15] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.450 ; 0.064 ; ; uTsu ; 1 ; FF_X80_Y156_N41 ; ; vx_d_e_reg|PC_next_out[15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1663: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|PC_next_out[13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.104 ; +; Data Required Time ; 5.450 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.106 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.635 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 10 ; 0.350 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.104 ; 3.106 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.689 ; FF ; IC ; 1 ; FF_X80_Y156_N35 ; High Speed ; vx_d_e_reg|PC_next_out[13]|sclr ; +; 6.104 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y156_N35 ; High Speed ; vx_d_e_reg|PC_next_out[13] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X80_Y156_N35 ; High Speed ; vx_d_e_reg|PC_next_out[13]|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y156_N35 ; High Speed ; vx_d_e_reg|PC_next_out[13] ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.450 ; 0.064 ; ; uTsu ; 1 ; FF_X80_Y156_N35 ; ; vx_d_e_reg|PC_next_out[13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1664: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[19] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.289 ; +; Data Required Time ; 5.635 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.091 ; ; ; ; ; ; +; Data Delay ; 2.234 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.312 ; 76 ; 0.000 ; 2.312 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.859 ; 83 ; 0.392 ; 0.786 ; +; Cell ; ; 8 ; 0.243 ; 11 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.132 ; 6 ; 0.132 ; 0.132 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.055 ; 3.055 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.055 ; 2.312 ; FF ; IC ; 1 ; FF_X90_Y148_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19]|clk ; +; 4.055 ; 0.000 ; FR ; CELL ; 1 ; FF_X90_Y148_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19] ; +; 6.289 ; 2.234 ; ; ; ; ; ; data path ; +; 4.187 ; 0.132 ; FF ; uTco ; 1 ; FF_X90_Y148_N56 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19]|q ; +; 4.230 ; 0.043 ; FF ; CELL ; 1 ; FF_X90_Y148_N56 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[19]~la_mlab/laboutb[17] ; +; 4.911 ; 0.681 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|datad ; +; 4.989 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; +; 4.994 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; +; 5.780 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; +; 5.806 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; +; 5.811 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; +; 6.203 ; 0.392 ; FF ; IC ; 1 ; MLABCELL_X74_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_one|i199~14|datae ; +; 6.289 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X74_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_one|i199~14|combout ; +; 6.289 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19]|d ; +; 6.289 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19] ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19] ; +; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.635 ; 0.201 ; ; uTsu ; 1 ; FF_X74_Y159_N40 ; ; vx_fetch|VX_Warp_one|real_PC[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1665: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[19] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.288 ; +; Data Required Time ; 5.634 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.095 ; ; ; ; ; ; +; Data Delay ; 2.229 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.316 ; 76 ; 0.000 ; 2.316 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.864 ; 84 ; 0.370 ; 0.786 ; +; Cell ; ; 8 ; 0.226 ; 10 ; 0.000 ; 0.069 ; +; uTco ; ; 1 ; 0.139 ; 6 ; 0.139 ; 0.139 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.059 ; 3.059 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.059 ; 2.316 ; FF ; IC ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]|clk ; +; 4.059 ; 0.000 ; FR ; CELL ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19] ; +; 6.288 ; 2.229 ; ; ; ; ; ; data path ; +; 4.198 ; 0.139 ; FF ; uTco ; 1 ; FF_X90_Y146_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]|q ; +; 4.267 ; 0.069 ; FF ; CELL ; 1 ; FF_X90_Y146_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|out_src1_data[19]~la_mlab/laboutt[15] ; +; 4.975 ; 0.708 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|datae ; +; 5.037 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; +; 5.042 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; +; 5.828 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; +; 5.854 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; +; 5.859 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; +; 6.229 ; 0.370 ; FF ; IC ; 1 ; MLABCELL_X74_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~16|datae ; +; 6.288 ; 0.059 ; FF ; CELL ; 1 ; MLABCELL_X74_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_three|i199~16|combout ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[19]|d ; +; 6.288 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[19] ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X74_Y159_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[19]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y159_N14 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[19] ; +; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.634 ; 0.200 ; ; uTsu ; 1 ; FF_X74_Y159_N14 ; ; vx_fetch|VX_Warp_three|real_PC[19] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1666: Setup slack is -0.654 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[14] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[14] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.295 ; +; Data Required Time ; 5.641 ; +; Slack ; -0.654 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.095 ; ; ; ; ; ; +; Data Delay ; 2.235 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.317 ; 76 ; 0.000 ; 2.317 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.845 ; 83 ; 0.366 ; 0.887 ; +; Cell ; ; 8 ; 0.257 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.060 ; 3.060 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.060 ; 2.317 ; FF ; IC ; 1 ; FF_X98_Y162_N8 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[14]|clk ; +; 4.060 ; 0.000 ; FR ; CELL ; 1 ; FF_X98_Y162_N8 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[14] ; +; 6.295 ; 2.235 ; ; ; ; ; ; data path ; +; 4.193 ; 0.133 ; FF ; uTco ; 1 ; FF_X98_Y162_N8 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[14]|q ; +; 4.236 ; 0.043 ; FF ; CELL ; 1 ; FF_X98_Y162_N8 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[14]~la_mlab/laboutt[5] ; +; 5.123 ; 0.887 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N51 ; High Speed ; vx_decode|out_a_reg_data[0]~33|datad ; +; 5.208 ; 0.085 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N51 ; High Speed ; vx_decode|out_a_reg_data[0]~33|combout ; +; 5.212 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N51 ; High Speed ; vx_decode|out_a_reg_data[0]~33~la_lab/laboutb[14] ; +; 5.804 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N51 ; High Speed ; vx_decode|out_a_reg_data[0]~34|dataf ; +; 5.832 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X75_Y154_N51 ; High Speed ; vx_decode|out_a_reg_data[0]~34|combout ; +; 5.837 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X75_Y154_N51 ; High Speed ; vx_decode|out_a_reg_data[0]~34~la_lab/laboutb[15] ; +; 6.203 ; 0.366 ; FF ; IC ; 1 ; MLABCELL_X74_Y160_N42 ; High Speed ; vx_fetch|VX_Warp_one|i199~9|datad ; +; 6.295 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X74_Y160_N42 ; High Speed ; vx_fetch|VX_Warp_one|i199~9|combout ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N43 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[14]|d ; +; 6.295 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N43 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[14] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X74_Y160_N43 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[14]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y160_N43 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[14] ; +; 5.465 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.641 ; 0.206 ; ; uTsu ; 1 ; FF_X74_Y160_N43 ; ; vx_fetch|VX_Warp_one|real_PC[14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1667: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.201 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.209 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.681 ; 84 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.403 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.201 ; 3.209 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.895 ; 0.710 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.018 ; 0.123 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.024 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.160 ; 0.136 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataf ; +; 4.185 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.191 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.306 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.332 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.337 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.057 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.135 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.141 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.507 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.535 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.539 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.173 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.201 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1668: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.202 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.210 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.682 ; 84 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.403 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.202 ; 3.210 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.895 ; 0.710 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.018 ; 0.123 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.024 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.160 ; 0.136 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataf ; +; 4.185 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.191 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.306 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.332 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.337 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.057 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.135 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.141 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.507 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.535 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.539 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.174 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.202 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.202 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.202 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1669: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.136 ; +; Data Required Time ; 5.483 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.138 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.136 ; 3.138 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|sload ; +; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.483 ; 0.036 ; ; uTsu ; 1 ; FF_X71_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[20] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1670: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.136 ; +; Data Required Time ; 5.483 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.138 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.136 ; 3.138 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|sload ; +; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.483 ; 0.036 ; ; uTsu ; 1 ; FF_X71_Y161_N44 ; ; vx_fetch|VX_Warp_zero|real_PC[17] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1671: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[16] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.136 ; +; Data Required Time ; 5.483 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.138 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.136 ; 3.138 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|sload ; +; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.483 ; 0.036 ; ; uTsu ; 1 ; FF_X71_Y161_N32 ; ; vx_fetch|VX_Warp_zero|real_PC[16] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1672: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.136 ; +; Data Required Time ; 5.483 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.138 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.698 ; 86 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.136 ; 3.138 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.330 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.782 ; 0.452 ; RR ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.807 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.813 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.136 ; 0.323 ; RR ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|sload ; +; 6.136 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.483 ; 0.036 ; ; uTsu ; 1 ; FF_X71_Y161_N14 ; ; vx_fetch|VX_Warp_zero|real_PC[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1673: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[12] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.113 ; +; Data Required Time ; 5.460 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.115 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.673 ; 86 ; 0.108 ; 0.787 ; +; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.113 ; 3.115 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.734 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.761 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.767 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.113 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|sload ; +; 6.113 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N46 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[12] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.460 ; 0.017 ; ; uTsu ; 1 ; FF_X73_Y161_N46 ; ; vx_fetch|VX_Warp_zero|real_PC[12] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1674: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.258 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.852 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.258 ; 3.260 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.230 ; 0.665 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|dataf ; +; 6.258 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|combout ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE|d ; +; 6.258 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y150_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1675: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.235 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.048 ; ; ; ; ; ; +; Data Delay ; 3.237 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.831 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.284 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.235 ; 3.237 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.454 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.481 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.485 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.207 ; 0.722 ; RR ; IC ; 1 ; MLABCELL_X92_Y160_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~561|dataf ; +; 6.235 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y160_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~561|combout ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17]|d ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17]|clk ; +; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; +; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.162 ; ; uTsu ; 1 ; FF_X92_Y160_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1676: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.727 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.474 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.501 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.506 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.154 ; 0.648 ; RR ; IC ; 1 ; LABCELL_X93_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~845|datac ; +; 6.236 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X93_Y160_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~845|combout ; +; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13]|d ; +; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y160_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.162 ; ; uTsu ; 1 ; FF_X93_Y160_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][13] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1677: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.809 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.324 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.501 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.528 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.533 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.225 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|dataf ; +; 6.252 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|combout ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|d ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1678: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.799 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.404 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.431 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.437 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.235 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|dataf ; +; 6.263 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~914|combout ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|d ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.164 ; ; uTsu ; 1 ; FF_X104_Y146_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1679: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.611 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.799 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.431 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.462 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.466 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.236 ; 0.770 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|dataf ; +; 6.264 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X104_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~690|combout ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|d ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1680: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.730 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.521 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.166 ; 0.645 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|datad ; +; 6.253 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~971|combout ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|d ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1681: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.784 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.624 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.220 ; 0.596 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|dataf ; +; 6.247 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~799|combout ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|d ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N26 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X98_Y143_N26 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1682: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.253 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.787 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.251 ; 3.253 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.443 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.472 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.477 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.224 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|dataf ; +; 6.251 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y142_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~726|combout ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|d ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y142_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y142_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1683: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.755 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.378 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.380 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.407 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.412 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.160 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.252 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|d ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y163_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1684: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.249 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.251 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.815 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.315 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.249 ; 3.251 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.409 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.436 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.442 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.221 ; 0.779 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|dataf ; +; 6.249 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1023|combout ; +; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|d ; +; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1685: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.786 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.079 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.429 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.458 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.463 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.169 ; 0.706 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; +; 6.248 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; +; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; +; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1686: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_d_e_reg|b_reg_data[31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.206 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.208 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.770 ; 86 ; 0.108 ; 0.905 ; +; Cell ; ; 12 ; 0.316 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.206 ; 3.208 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.177 ; 0.905 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|dataf ; +; 6.206 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N24 ; High Speed ; vx_d_e_reg|i385~96|combout ; +; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|d ; +; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N25 ; High Speed ; vx_d_e_reg|b_reg_data[31] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N25 ; ; vx_d_e_reg|b_reg_data[31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1687: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|PC_next_out[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.056 ; +; Data Required Time ; 5.403 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.073 ; ; ; ; ; ; +; Data Delay ; 3.064 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.567 ; 84 ; 0.115 ; 0.829 ; +; Cell ; ; 10 ; 0.372 ; 12 ; 0.000 ; 0.090 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.056 ; 3.064 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.227 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.056 ; 0.829 ; FF ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|sclr ; +; 6.056 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.419 ; 2.919 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N55 ; High Speed ; vx_d_e_reg|PC_next_out[1] ; +; 5.419 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.389 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.403 ; 0.014 ; ; uTsu ; 1 ; FF_X81_Y155_N55 ; ; vx_d_e_reg|PC_next_out[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1688: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.725 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.407 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; +; 5.436 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; +; 5.440 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; +; 6.156 ; 0.716 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|datad ; +; 6.248 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; +; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1689: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.744 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.175 ; 0.578 ; RR ; IC ; 1 ; LABCELL_X102_Y147_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~981|datad ; +; 6.255 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X102_Y147_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~981|combout ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y147_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21]|d ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y147_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y147_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y147_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y147_N13 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][21] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1690: Setup slack is -0.653 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|warp_num[1]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.206 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.653 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.208 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.644 ; 82 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.443 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.206 ; 3.208 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.113 ; 0.698 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N27 ; High Speed ; vx_d_e_reg|i602~1|datac ; +; 6.206 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X80_Y153_N27 ; High Speed ; vx_d_e_reg|i602~1|combout ; +; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N28 ; High Speed ; vx_d_e_reg|warp_num[1]~DUPLICATE|d ; +; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N28 ; High Speed ; vx_d_e_reg|warp_num[1]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X80_Y153_N28 ; High Speed ; vx_d_e_reg|warp_num[1]~DUPLICATE|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N28 ; High Speed ; vx_d_e_reg|warp_num[1]~DUPLICATE ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.165 ; ; uTsu ; 1 ; FF_X80_Y153_N28 ; ; vx_d_e_reg|warp_num[1]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1691: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.704 ; 83 ; 0.125 ; 0.708 ; +; Cell ; ; 14 ; 0.428 ; 13 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.251 ; 3.259 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.734 ; 0.552 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|dataf ; +; 3.762 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; +; 3.767 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; +; 3.892 ; 0.125 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; +; 3.918 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.923 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.279 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.369 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.374 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.057 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.148 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.154 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.862 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.890 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.896 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.176 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.251 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1692: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.199 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.207 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.679 ; 84 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.403 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.199 ; 3.207 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.895 ; 0.710 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.018 ; 0.123 ; FR ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.024 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.160 ; 0.136 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataf ; +; 4.185 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.191 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.306 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.332 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.337 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.057 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.135 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.141 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.507 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.535 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.539 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.171 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.199 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.199 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.199 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1693: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++----------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------+ +; Property ; Value ; ++--------------------+-------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.239 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+-------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.241 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.630 ; 81 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.490 ; 15 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.239 ; 3.241 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; +; 4.064 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; +; 4.170 ; 0.106 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.176 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.291 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.317 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.322 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.085 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.163 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.169 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.445 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.471 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.477 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.165 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.239 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1694: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.640 ; 81 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.495 ; 15 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; +; 4.064 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; +; 4.170 ; 0.106 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.176 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.291 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.317 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.322 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.085 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.163 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.169 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.883 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.913 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.919 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.179 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.254 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1695: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.239 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.547 ; 78 ; 0.116 ; 0.686 ; +; Cell ; ; 14 ; 0.575 ; 18 ; 0.000 ; 0.114 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.239 ; 3.247 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; +; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.501 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.527 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.533 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.132 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.239 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1696: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.113 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.115 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.673 ; 86 ; 0.108 ; 0.787 ; +; Cell ; ; 12 ; 0.320 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.113 ; 3.115 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.181 ; 0.061 ; RR ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.400 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.480 ; 0.080 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.485 ; 0.005 ; FF ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.272 ; 0.787 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.299 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.304 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.412 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.485 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.489 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.240 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.266 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.272 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.734 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.761 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.767 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.113 ; 0.346 ; FF ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|sload ; +; 6.113 ; 0.000 ; FF ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X73_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[10] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.018 ; ; uTsu ; 1 ; FF_X73_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1697: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.253 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.729 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.251 ; 3.253 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.378 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.458 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.462 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.158 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|datad ; +; 6.251 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|combout ; +; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]|d ; +; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N50 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1698: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.235 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.237 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.777 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.235 ; 3.237 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.486 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.518 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.522 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; +; 6.208 ; 0.686 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~585|dataf ; +; 6.235 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~585|combout ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9]|d ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.167 ; ; uTsu ; 1 ; FF_X89_Y160_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1699: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.737 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.469 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.496 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.502 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; +; 6.166 ; 0.664 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~971|datad ; +; 6.252 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~971|combout ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11]|d ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1700: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.229 ; +; Data Required Time ; 5.577 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.231 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.762 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.229 ; 3.231 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.446 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.473 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.479 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.201 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|dataf ; +; 6.229 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|combout ; +; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|d ; +; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.577 ; 0.163 ; ; uTsu ; 1 ; FF_X93_Y162_N53 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1701: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.239 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.413 ; 74 ; 0.118 ; 0.683 ; +; Cell ; ; 14 ; 0.708 ; 22 ; 0.000 ; 0.134 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.239 ; 3.247 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.516 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.542 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.548 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.105 ; 0.557 ; RR ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.239 ; 0.134 ; RR ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1702: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.253 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.788 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.251 ; 3.253 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.223 ; 0.600 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|dataf ; +; 6.251 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~793|combout ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|d ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1703: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.257 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.849 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.257 ; 3.259 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.577 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.605 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.610 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.230 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; +; 6.257 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1704: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.233 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.235 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.772 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.233 ; 3.235 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.347 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; +; 5.427 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; +; 5.432 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; +; 6.205 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; +; 6.233 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; +; 6.233 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; +; 6.233 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1705: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[14] ; +; To Node ; vx_e_m_reg|alu_result[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.153 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.083 ; ; ; ; ; ; +; Data Delay ; 3.205 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.484 ; 78 ; 0.115 ; 0.747 ; +; Cell ; ; 16 ; 0.546 ; 17 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.175 ; 5 ; 0.175 ; 0.175 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14]|clk ; +; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14] ; +; 6.153 ; 3.205 ; ; ; ; ; ; data path ; +; 3.123 ; 0.175 ; FF ; uTco ; 1 ; FF_X79_Y152_N19 ; ; vx_d_e_reg|b_reg_data[14]|q ; +; 3.191 ; 0.068 ; FF ; CELL ; 3 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14]~la_lab/laboutt[12] ; +; 3.866 ; 0.675 ; FF ; IC ; 1 ; LABCELL_X75_Y152_N6 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~10|datad ; +; 3.939 ; 0.073 ; FF ; CELL ; 2 ; LABCELL_X75_Y152_N6 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~10|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X75_Y152_N6 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~10~la_lab/laboutt[5] ; +; 4.100 ; 0.156 ; FF ; IC ; 1 ; MLABCELL_X74_Y152_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~16|datac ; +; 4.187 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X74_Y152_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~16|combout ; +; 4.192 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X74_Y152_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~16~la_mlab/laboutb[12] ; +; 4.393 ; 0.201 ; FF ; IC ; 1 ; MLABCELL_X74_Y151_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~19|datab ; +; 4.514 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X74_Y151_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~19|combout ; +; 4.520 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X74_Y151_N36 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~19~la_mlab/laboutb[5] ; +; 4.635 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datac ; +; 4.718 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.722 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.155 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.182 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.188 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.345 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; +; 5.373 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; +; 5.378 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; +; 6.125 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; +; 6.153 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; +; 6.153 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; +; 6.153 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1706: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.264 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.266 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.832 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.313 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.264 ; 3.266 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.566 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.594 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.600 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[9] ; +; 6.238 ; 0.638 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|dataf ; +; 6.264 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~786|combout ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|d ; +; 6.264 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1707: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|PC_next_out[30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.077 ; +; Data Required Time ; 5.425 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.079 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.077 ; 3.079 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30]|sclr ; +; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N25 ; High Speed ; vx_d_e_reg|PC_next_out[30] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.425 ; 0.020 ; ; uTsu ; 1 ; FF_X80_Y155_N25 ; ; vx_d_e_reg|PC_next_out[30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1708: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|b_reg_data[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.206 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.214 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.685 ; 84 ; 0.128 ; 0.940 ; +; Cell ; ; 12 ; 0.404 ; 13 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.206 ; 3.214 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.236 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.176 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; +; 6.206 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; +; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; +; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1709: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.779 ; 86 ; 0.114 ; 1.228 ; +; Cell ; ; 12 ; 0.342 ; 11 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.124 ; 1.228 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~47|datab ; +; 6.241 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~47|combout ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15]|d ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.168 ; ; uTsu ; 1 ; FF_X92_Y163_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1710: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.881 ; 89 ; 0.127 ; 1.317 ; +; Cell ; ; 12 ; 0.251 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.226 ; 1.317 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~363|dataf ; +; 6.252 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~363|combout ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11]|d ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1711: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.737 ; 84 ; 0.110 ; 1.275 ; +; Cell ; ; 12 ; 0.400 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.139 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; +; 6.256 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|d ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N11 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N11 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1712: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.868 ; 88 ; 0.106 ; 1.378 ; +; Cell ; ; 12 ; 0.260 ; 8 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.216 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.246 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1713: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.609 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+---------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.615 ; 80 ; 0.128 ; 0.769 ; +; Cell ; ; 14 ; 0.529 ; 16 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.261 ; 3.269 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 4.150 ; 0.142 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.224 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.229 ; 0.005 ; RR ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.412 ; 0.183 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.469 ; 0.057 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.474 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.157 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.248 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.253 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.022 ; 0.769 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|dataf ; +; 6.051 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34|combout ; +; 6.057 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~34~la_mlab/laboutt[9] ; +; 6.185 ; 0.128 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|datae ; +; 6.261 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y159_N18 ; High Speed ; vx_fetch|VX_Warp_two|i199~45|combout ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|d ; +; 6.261 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N19 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.609 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y159_N19 ; ; vx_fetch|VX_Warp_two|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1714: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.727 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.519 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.548 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.553 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.160 ; 0.607 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|datad ; +; 6.247 ; 0.087 ; RR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|d ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1715: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.242 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.244 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.732 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.242 ; 3.244 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.437 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; +; 5.517 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; +; 5.522 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; +; 6.215 ; 0.693 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~751|dataf ; +; 6.242 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y164_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~751|combout ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y164_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15]|d ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y164_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1716: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.267 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.028 ; ; ; ; ; ; +; Data Delay ; 3.269 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.805 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.267 ; 3.269 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.568 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.238 ; 0.670 ; RR ; IC ; 1 ; MLABCELL_X109_Y153_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1002|dataf ; +; 6.267 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X109_Y153_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1002|combout ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y153_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10]|d ; +; 6.267 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y153_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.470 ; 2.970 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X109_Y153_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y153_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10] ; +; 5.470 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.440 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.175 ; ; uTsu ; 1 ; FF_X109_Y153_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][10] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1717: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.796 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.508 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.539 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.543 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.229 ; 0.686 ; RR ; IC ; 1 ; LABCELL_X108_Y152_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~676|dataf ; +; 6.256 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X108_Y152_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~676|combout ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4]|d ; +; 6.256 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y152_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X108_Y152_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y152_N38 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y152_N38 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1718: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|warp_num[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.206 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.208 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.644 ; 82 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.443 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.206 ; 3.208 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.113 ; 0.698 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N27 ; High Speed ; vx_d_e_reg|i602~1|datac ; +; 6.206 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X80_Y153_N27 ; High Speed ; vx_d_e_reg|i602~1|combout ; +; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N29 ; High Speed ; vx_d_e_reg|warp_num[1]|d ; +; 6.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N29 ; High Speed ; vx_d_e_reg|warp_num[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X80_Y153_N29 ; High Speed ; vx_d_e_reg|warp_num[1]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y153_N29 ; High Speed ; vx_d_e_reg|warp_num[1] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.166 ; ; uTsu ; 1 ; FF_X80_Y153_N29 ; ; vx_d_e_reg|warp_num[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1719: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.736 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.495 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[13] ; +; 6.219 ; 0.724 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~959|dataf ; +; 6.247 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~959|combout ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31]|d ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X98_Y143_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1720: Setup slack is -0.652 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.652 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.754 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.461 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.537 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.541 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.232 ; 0.691 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~818|dataf ; +; 6.260 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X103_Y146_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~818|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y146_N50 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1721: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.199 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.201 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.619 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.128 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.199 ; 3.201 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; +; 3.935 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.939 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.055 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; +; 4.183 ; 0.128 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.189 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.304 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.330 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.335 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.055 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.133 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.139 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.505 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.533 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.537 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.171 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.199 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.199 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.199 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1722: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.200 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.202 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.128 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.200 ; 3.202 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; +; 3.935 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.939 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.055 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; +; 4.183 ; 0.128 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.189 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.304 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.330 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.335 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.055 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.133 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.139 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.505 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.533 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.537 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.172 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.200 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.200 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.200 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1723: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.655 ; 81 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.479 ; 15 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.253 ; 3.261 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.942 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; +; 4.063 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; +; 4.169 ; 0.106 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.175 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.290 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.316 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.321 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.084 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.162 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.168 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.882 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.912 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.918 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.178 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.253 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1724: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.238 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.547 ; 78 ; 0.116 ; 0.686 ; +; Cell ; ; 14 ; 0.574 ; 18 ; 0.000 ; 0.114 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.238 ; 3.246 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.888 ; 0.686 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|dataa ; +; 4.002 ; 0.114 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1|combout ; +; 4.008 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~1~la_mlab/laboutt[9] ; +; 4.124 ; 0.116 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|dataf ; +; 4.150 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.155 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.360 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.456 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.461 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.118 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.211 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.217 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.501 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.527 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.533 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.132 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.238 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1725: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.112 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.114 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.112 ; 3.114 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|sload ; +; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N4 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N4 ; ; vx_fetch|VX_Warp_zero|real_PC[14] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1726: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.112 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.114 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.112 ; 3.114 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|sload ; +; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N10 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[9] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.014 ; ; uTsu ; 1 ; FF_X71_Y161_N10 ; ; vx_fetch|VX_Warp_zero|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1727: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.847 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.288 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.227 ; 0.716 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~692|dataf ; +; 6.255 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X99_Y145_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~692|combout ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20]|d ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X99_Y145_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1728: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.250 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.252 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.794 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.250 ; 3.252 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.557 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.222 ; 0.665 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|dataf ; +; 6.250 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|combout ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]|d ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N32 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N32 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1729: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.848 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.375 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; +; 5.404 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; +; 5.408 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; +; 6.226 ; 0.818 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|dataf ; +; 6.255 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|combout ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE|d ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y150_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1730: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.612 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.805 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.469 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.501 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.506 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[17] ; +; 6.237 ; 0.731 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~786|dataf ; +; 6.263 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X103_Y146_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~786|combout ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18]|d ; +; 6.263 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.612 ; 0.167 ; ; uTsu ; 1 ; FF_X103_Y146_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1731: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.233 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.235 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.776 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.233 ; 3.235 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.479 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.508 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.514 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; +; 6.207 ; 0.693 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~655|dataf ; +; 6.233 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~655|combout ; +; 6.233 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15]|d ; +; 6.233 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.164 ; ; uTsu ; 1 ; FF_X94_Y164_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1732: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.224 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.226 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.712 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.224 ; 3.226 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.397 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.473 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.477 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.197 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|dataf ; +; 6.224 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|combout ; +; 6.224 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|d ; +; 6.224 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1733: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.302 ; 0.437 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|dataf ; +; 5.331 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|combout ; +; 5.335 ; 0.004 ; RR ; CELL ; 16 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14~la_lab/laboutt[4] ; +; 6.228 ; 0.893 ; RR ; IC ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|dataf ; +; 6.255 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|combout ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|d ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y159_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1734: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.238 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.587 ; 80 ; 0.117 ; 0.710 ; +; Cell ; ; 14 ; 0.534 ; 16 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.238 ; 3.246 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.500 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.526 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.532 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.131 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.238 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1735: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.269 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.740 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.410 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.269 ; 3.271 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.404 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.431 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.437 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.176 ; 0.739 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|datac ; +; 6.269 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~922|combout ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|d ; +; 6.269 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y142_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1736: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.617 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.027 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.804 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.433 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.460 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.466 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.240 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|dataf ; +; 6.268 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1017|combout ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|d ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; +; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.617 ; 0.176 ; ; uTsu ; 1 ; FF_X107_Y149_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1737: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|csr_mask[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.215 ; +; Data Required Time ; 5.564 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.217 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.728 ; 85 ; 0.108 ; 0.861 ; +; Cell ; ; 12 ; 0.368 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.215 ; 3.217 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.186 ; 0.861 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N36 ; High Speed ; vx_d_e_reg|i531~2|dataf ; +; 6.215 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N36 ; High Speed ; vx_d_e_reg|i531~2|combout ; +; 6.215 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2]|d ; +; 6.215 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N38 ; High Speed ; vx_d_e_reg|csr_mask[2] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N38 ; ; vx_d_e_reg|csr_mask[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1738: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_d_e_reg|csr_mask[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.215 ; +; Data Required Time ; 5.564 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.066 ; ; ; ; ; ; +; Data Delay ; 3.217 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.729 ; 85 ; 0.108 ; 0.862 ; +; Cell ; ; 12 ; 0.367 ; 11 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.144 ; 79 ; 0.000 ; 2.144 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.215 ; 3.217 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.325 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.187 ; 0.862 ; FF ; IC ; 1 ; LABCELL_X81_Y155_N33 ; High Speed ; vx_d_e_reg|i531~3|dataf ; +; 6.215 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X81_Y155_N33 ; High Speed ; vx_d_e_reg|i531~3|combout ; +; 6.215 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3]|d ; +; 6.215 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.432 ; 2.932 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.209 ; 2.144 ; RR ; IC ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3]|clk ; +; 5.209 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y155_N35 ; High Speed ; vx_d_e_reg|csr_mask[3] ; +; 5.432 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.402 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.564 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y155_N35 ; ; vx_d_e_reg|csr_mask[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1739: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.772 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.363 ; 11 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.834 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.282 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; +; 5.312 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; +; 5.316 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; +; 6.169 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; +; 6.255 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1740: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.755 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.378 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.380 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.407 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.412 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.160 ; 0.748 ; RR ; IC ; 1 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|datad ; +; 6.252 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y163_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~910|combout ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|d ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y163_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y163_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1741: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|csr_address[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.163 ; +; Data Required Time ; 5.512 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.121 ; ; ; ; ; ; +; Data Delay ; 3.165 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.670 ; 84 ; 0.119 ; 0.821 ; +; Cell ; ; 12 ; 0.373 ; 12 ; 0.000 ; 0.083 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.163 ; 3.165 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.203 ; 0.821 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.286 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.291 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.410 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.483 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.487 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.275 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.307 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.090 ; 0.783 ; RR ; IC ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|datae ; +; 6.163 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y149_N27 ; High Speed ; vx_d_e_reg|i498~0|combout ; +; 6.163 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|d ; +; 6.163 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.377 ; 2.877 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y149_N28 ; High Speed ; vx_d_e_reg|csr_address[0] ; +; 5.377 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.347 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.512 ; 0.165 ; ; uTsu ; 1 ; FF_X49_Y149_N28 ; ; vx_d_e_reg|csr_address[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1742: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|PC_next_out[31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.077 ; +; Data Required Time ; 5.426 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.079 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.077 ; 3.079 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31]|sclr ; +; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N29 ; High Speed ; vx_d_e_reg|PC_next_out[31] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N29 ; ; vx_d_e_reg|PC_next_out[31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1743: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|PC_next_out[28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.077 ; +; Data Required Time ; 5.426 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.079 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.077 ; 3.079 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28]|sclr ; +; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N19 ; High Speed ; vx_d_e_reg|PC_next_out[28] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N19 ; ; vx_d_e_reg|PC_next_out[28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1744: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|PC_next_out[23] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.077 ; +; Data Required Time ; 5.426 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.079 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.077 ; 3.079 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23]|sclr ; +; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N5 ; High Speed ; vx_d_e_reg|PC_next_out[23] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N5 ; ; vx_d_e_reg|PC_next_out[23] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1745: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|PC_next_out[24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.077 ; +; Data Required Time ; 5.426 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.079 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.077 ; 3.079 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24]|sclr ; +; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N7 ; High Speed ; vx_d_e_reg|PC_next_out[24] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N7 ; ; vx_d_e_reg|PC_next_out[24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1746: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|PC_next_out[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.077 ; +; Data Required Time ; 5.426 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.079 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.077 ; 3.079 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22]|sclr ; +; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N1 ; High Speed ; vx_d_e_reg|PC_next_out[22] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.426 ; 0.021 ; ; uTsu ; 1 ; FF_X80_Y155_N1 ; ; vx_d_e_reg|PC_next_out[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1747: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_f_d_reg|curr_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.121 ; +; Data Required Time ; 5.470 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.123 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.742 ; 88 ; 0.119 ; 1.398 ; +; Cell ; ; 10 ; 0.261 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.121 ; 3.123 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.356 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.690 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.718 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.723 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.121 ; 1.398 ; FF ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|ena ; +; 6.121 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N32 ; High Speed ; vx_f_d_reg|curr_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.470 ; 0.028 ; ; uTsu ; 1 ; FF_X69_Y158_N32 ; ; vx_f_d_reg|curr_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1748: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|csr_address[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.202 ; +; Data Required Time ; 5.551 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.113 ; ; ; ; ; ; +; Data Delay ; 3.210 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.515 ; 78 ; 0.118 ; 0.935 ; +; Cell ; ; 12 ; 0.569 ; 18 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.202 ; 3.210 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.239 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.174 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; +; 6.202 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; +; 6.202 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; +; 6.202 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1749: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.253 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.880 ; 89 ; 0.127 ; 1.316 ; +; Cell ; ; 12 ; 0.251 ; 8 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.251 ; 3.253 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.225 ; 1.316 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|dataf ; +; 6.251 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|combout ; +; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|d ; +; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1750: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.813 ; 87 ; 0.114 ; 1.354 ; +; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.218 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; +; 6.246 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|d ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1751: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.725 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.407 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; +; 5.436 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; +; 5.440 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; +; 6.156 ; 0.716 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|datad ; +; 6.248 ; 0.092 ; RR ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; +; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1752: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.235 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.237 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.728 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.388 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.235 ; 3.237 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.413 ; 0.485 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~17|datad ; +; 5.489 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~17|combout ; +; 5.494 ; 0.005 ; RR ; CELL ; 17 ; LABCELL_X99_Y153_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~17~la_lab/laboutb[3] ; +; 6.207 ; 0.713 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~559|dataf ; +; 6.235 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~559|combout ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15]|d ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.166 ; ; uTsu ; 1 ; FF_X94_Y164_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[17][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1753: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.250 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.252 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.790 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.250 ; 3.252 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.520 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.549 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.554 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.223 ; 0.669 ; RR ; IC ; 1 ; LABCELL_X104_Y158_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~715|dataf ; +; 6.250 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y158_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~715|combout ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y158_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11]|d ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y158_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X104_Y158_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y158_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y158_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1754: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.235 ; +; Data Required Time ; 5.584 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.237 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.777 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.235 ; 3.237 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.208 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X93_Y157_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~785|dataf ; +; 6.235 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X93_Y157_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~785|combout ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y157_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]|d ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y157_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X93_Y157_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y157_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.584 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y157_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1755: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.743 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.398 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; +; 5.427 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; +; 5.431 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; +; 6.174 ; 0.743 ; RR ; IC ; 1 ; LABCELL_X108_Y151_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~665|datac ; +; 6.254 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X108_Y151_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~665|combout ; +; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]|d ; +; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X108_Y151_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.164 ; ; uTsu ; 1 ; FF_X108_Y151_N29 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1756: Setup slack is -0.651 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|rs1[0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.203 ; +; Data Required Time ; 5.552 ; +; Slack ; -0.651 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.205 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.657 ; 83 ; 0.108 ; 0.868 ; +; Cell ; ; 12 ; 0.427 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.203 ; 3.205 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.496 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.364 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.442 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.447 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.555 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.628 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.632 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.383 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.409 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.415 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.126 ; 0.711 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N3 ; High Speed ; vx_d_e_reg|i316~0|datac ; +; 6.203 ; 0.077 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N3 ; High Speed ; vx_d_e_reg|i316~0|combout ; +; 6.203 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y153_N4 ; High Speed ; vx_d_e_reg|rs1[0]|d ; +; 6.203 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y153_N4 ; High Speed ; vx_d_e_reg|rs1[0] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y153_N4 ; High Speed ; vx_d_e_reg|rs1[0]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y153_N4 ; High Speed ; vx_d_e_reg|rs1[0] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.552 ; 0.165 ; ; uTsu ; 1 ; FF_X81_Y153_N4 ; ; vx_d_e_reg|rs1[0] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1757: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.197 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.199 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.617 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.461 ; 14 ; 0.000 ; 0.128 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.197 ; 3.199 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; +; 3.935 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.939 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.055 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; +; 4.183 ; 0.128 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.189 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.304 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.330 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.335 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.055 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.133 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.139 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.505 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.533 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.537 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.169 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.197 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.197 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.197 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1758: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.199 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.207 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.633 ; 82 ; 0.138 ; 0.657 ; +; Cell ; ; 14 ; 0.447 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.199 ; 3.207 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.795 ; 0.632 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datae ; +; 3.853 ; 0.058 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 3.859 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 3.997 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.071 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.076 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.281 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.377 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.382 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.039 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.132 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.138 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.504 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.532 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.536 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.171 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.199 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.199 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.199 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1759: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.198 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.206 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.632 ; 82 ; 0.138 ; 0.657 ; +; Cell ; ; 14 ; 0.447 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.198 ; 3.206 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.795 ; 0.632 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datae ; +; 3.853 ; 0.058 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 3.859 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 3.997 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.071 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.076 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.281 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.377 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.382 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.039 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.132 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.138 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.504 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.532 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.536 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.170 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.198 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.198 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.198 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1760: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.112 ; +; Data Required Time ; 5.462 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+---------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.114 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.112 ; 3.114 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|sload ; +; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N5 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N5 ; ; vx_fetch|VX_Warp_zero|real_PC[14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1761: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.112 ; +; Data Required Time ; 5.462 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.114 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.112 ; 3.114 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|sload ; +; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N14 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[8] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.462 ; 0.015 ; ; uTsu ; 1 ; FF_X71_Y161_N14 ; ; vx_fetch|VX_Warp_zero|real_PC[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1762: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.250 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.252 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.785 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.250 ; 3.252 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.478 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.505 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.511 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.164 ; 0.653 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1002|datac ; +; 6.250 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1002|combout ; +; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10]|d ; +; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y157_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1763: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.239 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.241 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.830 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.239 ; 3.241 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.488 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.517 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.523 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; +; 6.211 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|dataf ; +; 6.239 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|combout ; +; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]|d ; +; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y147_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1764: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.232 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.234 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.775 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.232 ; 3.234 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.503 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.204 ; 0.701 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1001|dataf ; +; 6.232 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1001|combout ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9]|d ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y159_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1765: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.762 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.386 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.371 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.451 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.455 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.241 ; 0.786 ; RR ; IC ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|dataf ; +; 6.268 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|combout ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|d ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.181 ; ; uTsu ; 1 ; FF_X101_Y160_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1766: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.785 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.480 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.509 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.515 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; +; 6.216 ; 0.701 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~732|dataf ; +; 6.243 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~732|combout ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28]|d ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1767: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.795 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.468 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.499 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.503 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.225 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|dataf ; +; 6.252 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|combout ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE|d ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N25 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.164 ; ; uTsu ; 1 ; FF_X108_Y150_N25 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1768: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.232 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.234 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.776 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.232 ; 3.234 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.558 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.205 ; 0.647 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~969|dataf ; +; 6.232 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N36 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~969|combout ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9]|d ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N37 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X89_Y159_N37 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1769: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-----------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------+ +; Property ; Value ; ++--------------------+--------------------------+ +; From Node ; vx_d_e_reg|a_reg_data[5] ; +; To Node ; vx_e_m_reg|alu_result[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.153 ; +; Data Required Time ; 5.503 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+--------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.084 ; ; ; ; ; ; +; Data Delay ; 3.204 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.322 ; 79 ; 0.000 ; 2.322 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 4 ; 2.394 ; 75 ; 0.121 ; 1.030 ; +; Cell ; ; 12 ; 0.576 ; 18 ; 0.000 ; 0.131 ; +; uTco ; ; 1 ; 0.234 ; 7 ; 0.234 ; 0.234 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.949 ; 2.949 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.949 ; 2.322 ; RR ; IC ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5]|clk ; +; 2.949 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5] ; +; 6.153 ; 3.204 ; ; ; ; ; ; data path ; +; 3.183 ; 0.234 ; RR ; uTco ; 1 ; FF_X79_Y157_N46 ; ; vx_d_e_reg|a_reg_data[5]|q ; +; 3.247 ; 0.064 ; RR ; CELL ; 16 ; FF_X79_Y157_N46 ; High Speed ; vx_d_e_reg|a_reg_data[5]~la_lab/laboutb[10] ; +; 4.277 ; 1.030 ; RR ; IC ; 4 ; LABCELL_X73_Y152_N15 ; High Speed ; vx_execute|[0].vx_alu|add_0~21|datad ; +; 4.408 ; 0.131 ; RF ; CELL ; 1 ; LABCELL_X73_Y152_N15 ; High Speed ; vx_execute|[0].vx_alu|add_0~21|cout ; +; 4.408 ; 0.000 ; FF ; CELL ; 3 ; LABCELL_X73_Y152_N18 ; High Speed ; vx_execute|[0].vx_alu|add_0~25|cin ; +; 4.522 ; 0.114 ; FF ; CELL ; 1 ; LABCELL_X73_Y152_N21 ; High Speed ; vx_execute|[0].vx_alu|add_0~29|sumout ; +; 4.527 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X73_Y152_N21 ; High Speed ; vx_execute|[0].vx_alu|add_0~29~la_lab/laboutt[15] ; +; 4.954 ; 0.427 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~51|datac ; +; 5.041 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~51|combout ; +; 5.047 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~51~la_mlab/laboutt[13] ; +; 5.168 ; 0.121 ; FF ; IC ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|datac ; +; 5.258 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|combout ; +; 5.264 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52~la_mlab/laboutb[11] ; +; 6.080 ; 0.816 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|datad ; +; 6.153 ; 0.073 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|combout ; +; 6.153 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|d ; +; 6.153 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.503 ; 0.168 ; ; uTsu ; 1 ; FF_X46_Y153_N34 ; ; vx_e_m_reg|alu_result[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1770: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++----------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.186 ; +; Data Required Time ; 5.536 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+-------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.082 ; ; ; ; ; ; +; Data Delay ; 3.188 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.633 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.433 ; 14 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.141 ; 79 ; 0.000 ; 2.141 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.186 ; 3.188 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.104 ; 0.750 ; FF ; IC ; 1 ; LABCELL_X79_Y151_N57 ; High Speed ; vx_d_e_reg|i385~81|datad ; +; 6.186 ; 0.082 ; FR ; CELL ; 2 ; LABCELL_X79_Y151_N57 ; High Speed ; vx_d_e_reg|i385~81|combout ; +; 6.186 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE|d ; +; 6.186 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.416 ; 2.916 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.206 ; 2.141 ; RR ; IC ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE|clk ; +; 5.206 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N58 ; High Speed ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; +; 5.416 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.386 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.536 ; 0.150 ; ; uTsu ; 1 ; FF_X79_Y151_N58 ; ; vx_d_e_reg|b_reg_data[26]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1771: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.227 ; +; Data Required Time ; 5.577 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.229 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.781 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.227 ; 3.229 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.444 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.471 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.477 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.199 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|dataf ; +; 6.227 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1000|combout ; +; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|d ; +; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N53 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.577 ; 0.163 ; ; uTsu ; 1 ; FF_X93_Y162_N53 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1772: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.237 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.587 ; 80 ; 0.117 ; 0.710 ; +; Cell ; ; 14 ; 0.533 ; 16 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.237 ; 3.245 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; RR ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.202 ; 0.085 ; RR ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.912 ; 0.710 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 4.002 ; 0.090 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.007 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.124 ; 0.117 ; FF ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.206 ; 0.082 ; FR ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.211 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.431 ; 0.220 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.455 ; 0.024 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.117 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.210 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.216 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.500 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.526 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.532 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.131 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.237 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1773: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.051 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.788 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.491 ; 0.627 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|dataf ; +; 5.517 ; 0.026 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27|combout ; +; 5.523 ; 0.006 ; RR ; CELL ; 20 ; MLABCELL_X98_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~27~la_mlab/laboutt[11] ; +; 6.222 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|dataf ; +; 6.248 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X94_Y163_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~872|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.447 ; 2.947 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y163_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; +; 5.447 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.417 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.181 ; ; uTsu ; 1 ; FF_X94_Y163_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[27][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1774: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.730 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.190 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; +; 5.217 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; +; 5.222 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; +; 6.164 ; 0.942 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|datad ; +; 6.246 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~270|combout ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|d ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y162_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][14] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1775: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.380 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.457 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.462 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; +; 6.219 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; +; 6.246 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1776: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|PC_next_out[25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.077 ; +; Data Required Time ; 5.427 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.063 ; ; ; ; ; ; +; Data Delay ; 3.079 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.606 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 10 ; 0.351 ; 11 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.077 ; 3.079 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.077 ; 0.723 ; FF ; IC ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25]|sclr ; +; 6.077 ; 0.000 ; FF ; CELL ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.435 ; 2.935 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X80_Y155_N11 ; High Speed ; vx_d_e_reg|PC_next_out[25] ; +; 5.435 ; 0.228 ; ; ; ; ; ; clock pessimism removed ; +; 5.405 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.427 ; 0.022 ; ; uTsu ; 1 ; FF_X80_Y155_N11 ; ; vx_d_e_reg|PC_next_out[25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1777: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.245 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.815 ; 87 ; 0.110 ; 1.366 ; +; Cell ; ; 12 ; 0.311 ; 10 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.245 ; 3.247 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.217 ; 1.366 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|dataf ; +; 6.245 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~814|combout ; +; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|d ; +; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1778: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.750 ; 84 ; 0.106 ; 1.220 ; +; Cell ; ; 12 ; 0.399 ; 12 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.148 ; 1.220 ; FF ; IC ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|datab ; +; 6.268 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X101_Y160_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~866|combout ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|d ; +; 6.268 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.181 ; ; uTsu ; 1 ; FF_X101_Y160_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1779: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.727 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.401 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.519 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.548 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.553 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.160 ; 0.607 ; RR ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|datad ; +; 6.247 ; 0.087 ; RR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|d ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1780: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.263 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.265 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.745 ; 84 ; 0.106 ; 1.215 ; +; Cell ; ; 12 ; 0.399 ; 12 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.263 ; 3.265 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.143 ; 1.215 ; FF ; IC ; 1 ; MLABCELL_X101_Y160_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~610|datab ; +; 6.263 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X101_Y160_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~610|combout ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2]|d ; +; 6.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y160_N50 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1781: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.725 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.411 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.252 ; 0.326 ; RR ; IC ; 1 ; LABCELL_X93_Y153_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~19|datac ; +; 5.331 ; 0.079 ; RF ; CELL ; 2 ; LABCELL_X93_Y153_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~19|combout ; +; 5.335 ; 0.004 ; FF ; CELL ; 23 ; LABCELL_X93_Y153_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~19~la_lab/laboutb[16] ; +; 6.226 ; 0.891 ; FF ; IC ; 1 ; MLABCELL_X101_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~622|dataf ; +; 6.255 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X101_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~622|combout ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14]|d ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[19][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1782: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.792 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.526 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.558 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.562 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[16] ; +; 6.226 ; 0.664 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~607|dataf ; +; 6.253 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y145_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~607|combout ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31]|d ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.166 ; ; uTsu ; 1 ; FF_X99_Y145_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1783: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.041 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.728 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.394 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.567 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.594 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.599 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.158 ; 0.559 ; RR ; IC ; 1 ; LABCELL_X99_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~517|datac ; +; 6.241 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~517|combout ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y163_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5]|d ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y163_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X99_Y163_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5]|clk ; +; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y163_N14 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5] ; +; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y163_N14 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][5] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1784: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.235 ; +; Data Required Time ; 5.585 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.237 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.777 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.235 ; 3.237 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.667 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.695 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.700 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.208 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X93_Y157_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~785|dataf ; +; 6.235 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X93_Y157_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~785|combout ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y157_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE|d ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y157_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X93_Y157_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y157_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.585 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y157_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][17]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1785: Setup slack is -0.650 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.650 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.743 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.398 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; +; 5.427 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; +; 5.431 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; +; 6.174 ; 0.743 ; RR ; IC ; 1 ; LABCELL_X108_Y151_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~665|datac ; +; 6.254 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X108_Y151_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~665|combout ; +; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE|d ; +; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X108_Y151_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y151_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.165 ; ; uTsu ; 1 ; FF_X108_Y151_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1786: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.196 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.204 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.630 ; 82 ; 0.138 ; 0.657 ; +; Cell ; ; 14 ; 0.447 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.196 ; 3.204 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.795 ; 0.632 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datae ; +; 3.853 ; 0.058 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 3.859 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 3.997 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.071 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.076 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.281 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.377 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.382 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.039 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.132 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.138 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.504 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.532 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.536 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.168 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.196 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.196 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.196 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1787: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.249 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.251 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.844 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.249 ; 3.251 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.482 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.223 ; 0.741 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~924|dataf ; +; 6.249 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~924|combout ; +; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28]|d ; +; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1788: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.239 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.241 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.830 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.239 ; 3.241 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.488 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.517 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.523 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; +; 6.211 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|dataf ; +; 6.239 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|combout ; +; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE|d ; +; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y147_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1789: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.795 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.468 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.499 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.503 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.225 ; 0.722 ; RR ; IC ; 1 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|dataf ; +; 6.252 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X108_Y150_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~697|combout ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]|d ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.165 ; ; uTsu ; 1 ; FF_X108_Y150_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1790: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.733 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.388 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.469 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.496 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.502 ; 0.006 ; RR ; CELL ; 22 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[3] ; +; 6.162 ; 0.660 ; RR ; IC ; 1 ; LABCELL_X95_Y143_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~986|datac ; +; 6.241 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X95_Y143_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~986|combout ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26]|d ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y143_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y143_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1791: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.790 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.296 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.323 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.329 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.219 ; 0.890 ; RR ; IC ; 1 ; LABCELL_X104_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~263|dataf ; +; 6.246 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X104_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~263|combout ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7]|d ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y159_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.163 ; ; uTsu ; 1 ; FF_X104_Y159_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][7] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1792: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.808 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.300 ; 0.437 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|dataf ; +; 5.329 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14|combout ; +; 5.333 ; 0.004 ; RR ; CELL ; 16 ; LABCELL_X89_Y152_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~14~la_lab/laboutt[4] ; +; 6.226 ; 0.893 ; RR ; IC ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|dataf ; +; 6.253 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y159_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~459|combout ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|d ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y159_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X102_Y159_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[14][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1793: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.222 ; +; Data Required Time ; 5.573 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.056 ; ; ; ; ; ; +; Data Delay ; 3.224 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.731 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.372 ; 12 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.167 ; 79 ; 0.000 ; 2.167 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.222 ; 3.224 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.395 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.471 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.475 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.195 ; 0.720 ; RR ; IC ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|dataf ; +; 6.222 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y164_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~809|combout ; +; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|d ; +; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.442 ; 2.942 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.232 ; 2.167 ; RR ; IC ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9]|clk ; +; 5.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y164_N17 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; +; 5.442 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.412 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.573 ; 0.161 ; ; uTsu ; 1 ; FF_X89_Y164_N17 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1794: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.726 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.410 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.456 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.487 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.491 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.163 ; 0.672 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|datad ; +; 6.255 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1006|combout ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|d ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1795: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_d_e_reg|csr_address[1] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.154 ; +; Data Required Time ; 5.505 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.125 ; ; ; ; ; ; +; Data Delay ; 3.156 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.675 ; 85 ; 0.119 ; 0.840 ; +; Cell ; ; 12 ; 0.361 ; 11 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.154 ; 3.156 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.388 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.228 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.308 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.313 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.432 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.505 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.509 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.297 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.324 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.329 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.081 ; 0.752 ; RR ; IC ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|datae ; +; 6.154 ; 0.073 ; RF ; CELL ; 1 ; LABCELL_X49_Y152_N57 ; High Speed ; vx_d_e_reg|i498~1|combout ; +; 6.154 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|d ; +; 6.154 ; 0.000 ; FF ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.373 ; 2.873 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X49_Y152_N58 ; High Speed ; vx_d_e_reg|csr_address[1] ; +; 5.373 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.343 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.505 ; 0.162 ; ; uTsu ; 1 ; FF_X49_Y152_N58 ; ; vx_d_e_reg|csr_address[1] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1796: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.245 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.765 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.245 ; 3.247 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.827 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.369 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.446 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.450 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.218 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|dataf ; +; 6.245 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y142_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~598|combout ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|d ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y142_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y142_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1797: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|b_reg_data[16] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.200 ; +; Data Required Time ; 5.551 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.078 ; ; ; ; ; ; +; Data Delay ; 3.202 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.632 ; 82 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.448 ; 14 ; 0.000 ; 0.128 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.200 ; 3.202 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.072 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|datab ; +; 6.200 ; 0.128 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N30 ; High Speed ; vx_d_e_reg|i385~51|combout ; +; 6.200 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|d ; +; 6.200 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16]|clk ; +; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N32 ; High Speed ; vx_d_e_reg|b_reg_data[16] ; +; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.551 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y152_N32 ; ; vx_d_e_reg|b_reg_data[16] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1798: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.747 ; 85 ; 0.096 ; 1.046 ; +; Cell ; ; 14 ; 0.377 ; 12 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.493 ; 0.096 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.569 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.574 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.620 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.646 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.650 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.775 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.799 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.805 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.388 ; 0.583 ; RR ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.417 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.422 ; 0.005 ; FF ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.164 ; 0.742 ; FF ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; +; 6.244 ; 0.080 ; FF ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; +; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; +; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1799: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.813 ; 87 ; 0.114 ; 1.354 ; +; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.218 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; +; 6.246 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|d ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1800: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.832 ; 87 ; 0.104 ; 1.354 ; +; Cell ; ; 12 ; 0.293 ; 9 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.216 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; +; 6.244 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|d ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1801: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.868 ; 88 ; 0.106 ; 1.378 ; +; Cell ; ; 12 ; 0.260 ; 8 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.216 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.246 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1802: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-----------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------+ +; Property ; Value ; ++--------------------+--------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[1] ; +; To Node ; vx_e_m_reg|alu_result[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.112 ; +; Data Required Time ; 5.463 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+--------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.168 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.317 ; 79 ; 0.000 ; 2.317 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.542 ; 80 ; 0.127 ; 0.625 ; +; Cell ; ; 16 ; 0.443 ; 14 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.183 ; 6 ; 0.183 ; 0.183 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.170 ; 79 ; 0.000 ; 2.170 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.944 ; 2.944 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.944 ; 2.317 ; RR ; IC ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]|clk ; +; 2.944 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1] ; +; 6.112 ; 3.168 ; ; ; ; ; ; data path ; +; 3.127 ; 0.183 ; FF ; uTco ; 1 ; FF_X79_Y151_N7 ; ; vx_d_e_reg|b_reg_data[1]|q ; +; 3.195 ; 0.068 ; FF ; CELL ; 4 ; FF_X79_Y151_N7 ; High Speed ; vx_d_e_reg|b_reg_data[1]~la_lab/laboutt[4] ; +; 3.820 ; 0.625 ; FF ; IC ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|dataf ; +; 3.848 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22|combout ; +; 3.852 ; 0.004 ; FF ; CELL ; 71 ; LABCELL_X75_Y151_N33 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~22~la_lab/laboutb[2] ; +; 4.224 ; 0.372 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|datac ; +; 4.316 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28|combout ; +; 4.321 ; 0.005 ; FF ; CELL ; 2 ; MLABCELL_X72_Y153_N3 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~28~la_mlab/laboutt[2] ; +; 4.448 ; 0.127 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; +; 4.742 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; +; 4.817 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.821 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.254 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.281 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.287 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.440 ; 0.153 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~29|dataf ; +; 5.468 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~29|combout ; +; 5.472 ; 0.004 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~29~la_lab/laboutt[6] ; +; 6.087 ; 0.615 ; FF ; IC ; 1 ; MLABCELL_X45_Y153_N21 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~30|dataf ; +; 6.112 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X45_Y153_N21 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~30|combout ; +; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3]|d ; +; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.363 ; 2.863 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.235 ; 2.170 ; RR ; IC ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3]|clk ; +; 5.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X45_Y153_N22 ; High Speed ; vx_e_m_reg|alu_result[3] ; +; 5.363 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.333 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.463 ; 0.130 ; ; uTsu ; 1 ; FF_X45_Y153_N22 ; ; vx_e_m_reg|alu_result[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1803: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.728 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.519 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.548 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.553 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.161 ; 0.608 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~666|datad ; +; 6.243 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X97_Y143_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~666|combout ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26]|d ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.165 ; ; uTsu ; 1 ; FF_X97_Y143_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][26] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1804: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.776 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.322 ; 0.404 ; RR ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.226 ; 0.872 ; FF ; IC ; 1 ; LABCELL_X108_Y150_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~281|dataf ; +; 6.254 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X108_Y150_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~281|combout ; +; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25]|d ; +; 6.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y150_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][25] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1805: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.611 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.754 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.387 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.461 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.537 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.541 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.232 ; 0.691 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~818|dataf ; +; 6.260 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X103_Y146_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~818|combout ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE|d ; +; 6.260 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y146_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.611 ; 0.166 ; ; uTsu ; 1 ; FF_X103_Y146_N49 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][18]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1806: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.110 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.112 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.652 ; 85 ; 0.119 ; 1.143 ; +; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.110 ; 3.112 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.110 ; 1.143 ; FF ; IC ; 1 ; FF_X74_Y156_N49 ; High Speed ; vx_f_d_reg|curr_PC[21]|ena ; +; 6.110 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y156_N49 ; High Speed ; vx_f_d_reg|curr_PC[21] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X74_Y156_N49 ; High Speed ; vx_f_d_reg|curr_PC[21]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y156_N49 ; High Speed ; vx_f_d_reg|curr_PC[21] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.027 ; ; uTsu ; 1 ; FF_X74_Y156_N49 ; ; vx_f_d_reg|curr_PC[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1807: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.110 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.112 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.652 ; 85 ; 0.119 ; 1.143 ; +; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.110 ; 3.112 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.110 ; 1.143 ; FF ; IC ; 1 ; FF_X74_Y156_N40 ; High Speed ; vx_f_d_reg|curr_PC[3]|ena ; +; 6.110 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y156_N40 ; High Speed ; vx_f_d_reg|curr_PC[3] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X74_Y156_N40 ; High Speed ; vx_f_d_reg|curr_PC[3]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y156_N40 ; High Speed ; vx_f_d_reg|curr_PC[3] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.027 ; ; uTsu ; 1 ; FF_X74_Y156_N40 ; ; vx_f_d_reg|curr_PC[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1808: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.262 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.264 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.737 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.406 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.262 ; 3.264 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.510 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.537 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.543 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.169 ; 0.626 ; RR ; IC ; 1 ; MLABCELL_X98_Y142_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1014|datac ; +; 6.262 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X98_Y142_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1014|combout ; +; 6.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22]|d ; +; 6.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X98_Y142_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y142_N34 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.177 ; ; uTsu ; 1 ; FF_X98_Y142_N34 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1809: Setup slack is -0.649 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.649 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.747 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.408 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.488 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.492 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.229 ; 0.737 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~842|dataf ; +; 6.255 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X107_Y157_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~842|combout ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]|d ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y157_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N47 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y157_N47 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1810: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.197 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.205 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.696 ; 84 ; 0.135 ; 0.657 ; +; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.197 ; 3.205 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.734 ; 0.552 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|dataf ; +; 3.760 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; +; 3.765 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; +; 3.900 ; 0.135 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; +; 3.926 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.931 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.282 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.375 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.380 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.037 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.130 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.136 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.502 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.530 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.534 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.169 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.197 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.197 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.197 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1811: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.196 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.204 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.695 ; 84 ; 0.135 ; 0.657 ; +; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.196 ; 3.204 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.734 ; 0.552 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|dataf ; +; 3.760 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; +; 3.765 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; +; 3.900 ; 0.135 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; +; 3.926 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.931 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.282 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.375 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.380 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.037 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.130 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.136 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.502 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.530 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.534 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.168 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.196 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.196 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.196 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1812: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++----------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------+ +; Property ; Value ; ++--------------------+-------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.234 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+-------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.236 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.578 ; 80 ; 0.127 ; 0.712 ; +; Cell ; ; 14 ; 0.536 ; 17 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.234 ; 3.236 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.818 ; 0.654 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datac ; +; 3.902 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.906 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.050 ; 0.144 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.130 ; 0.080 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.135 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.262 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.383 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.428 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.454 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.460 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.172 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.234 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1813: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[24] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.234 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.060 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.350 ; 79 ; 0.000 ; 2.350 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.628 ; 81 ; 0.192 ; 0.712 ; +; Cell ; ; 14 ; 0.506 ; 16 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.977 ; 2.977 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.977 ; 2.350 ; RR ; IC ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]|clk ; +; 2.977 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24] ; +; 6.234 ; 3.257 ; ; ; ; ; ; data path ; +; 3.100 ; 0.123 ; RR ; uTco ; 1 ; FF_X91_Y153_N23 ; ; vx_f_d_reg|instruction[24]|q ; +; 3.189 ; 0.089 ; RR ; CELL ; 138 ; FF_X91_Y153_N23 ; High Speed ; vx_f_d_reg|instruction[24]~la_lab/laboutt[15] ; +; 3.767 ; 0.578 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|dataf ; +; 3.794 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.799 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 3.991 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.077 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.082 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.287 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.383 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.388 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.045 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.138 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.144 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.428 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.454 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.460 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.172 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.234 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1814: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.112 ; +; Data Required Time ; 5.464 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.114 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.112 ; 3.114 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|sload ; +; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N56 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[20] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N56 ; ; vx_fetch|VX_Warp_zero|real_PC[20] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1815: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.112 ; +; Data Required Time ; 5.464 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.114 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.112 ; 3.114 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|sload ; +; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N44 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[17] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N44 ; ; vx_fetch|VX_Warp_zero|real_PC[17] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1816: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[16] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.112 ; +; Data Required Time ; 5.464 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.021 ; ; ; ; ; ; +; Data Delay ; 3.114 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.639 ; 85 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.353 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.202 ; 80 ; 0.000 ; 2.202 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.112 ; 3.114 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.770 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.797 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.803 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.112 ; 0.309 ; FF ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|sload ; +; 6.112 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.477 ; 2.977 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.267 ; 2.202 ; RR ; IC ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16]|clk ; +; 5.267 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y161_N32 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[16] ; +; 5.477 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.447 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.464 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y161_N32 ; ; vx_fetch|VX_Warp_zero|real_PC[16] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1817: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.728 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.404 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.417 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.444 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.449 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.166 ; 0.717 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|datac ; +; 6.252 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|combout ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|d ; +; 6.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X107_Y157_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1818: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.785 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.167 ; 0.258 ; FF ; IC ; 1 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11|dataf ; +; 5.194 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11|combout ; +; 5.200 ; 0.006 ; RR ; CELL ; 29 ; MLABCELL_X90_Y153_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~11~la_mlab/laboutt[1] ; +; 6.163 ; 0.963 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~366|datac ; +; 6.241 ; 0.078 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N57 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~366|combout ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14]|d ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N58 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.162 ; ; uTsu ; 1 ; FF_X102_Y162_N58 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1819: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.270 ; +; Data Required Time ; 5.622 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.027 ; ; ; ; ; ; +; Data Delay ; 3.272 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.813 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.270 ; 3.272 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.493 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.524 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.528 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.243 ; 0.715 ; RR ; IC ; 1 ; MLABCELL_X107_Y149_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1017|dataf ; +; 6.270 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X107_Y149_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1017|combout ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25]|d ; +; 6.270 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y149_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; +; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.622 ; 0.181 ; ; uTsu ; 1 ; FF_X107_Y149_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1820: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.790 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.367 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; +; 5.396 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; +; 5.400 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; +; 6.218 ; 0.818 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|dataf ; +; 6.247 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|combout ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]|d ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1821: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.229 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.231 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.764 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.229 ; 3.231 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.450 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.477 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.483 ; 0.006 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[3] ; +; 6.202 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|dataf ; +; 6.229 ; 0.027 ; RR ; CELL ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|combout ; +; 6.229 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|d ; +; 6.229 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y159_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1822: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.235 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.237 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.772 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.235 ; 3.237 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.207 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; +; 6.235 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|d ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1823: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.235 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.042 ; ; ; ; ; ; +; Data Delay ; 3.237 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.772 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.181 ; 79 ; 0.000 ; 2.181 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.235 ; 3.237 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.590 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.618 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.623 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.207 ; 0.584 ; RR ; IC ; 1 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|dataf ; +; 6.235 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X97_Y164_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~774|combout ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|d ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.456 ; 2.956 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.246 ; 2.181 ; RR ; IC ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6]|clk ; +; 5.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y164_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; +; 5.456 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.426 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y164_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1824: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.238 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.240 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.771 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.238 ; 3.240 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.272 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.299 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.305 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.210 ; 0.905 ; RR ; IC ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|dataf ; +; 6.238 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|combout ; +; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|d ; +; 6.238 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.162 ; ; uTsu ; 1 ; FF_X109_Y154_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1825: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.048 ; ; ; ; ; ; +; Data Delay ; 3.253 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.844 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.251 ; 3.253 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.396 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.423 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.427 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.223 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; +; 6.251 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; +; 6.251 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; +; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1826: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.254 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.846 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.254 ; 3.256 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.421 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.448 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.454 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.227 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; +; 6.254 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; +; 6.254 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1827: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.802 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.328 ; 10 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.431 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.459 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.465 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.165 ; 0.700 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|datac ; +; 6.248 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X99_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~982|combout ; +; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|d ; +; 6.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X99_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1828: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.810 ; 87 ; 0.114 ; 1.351 ; +; Cell ; ; 12 ; 0.313 ; 10 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.215 ; 1.351 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|dataf ; +; 6.243 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|combout ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|d ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1829: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.778 ; 86 ; 0.106 ; 1.275 ; +; Cell ; ; 12 ; 0.350 ; 11 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.126 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.246 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1830: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.107 ; ; ; ; ; ; +; Data Delay ; 2.175 ; ; ; ; ; ; +; Number of Logic Levels ; ; 2 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 2 ; 1.871 ; 86 ; 0.742 ; 1.129 ; +; Cell ; ; 6 ; 0.171 ; 8 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y155_N44 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10]|clk ; +; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y155_N44 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10] ; +; 6.248 ; 2.175 ; ; ; ; ; ; data path ; +; 4.206 ; 0.133 ; FF ; uTco ; 1 ; FF_X102_Y155_N44 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10]|q ; +; 4.250 ; 0.044 ; FF ; CELL ; 2 ; FF_X102_Y155_N44 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[9] ; +; 4.992 ; 0.742 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|datad ; +; 5.084 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; +; 5.090 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; +; 6.219 ; 1.129 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|dataf ; +; 6.248 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; +; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1831: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.739 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.398 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.407 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; +; 5.436 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; +; 5.440 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; +; 6.170 ; 0.730 ; RR ; IC ; 1 ; MLABCELL_X101_Y146_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~693|datad ; +; 6.256 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y146_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~693|combout ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y146_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21]|d ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y146_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X101_Y146_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y146_N22 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y146_N22 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1832: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.215 ; +; Data Required Time ; 5.567 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.061 ; ; ; ; ; ; +; Data Delay ; 3.217 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.701 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.162 ; 79 ; 0.000 ; 2.162 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.215 ; 3.217 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.363 ; 0.434 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|dataf ; +; 5.392 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12|combout ; +; 5.396 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X89_Y152_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~12~la_lab/laboutt[8] ; +; 6.133 ; 0.737 ; RR ; IC ; 1 ; LABCELL_X87_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~397|datad ; +; 6.215 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X87_Y164_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~397|combout ; +; 6.215 ; 0.000 ; RR ; CELL ; 1 ; FF_X87_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13]|d ; +; 6.215 ; 0.000 ; RR ; CELL ; 1 ; FF_X87_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.437 ; 2.937 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.227 ; 2.162 ; RR ; IC ; 1 ; FF_X87_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13]|clk ; +; 5.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X87_Y164_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13] ; +; 5.437 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.407 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.567 ; 0.160 ; ; uTsu ; 1 ; FF_X87_Y164_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1833: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|b_reg_data[30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.201 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.203 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.605 ; 81 ; 0.192 ; 0.884 ; +; Cell ; ; 12 ; 0.477 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.201 ; 3.203 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.854 ; 0.667 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datad ; +; 3.939 ; 0.085 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.944 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.136 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.222 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.227 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.432 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.528 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.533 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.190 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.283 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.289 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.173 ; 0.884 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; +; 6.201 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; +; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; +; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1834: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[19] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.117 ; +; Data Required Time ; 5.469 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.119 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.659 ; 85 ; 0.119 ; 1.150 ; +; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.117 ; 3.119 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.117 ; 1.150 ; FF ; IC ; 1 ; FF_X74_Y161_N5 ; High Speed ; vx_f_d_reg|curr_PC[19]|ena ; +; 6.117 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y161_N5 ; High Speed ; vx_f_d_reg|curr_PC[19] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X74_Y161_N5 ; High Speed ; vx_f_d_reg|curr_PC[19]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y161_N5 ; High Speed ; vx_f_d_reg|curr_PC[19] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.469 ; 0.026 ; ; uTsu ; 1 ; FF_X74_Y161_N5 ; ; vx_f_d_reg|curr_PC[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1835: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[12] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.117 ; +; Data Required Time ; 5.469 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.119 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.659 ; 85 ; 0.119 ; 1.150 ; +; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.117 ; 3.119 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.117 ; 1.150 ; FF ; IC ; 1 ; FF_X74_Y161_N49 ; High Speed ; vx_f_d_reg|curr_PC[12]|ena ; +; 6.117 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y161_N49 ; High Speed ; vx_f_d_reg|curr_PC[12] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X74_Y161_N49 ; High Speed ; vx_f_d_reg|curr_PC[12]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y161_N49 ; High Speed ; vx_f_d_reg|curr_PC[12] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.469 ; 0.026 ; ; uTsu ; 1 ; FF_X74_Y161_N49 ; ; vx_f_d_reg|curr_PC[12] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1836: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.117 ; +; Data Required Time ; 5.469 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.119 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.659 ; 85 ; 0.119 ; 1.150 ; +; Cell ; ; 10 ; 0.339 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.117 ; 3.119 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.967 ; 0.005 ; FF ; CELL ; 61 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[5] ; +; 6.117 ; 1.150 ; FF ; IC ; 1 ; FF_X74_Y161_N13 ; High Speed ; vx_f_d_reg|curr_PC[2]|ena ; +; 6.117 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y161_N13 ; High Speed ; vx_f_d_reg|curr_PC[2] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X74_Y161_N13 ; High Speed ; vx_f_d_reg|curr_PC[2]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y161_N13 ; High Speed ; vx_f_d_reg|curr_PC[2] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.469 ; 0.026 ; ; uTsu ; 1 ; FF_X74_Y161_N13 ; ; vx_f_d_reg|curr_PC[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1837: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.250 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.252 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.739 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.250 ; 3.252 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.541 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.170 ; 0.629 ; RR ; IC ; 1 ; LABCELL_X104_Y160_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~974|datac ; +; 6.250 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X104_Y160_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~974|combout ; +; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]|d ; +; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X104_Y160_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.166 ; ; uTsu ; 1 ; FF_X104_Y160_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1838: Setup slack is -0.648 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.257 ; +; Data Required Time ; 5.609 ; +; Slack ; -0.648 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.023 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.681 ; 82 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.457 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.200 ; 80 ; 0.000 ; 2.200 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.257 ; 3.259 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.410 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.490 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.495 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[13] ; +; 6.164 ; 0.669 ; RR ; IC ; 1 ; MLABCELL_X103_Y146_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~946|datac ; +; 6.257 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X103_Y146_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~946|combout ; +; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18]|d ; +; 6.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.475 ; 2.975 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.265 ; 2.200 ; RR ; IC ; 1 ; FF_X103_Y146_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18]|clk ; +; 5.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y146_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18] ; +; 5.475 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.445 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.609 ; 0.164 ; ; uTsu ; 1 ; FF_X103_Y146_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1839: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[18] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.194 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.202 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.693 ; 84 ; 0.135 ; 0.657 ; +; Cell ; ; 14 ; 0.382 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18] ; +; 6.194 ; 3.202 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N14 ; ; vx_f_d_reg|instruction[18]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 649 ; FF_X97_Y153_N14 ; High Speed ; vx_f_d_reg|instruction[18]~la_lab/laboutt[9] ; +; 3.734 ; 0.552 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|dataf ; +; 3.760 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; +; 3.765 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; +; 3.900 ; 0.135 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; +; 3.926 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.931 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.282 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.375 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.380 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.037 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.130 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.136 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.502 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.530 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.534 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.166 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.194 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.194 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.194 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1840: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.608 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.686 ; 82 ; 0.107 ; 0.854 ; +; Cell ; ; 14 ; 0.450 ; 14 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.336 ; 0.154 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.410 ; 0.074 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.415 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.269 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.353 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.358 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.466 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.539 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.543 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.294 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.320 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.326 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.038 ; 0.712 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33|dataf ; +; 6.066 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33|combout ; +; 6.072 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N15 ; High Speed ; vx_fetch|VX_Warp_one|i199~33~la_mlab/laboutt[11] ; +; 6.179 ; 0.107 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|datae ; +; 6.255 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N24 ; High Speed ; vx_fetch|VX_Warp_one|i199~39|combout ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|d ; +; 6.255 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N25 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.608 ; 0.166 ; ; uTsu ; 1 ; FF_X69_Y158_N25 ; ; vx_fetch|VX_Warp_one|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1841: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_fetch|VX_Warp_two|real_PC[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.754 ; 85 ; 0.108 ; 0.868 ; +; Cell ; ; 14 ; 0.381 ; 12 ; 0.000 ; 0.078 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; FF ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.346 ; 0.184 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.373 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.379 ; 0.006 ; FF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.247 ; 0.868 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.325 ; 0.078 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.330 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.438 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.511 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.515 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.266 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.292 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.298 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.011 ; 0.713 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|dataf ; +; 6.041 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35|combout ; +; 6.047 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N12 ; High Speed ; vx_fetch|VX_Warp_two|i199~35~la_mlab/laboutt[9] ; +; 6.177 ; 0.130 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|datae ; +; 6.253 ; 0.076 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N42 ; High Speed ; vx_fetch|VX_Warp_two|i199~41|combout ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|d ; +; 6.253 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N44 ; High Speed ; vx_fetch|VX_Warp_two|real_PC[10] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.164 ; ; uTsu ; 1 ; FF_X69_Y158_N44 ; ; vx_fetch|VX_Warp_two|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1842: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.252 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.254 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.830 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.252 ; 3.254 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.572 ; 0.739 ; FF ; IC ; 1 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|dataf ; +; 5.600 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24|combout ; +; 5.605 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X98_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~24~la_mlab/laboutb[8] ; +; 6.225 ; 0.620 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|dataf ; +; 6.252 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~775|combout ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|d ; +; 6.252 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[24][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1843: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.795 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.477 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.504 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.509 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.173 ; 0.664 ; RR ; IC ; 1 ; LABCELL_X104_Y147_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~978|datad ; +; 6.253 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y147_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~978|combout ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18]|d ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.167 ; ; uTsu ; 1 ; FF_X104_Y147_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1844: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.838 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.285 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.482 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.217 ; 0.735 ; RR ; IC ; 1 ; MLABCELL_X98_Y143_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~927|dataf ; +; 6.243 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X98_Y143_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~927|combout ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31]|d ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y143_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X98_Y143_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1845: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.841 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.221 ; 0.710 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|dataf ; +; 6.248 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y145_N29 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1846: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.041 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.731 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.385 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.358 ; 0.470 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|datad ; +; 5.436 ; 0.078 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19|combout ; +; 5.441 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y153_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~19~la_lab/laboutb[11] ; +; 6.209 ; 0.768 ; RR ; IC ; 1 ; LABCELL_X99_Y163_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~613|dataf ; +; 6.236 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y163_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~613|combout ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5]|d ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5]|clk ; +; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y163_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; +; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.162 ; ; uTsu ; 1 ; FF_X99_Y163_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[19][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1847: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.237 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.239 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.781 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.237 ; 3.239 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.379 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.459 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.463 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.210 ; 0.747 ; RR ; IC ; 1 ; LABCELL_X93_Y161_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~877|dataf ; +; 6.237 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y161_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~877|combout ; +; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13]|d ; +; 6.237 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y161_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1848: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_d_e_reg|b_reg_data[14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.198 ; +; Data Required Time ; 5.551 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.078 ; ; ; ; ; ; +; Data Delay ; 3.200 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.653 ; 83 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.425 ; 13 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.198 ; 3.200 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.124 ; 0.770 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N18 ; High Speed ; vx_d_e_reg|i385~45|datae ; +; 6.198 ; 0.074 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N18 ; High Speed ; vx_d_e_reg|i385~45|combout ; +; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14]|d ; +; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14]|clk ; +; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N19 ; High Speed ; vx_d_e_reg|b_reg_data[14] ; +; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.551 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y152_N19 ; ; vx_d_e_reg|b_reg_data[14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1849: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.780 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.446 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.477 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.481 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.220 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|dataf ; +; 6.247 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|combout ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|d ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X102_Y161_N4 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1850: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.782 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.500 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.528 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.534 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.221 ; 0.687 ; RR ; IC ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|dataf ; +; 6.248 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y144_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1851: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.235 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.074 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.413 ; 74 ; 0.118 ; 0.683 ; +; Cell ; ; 14 ; 0.704 ; 22 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.235 ; 3.243 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.516 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.542 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.548 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.105 ; 0.557 ; RR ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.235 ; 0.130 ; RR ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1852: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.668 ; 82 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.334 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.414 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.418 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.154 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; +; 6.236 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; +; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|d ; +; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.165 ; ; uTsu ; 1 ; FF_X95_Y164_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1853: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.263 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.740 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.261 ; 3.263 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.520 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.175 ; 0.655 ; RR ; IC ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|datac ; +; 6.261 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X103_Y160_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~962|combout ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|d ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N55 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.175 ; ; uTsu ; 1 ; FF_X103_Y160_N55 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][2] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1854: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.245 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.733 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.245 ; 3.247 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.406 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.483 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.487 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.219 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|dataf ; +; 6.245 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|combout ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|d ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1855: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.037 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.725 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.397 ; 12 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.190 ; 0.326 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|dataf ; +; 5.217 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8|combout ; +; 5.222 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X90_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~8~la_mlab/laboutb[6] ; +; 6.159 ; 0.937 ; RR ; IC ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|datad ; +; 6.241 ; 0.082 ; RR ; CELL ; 1 ; LABCELL_X102_Y162_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~267|combout ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|d ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.461 ; 2.961 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y162_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; +; 5.461 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.431 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y162_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[8][11] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1856: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.228 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.230 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.753 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.355 ; 11 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.228 ; 3.230 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.342 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; +; 5.422 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; +; 5.427 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; +; 6.200 ; 0.773 ; RR ; IC ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|dataf ; +; 6.228 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~745|combout ; +; 6.228 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|d ; +; 6.228 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y160_N28 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y160_N28 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][9] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1857: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_address[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.198 ; +; Data Required Time ; 5.551 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.113 ; ; ; ; ; ; +; Data Delay ; 3.206 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.680 ; 84 ; 0.128 ; 0.935 ; +; Cell ; ; 12 ; 0.401 ; 13 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.198 ; 3.206 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.235 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.170 ; 0.935 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; +; 6.198 ; 0.028 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; +; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; +; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.551 ; 0.202 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1858: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.721 ; 84 ; 0.104 ; 1.228 ; +; Cell ; ; 12 ; 0.395 ; 12 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.116 ; 1.228 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~79|datab ; +; 6.236 ; 0.120 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~79|combout ; +; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15]|d ; +; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N1 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.168 ; ; uTsu ; 1 ; FF_X92_Y163_N1 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[2][15] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1859: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.832 ; 87 ; 0.104 ; 1.354 ; +; Cell ; ; 12 ; 0.293 ; 9 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.216 ; 1.354 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|dataf ; +; 6.244 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X101_Y162_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~654|combout ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|d ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1860: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; +; To Node ; vx_e_m_reg|alu_result[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.150 ; +; Data Required Time ; 5.503 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.083 ; ; ; ; ; ; +; Data Delay ; 3.202 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.548 ; 80 ; 0.096 ; 0.816 ; +; Cell ; ; 14 ; 0.531 ; 17 ; 0.000 ; 0.122 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|clk ; +; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; +; 6.150 ; 3.202 ; ; ; ; ; ; data path ; +; 3.071 ; 0.123 ; FF ; uTco ; 1 ; FF_X79_Y153_N40 ; ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|q ; +; 3.115 ; 0.044 ; FF ; CELL ; 2 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE~la_lab/laboutb[6] ; +; 3.931 ; 0.816 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|dataf ; +; 3.958 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|combout ; +; 3.964 ; 0.006 ; FF ; CELL ; 70 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20~la_mlab/laboutt[7] ; +; 4.457 ; 0.493 ; FF ; IC ; 1 ; LABCELL_X68_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~31|datae ; +; 4.531 ; 0.074 ; FR ; CELL ; 2 ; LABCELL_X68_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~31|combout ; +; 4.535 ; 0.004 ; RR ; CELL ; 7 ; LABCELL_X68_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~31~la_lab/laboutb[12] ; +; 4.669 ; 0.134 ; RR ; IC ; 1 ; MLABCELL_X69_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|shift_right_0~9|datac ; +; 4.755 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X69_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|shift_right_0~9|combout ; +; 4.761 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X69_Y151_N54 ; High Speed ; vx_execute|[0].vx_alu|shift_right_0~9~la_mlab/laboutb[17] ; +; 4.857 ; 0.096 ; RR ; IC ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50|datab ; +; 4.979 ; 0.122 ; RR ; CELL ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50|combout ; +; 4.985 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y151_N51 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~50~la_mlab/laboutb[15] ; +; 5.210 ; 0.225 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|datad ; +; 5.288 ; 0.078 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52|combout ; +; 5.294 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N45 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~52~la_mlab/laboutb[11] ; +; 6.078 ; 0.784 ; RR ; IC ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|datad ; +; 6.150 ; 0.072 ; RR ; CELL ; 1 ; LABCELL_X46_Y153_N33 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~54|combout ; +; 6.150 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|d ; +; 6.150 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N34 ; High Speed ; vx_e_m_reg|alu_result[7] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.503 ; 0.168 ; ; uTsu ; 1 ; FF_X46_Y153_N34 ; ; vx_e_m_reg|alu_result[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1861: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.849 ; 88 ; 0.104 ; 1.378 ; +; Cell ; ; 12 ; 0.272 ; 8 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.211 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.241 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|d ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N8 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.164 ; ; uTsu ; 1 ; FF_X101_Y162_N8 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1862: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.265 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.267 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.750 ; 84 ; 0.106 ; 1.220 ; +; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.265 ; 3.267 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.148 ; 1.220 ; FF ; IC ; 1 ; MLABCELL_X101_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~738|datab ; +; 6.265 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X101_Y160_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~738|combout ; +; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2]|d ; +; 6.265 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N29 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.181 ; ; uTsu ; 1 ; FF_X101_Y160_N29 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1863: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.272 ; +; Data Required Time ; 5.625 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.274 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.811 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 10 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.272 ; 3.274 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.510 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.541 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.545 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.244 ; 0.699 ; RR ; IC ; 1 ; MLABCELL_X103_Y148_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~914|dataf ; +; 6.272 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X103_Y148_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~914|combout ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y148_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18]|d ; +; 6.272 ; 0.000 ; FF ; CELL ; 1 ; FF_X103_Y148_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X103_Y148_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y148_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.625 ; 0.182 ; ; uTsu ; 1 ; FF_X103_Y148_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1864: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_d_e_reg|csr_mask[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.594 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.036 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.665 ; 82 ; 0.119 ; 0.840 ; +; Cell ; ; 14 ; 0.457 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.187 ; 79 ; 0.000 ; 2.187 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.599 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.387 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.414 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.420 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.704 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.730 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.736 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.154 ; 0.418 ; FF ; IC ; 1 ; MLABCELL_X76_Y150_N30 ; High Speed ; vx_d_e_reg|i531~22|datac ; +; 6.241 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X76_Y150_N30 ; High Speed ; vx_d_e_reg|i531~22|combout ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y150_N32 ; High Speed ; vx_d_e_reg|csr_mask[22]|d ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X76_Y150_N32 ; High Speed ; vx_d_e_reg|csr_mask[22] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.252 ; 2.187 ; RR ; IC ; 1 ; FF_X76_Y150_N32 ; High Speed ; vx_d_e_reg|csr_mask[22]|clk ; +; 5.252 ; 0.000 ; RR ; CELL ; 1 ; FF_X76_Y150_N32 ; High Speed ; vx_d_e_reg|csr_mask[22] ; +; 5.462 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.594 ; 0.162 ; ; uTsu ; 1 ; FF_X76_Y150_N32 ; ; vx_d_e_reg|csr_mask[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1865: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|b_reg_data[30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.200 ; +; Data Required Time ; 5.553 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.208 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.620 ; 82 ; 0.192 ; 0.884 ; +; Cell ; ; 12 ; 0.461 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.200 ; 3.208 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.938 ; 0.076 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.943 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.135 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.221 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.226 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.431 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.527 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.532 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.189 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.282 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.288 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.172 ; 0.884 ; RR ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; +; 6.200 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; +; 6.200 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; +; 6.200 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.553 ; 0.160 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1866: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.250 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.252 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.739 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.392 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.250 ; 3.252 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.509 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.536 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.541 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.170 ; 0.629 ; RR ; IC ; 1 ; LABCELL_X104_Y160_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~974|datac ; +; 6.250 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X104_Y160_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~974|combout ; +; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE|d ; +; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X104_Y160_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y160_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.167 ; ; uTsu ; 1 ; FF_X104_Y160_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1867: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[19] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.282 ; +; Data Required Time ; 5.635 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.091 ; ; ; ; ; ; +; Data Delay ; 2.227 ; ; ; ; ; ; +; Number of Logic Levels ; ; 3 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.312 ; 76 ; 0.000 ; 2.312 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 3 ; 1.903 ; 85 ; 0.392 ; 0.786 ; +; Cell ; ; 8 ; 0.191 ; 9 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.195 ; 80 ; 0.000 ; 2.195 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.055 ; 3.055 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.055 ; 2.312 ; FF ; IC ; 1 ; FF_X92_Y148_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19]|clk ; +; 4.055 ; 0.000 ; FR ; CELL ; 1 ; FF_X92_Y148_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19] ; +; 6.282 ; 2.227 ; ; ; ; ; ; data path ; +; 4.188 ; 0.133 ; FF ; uTco ; 1 ; FF_X92_Y148_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19]|q ; +; 4.231 ; 0.043 ; FF ; CELL ; 1 ; FF_X92_Y148_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|out_src1_data[19]~la_mlab/laboutt[9] ; +; 4.956 ; 0.725 ; FF ; IC ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|dataf ; +; 4.982 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43|combout ; +; 4.987 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y154_N18 ; High Speed ; vx_decode|out_a_reg_data[0]~43~la_lab/laboutt[13] ; +; 5.773 ; 0.786 ; FF ; IC ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|dataf ; +; 5.799 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44|combout ; +; 5.804 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X75_Y154_N3 ; High Speed ; vx_decode|out_a_reg_data[0]~44~la_lab/laboutt[3] ; +; 6.196 ; 0.392 ; FF ; IC ; 1 ; MLABCELL_X74_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_one|i199~14|datae ; +; 6.282 ; 0.086 ; FF ; CELL ; 1 ; MLABCELL_X74_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_one|i199~14|combout ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19]|d ; +; 6.282 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19] ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.260 ; 2.195 ; RR ; IC ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19]|clk ; +; 5.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y159_N40 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[19] ; +; 5.464 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.635 ; 0.201 ; ; uTsu ; 1 ; FF_X74_Y159_N40 ; ; vx_fetch|VX_Warp_one|real_PC[19] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1868: Setup slack is -0.647 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.647 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.262 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.745 ; 84 ; 0.106 ; 1.215 ; +; Cell ; ; 12 ; 0.396 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.260 ; 3.262 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.143 ; 1.215 ; FF ; IC ; 1 ; MLABCELL_X101_Y160_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~994|datab ; +; 6.260 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X101_Y160_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~994|combout ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2]|d ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X101_Y160_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y160_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y160_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1869: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[7] ; +; To Node ; vx_e_m_reg|csr_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.245 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.252 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.366 ; 79 ; 0.000 ; 2.366 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.694 ; 83 ; 0.116 ; 1.036 ; +; Cell ; ; 14 ; 0.435 ; 13 ; 0.000 ; 0.095 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.993 ; 2.993 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.993 ; 2.366 ; RR ; IC ; 1 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7]|clk ; +; 2.993 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7] ; +; 6.245 ; 3.252 ; ; ; ; ; ; data path ; +; 3.116 ; 0.123 ; FF ; uTco ; 1 ; FF_X51_Y160_N17 ; ; vx_csr_handler|decode_csr_address[7]|q ; +; 3.191 ; 0.075 ; FF ; CELL ; 224 ; FF_X51_Y160_N17 ; High Speed ; vx_csr_handler|decode_csr_address[7]~la_lab/laboutt[11] ; +; 4.227 ; 1.036 ; FF ; IC ; 1 ; MLABCELL_X39_Y145_N27 ; High Speed ; vx_csr_handler|Mux_3~179|datae ; +; 4.322 ; 0.095 ; FR ; CELL ; 1 ; MLABCELL_X39_Y145_N27 ; High Speed ; vx_csr_handler|Mux_3~179|combout ; +; 4.328 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X39_Y145_N27 ; High Speed ; vx_csr_handler|Mux_3~179~la_mlab/laboutt[19] ; +; 4.444 ; 0.116 ; RR ; IC ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|datad ; +; 4.524 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190|combout ; +; 4.529 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X38_Y145_N42 ; High Speed ; vx_csr_handler|Mux_3~190~la_lab/laboutb[9] ; +; 5.045 ; 0.516 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|dataf ; +; 5.071 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254|combout ; +; 5.075 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N48 ; High Speed ; vx_csr_handler|Mux_3~254~la_lab/laboutb[12] ; +; 5.202 ; 0.127 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|datac ; +; 5.285 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.289 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.066 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.092 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.097 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.219 ; 0.122 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; +; 6.245 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; +; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; +; 6.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.462 ; 2.962 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; +; 5.462 ; 0.209 ; ; ; ; ; ; clock pessimism removed ; +; 5.432 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.167 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1870: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|wb[0] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.195 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.197 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.598 ; 81 ; 0.123 ; 0.657 ; +; Cell ; ; 14 ; 0.477 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0] ; +; 6.195 ; 3.197 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N14 ; ; vx_d_e_reg|wb[0]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0]~la_lab/laboutt[9] ; +; 3.776 ; 0.612 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2|datae ; +; 3.860 ; 0.084 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2|combout ; +; 3.865 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2~la_mlab/laboutt[2] ; +; 3.988 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datad ; +; 4.067 ; 0.079 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.072 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.277 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.373 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.378 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.035 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.128 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.134 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.500 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.528 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.532 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.167 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.195 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.195 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.195 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1871: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|wb[0] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.194 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.196 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.597 ; 81 ; 0.123 ; 0.657 ; +; Cell ; ; 14 ; 0.477 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0] ; +; 6.194 ; 3.196 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N14 ; ; vx_d_e_reg|wb[0]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0]~la_lab/laboutt[9] ; +; 3.776 ; 0.612 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2|datae ; +; 3.860 ; 0.084 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2|combout ; +; 3.865 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2~la_mlab/laboutt[2] ; +; 3.988 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datad ; +; 4.067 ; 0.079 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.072 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.277 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.373 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.378 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.035 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.128 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.134 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.500 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.528 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.532 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.166 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.194 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.194 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.194 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1872: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.251 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.253 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.729 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.402 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.251 ; 3.253 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.378 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.458 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.462 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.158 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|datad ; +; 6.251 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|combout ; +; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE|d ; +; 6.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X103_Y161_N49 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1873: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.841 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.476 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.507 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.511 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.221 ; 0.710 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|dataf ; +; 6.248 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X99_Y145_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~694|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X99_Y145_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][22]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1874: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.841 ; 87 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.287 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.501 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.532 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.536 ; 0.004 ; RR ; CELL ; 27 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[6] ; +; 6.221 ; 0.685 ; RR ; IC ; 1 ; LABCELL_X102_Y147_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1013|dataf ; +; 6.248 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y147_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1013|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y147_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X102_Y147_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][21] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1875: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.200 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.076 ; ; ; ; ; ; +; Data Delay ; 3.202 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.743 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 11 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.147 ; 79 ; 0.000 ; 2.147 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.200 ; 3.202 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.337 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; +; 5.367 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; +; 5.371 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; +; 6.173 ; 0.802 ; RR ; IC ; 1 ; LABCELL_X83_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~488|dataf ; +; 6.200 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X83_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~488|combout ; +; 6.200 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8]|d ; +; 6.200 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.422 ; 2.922 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.212 ; 2.147 ; RR ; IC ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8]|clk ; +; 5.212 ; 0.000 ; RR ; CELL ; 1 ; FF_X83_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; +; 5.422 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.392 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.162 ; ; uTsu ; 1 ; FF_X83_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1876: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.234 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.236 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.776 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.234 ; 3.236 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.468 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.499 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.503 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.206 ; 0.703 ; RR ; IC ; 1 ; MLABCELL_X92_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~687|dataf ; +; 6.234 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y163_N12 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~687|combout ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15]|d ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N13 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.167 ; ; uTsu ; 1 ; FF_X92_Y163_N13 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1877: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.227 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.229 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.783 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.227 ; 3.229 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.448 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.475 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.481 ; 0.006 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[3] ; +; 6.200 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|dataf ; +; 6.227 ; 0.027 ; RR ; CELL ; 1 ; LABCELL_X89_Y159_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~841|combout ; +; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|d ; +; 6.227 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y159_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1878: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.250 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.252 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.747 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.384 ; 12 ; 0.000 ; 0.086 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.250 ; 3.252 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.415 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.442 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.447 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.164 ; 0.717 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|datac ; +; 6.250 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~903|combout ; +; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|d ; +; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X107_Y157_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1879: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.668 ; 82 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.334 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.414 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.418 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.154 ; 0.736 ; RR ; IC ; 1 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|datac ; +; 6.236 ; 0.082 ; RR ; CELL ; 2 ; LABCELL_X95_Y164_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~879|combout ; +; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|d ; +; 6.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y164_N14 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.166 ; ; uTsu ; 1 ; FF_X95_Y164_N14 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1880: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.245 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.781 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.245 ; 3.247 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.432 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.464 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.468 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.219 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|dataf ; +; 6.245 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X107_Y150_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~793|combout ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|d ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N28 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y150_N28 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][25] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1881: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.229 ; +; Data Required Time ; 5.583 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.231 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.766 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.229 ; 3.231 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.487 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.515 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.521 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.202 ; 0.681 ; RR ; IC ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|dataf ; +; 6.229 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y161_N18 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~977|combout ; +; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|d ; +; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y161_N19 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.583 ; 0.165 ; ; uTsu ; 1 ; FF_X89_Y161_N19 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1882: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.590 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.790 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.270 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.297 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.303 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[18] ; +; 6.208 ; 0.905 ; RR ; IC ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|dataf ; +; 6.236 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X109_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~260|combout ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|d ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y154_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.590 ; 0.162 ; ; uTsu ; 1 ; FF_X109_Y154_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][4] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1883: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_d_e_reg|b_reg_data[17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.198 ; +; Data Required Time ; 5.552 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.078 ; ; ; ; ; ; +; Data Delay ; 3.200 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.632 ; 82 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.446 ; 14 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.145 ; 79 ; 0.000 ; 2.145 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.198 ; 3.200 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.209 ; 0.089 ; RR ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.364 ; 0.155 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.392 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.397 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.251 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.335 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.340 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.448 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.521 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.525 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.276 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.302 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.308 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.072 ; 0.764 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|datab ; +; 6.198 ; 0.126 ; FR ; CELL ; 1 ; LABCELL_X79_Y152_N33 ; High Speed ; vx_d_e_reg|i385~54|combout ; +; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|d ; +; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.420 ; 2.920 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.210 ; 2.145 ; RR ; IC ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17]|clk ; +; 5.210 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y152_N34 ; High Speed ; vx_d_e_reg|b_reg_data[17] ; +; 5.420 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.390 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.552 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y152_N34 ; ; vx_d_e_reg|b_reg_data[17] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1884: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|csr_address[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.196 ; +; Data Required Time ; 5.550 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.113 ; ; ; ; ; ; +; Data Delay ; 3.204 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.510 ; 78 ; 0.118 ; 0.930 ; +; Cell ; ; 12 ; 0.568 ; 18 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.196 ; 3.204 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.239 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.169 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; +; 6.196 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; +; 6.196 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; +; 6.196 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1885: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.829 ; 87 ; 0.104 ; 1.351 ; +; Cell ; ; 12 ; 0.293 ; 9 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.213 ; 1.351 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|dataf ; +; 6.241 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X101_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~846|combout ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|d ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N55 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X101_Y162_N55 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1886: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|b_reg_data[22] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.201 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.209 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.682 ; 84 ; 0.115 ; 0.944 ; +; Cell ; ; 12 ; 0.402 ; 13 ; 0.000 ; 0.090 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.201 ; 3.209 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.228 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.172 ; 0.944 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|dataf ; +; 6.201 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N33 ; High Speed ; vx_d_e_reg|i385~69|combout ; +; 6.201 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|d ; +; 6.201 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N35 ; High Speed ; vx_d_e_reg|b_reg_data[22] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N35 ; ; vx_d_e_reg|b_reg_data[22] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1887: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|b_reg_data[20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.201 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.209 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.681 ; 84 ; 0.115 ; 0.943 ; +; Cell ; ; 12 ; 0.403 ; 13 ; 0.000 ; 0.090 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.201 ; 3.209 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.228 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.171 ; 0.943 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|dataf ; +; 6.201 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N36 ; High Speed ; vx_d_e_reg|i385~63|combout ; +; 6.201 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|d ; +; 6.201 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N37 ; High Speed ; vx_d_e_reg|b_reg_data[20] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.162 ; ; uTsu ; 1 ; FF_X79_Y149_N37 ; ; vx_d_e_reg|b_reg_data[20] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1888: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[10] ; +; Launch Clock ; clk (INVERTED) ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 1.500 ; ; ; ; ; ; +; Clock Skew ; -0.107 ; ; ; ; ; ; +; Data Delay ; 2.174 ; ; ; ; ; ; +; Number of Logic Levels ; ; 2 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.330 ; 76 ; 0.000 ; 2.330 ; +; Cell ; ; 4 ; 0.743 ; 24 ; 0.000 ; 0.405 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 2 ; 1.870 ; 86 ; 0.742 ; 1.128 ; +; Cell ; ; 6 ; 0.171 ; 8 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.133 ; 6 ; 0.133 ; 0.133 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ +; 1.000 ; 1.000 ; ; ; ; ; ; launch edge time ; +; 4.073 ; 3.073 ; ; ; ; ; ; clock path ; +; 1.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 1.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 1.000 ; 0.000 ; FF ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 1.405 ; 0.405 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 1.483 ; 0.078 ; FF ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 1.483 ; 0.000 ; FF ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 1.743 ; 0.260 ; FF ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 4.073 ; 2.330 ; FF ; IC ; 1 ; FF_X102_Y155_N44 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10]|clk ; +; 4.073 ; 0.000 ; FR ; CELL ; 1 ; FF_X102_Y155_N44 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10] ; +; 6.247 ; 2.174 ; ; ; ; ; ; data path ; +; 4.206 ; 0.133 ; FF ; uTco ; 1 ; FF_X102_Y155_N44 ; ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10]|q ; +; 4.250 ; 0.044 ; FF ; CELL ; 2 ; FF_X102_Y155_N44 ; High Speed ; vx_decode|VX_Context_one|vx_register_file_master|out_src1_data[10]~la_lab/laboutb[9] ; +; 4.992 ; 0.742 ; FF ; IC ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|datad ; +; 5.084 ; 0.092 ; FF ; CELL ; 1 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93|combout ; +; 5.090 ; 0.006 ; FF ; CELL ; 4 ; MLABCELL_X80_Y154_N54 ; High Speed ; vx_decode|out_a_reg_data[0]~93~la_mlab/laboutb[17] ; +; 6.218 ; 1.128 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|dataf ; +; 6.247 ; 0.029 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~41|combout ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|d ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[10] ; +; 5.466 ; 0.204 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.165 ; ; uTsu ; 1 ; FF_X69_Y158_N49 ; ; vx_fetch|VX_Warp_three|real_PC[10] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1889: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.201 ; +; Data Required Time ; 5.555 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.076 ; ; ; ; ; ; +; Data Delay ; 3.203 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.741 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.341 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.147 ; 79 ; 0.000 ; 2.147 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.201 ; 3.203 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.929 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.336 ; 0.407 ; FF ; IC ; 1 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|dataf ; +; 5.363 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8|combout ; +; 5.369 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X90_Y152_N27 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~8~la_mlab/laboutt[19] ; +; 6.173 ; 0.804 ; RR ; IC ; 1 ; LABCELL_X83_Y160_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~273|dataf ; +; 6.201 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X83_Y160_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~273|combout ; +; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y160_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17]|d ; +; 6.201 ; 0.000 ; FF ; CELL ; 1 ; FF_X83_Y160_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.422 ; 2.922 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.212 ; 2.147 ; RR ; IC ; 1 ; FF_X83_Y160_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17]|clk ; +; 5.212 ; 0.000 ; RR ; CELL ; 1 ; FF_X83_Y160_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17] ; +; 5.422 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.392 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.555 ; 0.163 ; ; uTsu ; 1 ; FF_X83_Y160_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[8][17] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1890: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.237 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.043 ; ; ; ; ; ; +; Data Delay ; 3.239 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.723 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.180 ; 79 ; 0.000 ; 2.180 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.237 ; 3.239 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.564 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.592 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.597 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.154 ; 0.557 ; RR ; IC ; 1 ; LABCELL_X97_Y163_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~968|datac ; +; 6.237 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X97_Y163_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~968|combout ; +; 6.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8]|d ; +; 6.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.455 ; 2.955 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.245 ; 2.180 ; RR ; IC ; 1 ; FF_X97_Y163_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8]|clk ; +; 5.245 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y163_N1 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8] ; +; 5.455 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.425 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.166 ; ; uTsu ; 1 ; FF_X97_Y163_N1 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1891: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.268 ; +; Data Required Time ; 5.622 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.011 ; ; ; ; ; ; +; Data Delay ; 3.270 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.199 ; 80 ; 0.000 ; 2.199 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.268 ; 3.270 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.523 ; 0.006 ; FF ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.241 ; 0.718 ; FF ; IC ; 1 ; LABCELL_X108_Y155_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~743|dataf ; +; 6.268 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X108_Y155_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~743|combout ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y155_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7]|d ; +; 6.268 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y155_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.487 ; 2.987 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.264 ; 2.199 ; RR ; IC ; 1 ; FF_X108_Y155_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7]|clk ; +; 5.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y155_N17 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7] ; +; 5.487 ; 0.223 ; ; ; ; ; ; clock pessimism removed ; +; 5.457 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.622 ; 0.165 ; ; uTsu ; 1 ; FF_X108_Y155_N17 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][7] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1892: Setup slack is -0.646 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.257 ; +; Data Required Time ; 5.611 ; +; Slack ; -0.646 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.259 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.749 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.389 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.257 ; 3.259 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.411 ; 0.483 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|datad ; +; 5.491 ; 0.080 ; FR ; CELL ; 1 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27|combout ; +; 5.495 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X95_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~27~la_lab/laboutt[4] ; +; 6.231 ; 0.736 ; RR ; IC ; 1 ; MLABCELL_X98_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~869|dataf ; +; 6.257 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X98_Y163_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~869|combout ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5]|d ; +; 6.257 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X98_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y163_N10 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.611 ; 0.182 ; ; uTsu ; 1 ; FF_X98_Y163_N10 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[27][5] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1893: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.232 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.240 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.620 ; 81 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.494 ; 15 ; 0.000 ; 0.113 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.232 ; 3.240 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.919 ; 0.113 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.925 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[4] ; +; 4.076 ; 0.151 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datac ; +; 4.163 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.169 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.284 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.310 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.315 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.078 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.156 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.162 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.438 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.464 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.470 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.158 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.232 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1894: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++----------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------+ +; Property ; Value ; ++--------------------+-------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.232 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+-------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.234 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.633 ; 81 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.480 ; 15 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.232 ; 3.234 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; +; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.056 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; +; 4.163 ; 0.107 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.169 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.284 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.310 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.315 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.078 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.156 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.162 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.438 ; 0.276 ; FF ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.464 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.470 ; 0.006 ; RR ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.158 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.232 ; 0.074 ; RR ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.232 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.200 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1895: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_d_e_reg|rd[4] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.643 ; 81 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.485 ; 15 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y153_N19 ; ; vx_d_e_reg|rd[4]|q ; +; 3.187 ; 0.068 ; FF ; CELL ; 4 ; FF_X77_Y153_N19 ; High Speed ; vx_d_e_reg|rd[4]~la_lab/laboutt[12] ; +; 3.855 ; 0.668 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datad ; +; 3.929 ; 0.074 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.933 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.056 ; 0.123 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|dataa ; +; 4.163 ; 0.107 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.169 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.284 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.310 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.315 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.078 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.156 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.162 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.876 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.906 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.912 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.172 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.247 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1896: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.602 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.630 ; 81 ; 0.115 ; 0.763 ; +; Cell ; ; 14 ; 0.499 ; 15 ; 0.000 ; 0.113 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.247 ; 3.255 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.919 ; 0.113 ; RF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.925 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[4] ; +; 4.076 ; 0.151 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datac ; +; 4.163 ; 0.087 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.169 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.284 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.310 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.315 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.078 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.156 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.162 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.876 ; 0.714 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|dataf ; +; 5.906 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36|combout ; +; 5.912 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N6 ; High Speed ; vx_fetch|VX_Warp_three|i199~36~la_mlab/laboutt[4] ; +; 6.172 ; 0.260 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|datae ; +; 6.247 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N0 ; High Speed ; vx_fetch|VX_Warp_three|i199~37|combout ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|d ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N1 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.602 ; 0.165 ; ; uTsu ; 1 ; FF_X71_Y158_N1 ; ; vx_fetch|VX_Warp_three|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1897: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++-----------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------+ +; Property ; Value ; ++--------------------+--------------------------+ +; From Node ; vx_d_e_reg|a_reg_data[3] ; +; To Node ; vx_e_m_reg|alu_result[2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.146 ; +; Data Required Time ; 5.501 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+--------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.072 ; ; ; ; ; ; +; Data Delay ; 3.209 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.310 ; 79 ; 0.000 ; 2.310 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.590 ; 81 ; 0.109 ; 0.927 ; +; Cell ; ; 14 ; 0.436 ; 14 ; 0.000 ; 0.127 ; +; uTco ; ; 1 ; 0.183 ; 6 ; 0.183 ; 0.183 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.937 ; 2.937 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.937 ; 2.310 ; RR ; IC ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]|clk ; +; 2.937 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3] ; +; 6.146 ; 3.209 ; ; ; ; ; ; data path ; +; 3.120 ; 0.183 ; FF ; uTco ; 1 ; FF_X79_Y154_N32 ; ; vx_d_e_reg|a_reg_data[3]|q ; +; 3.167 ; 0.047 ; FF ; CELL ; 16 ; FF_X79_Y154_N32 ; High Speed ; vx_d_e_reg|a_reg_data[3]~la_lab/laboutb[1] ; +; 4.094 ; 0.927 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N6 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~27|datad ; +; 4.174 ; 0.080 ; FF ; CELL ; 1 ; LABCELL_X73_Y153_N6 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~27|combout ; +; 4.179 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X73_Y153_N6 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~27~la_lab/laboutt[5] ; +; 4.288 ; 0.109 ; FF ; IC ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|dataa ; +; 4.415 ; 0.127 ; FR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35|combout ; +; 4.419 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X73_Y153_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~35~la_lab/laboutb[12] ; +; 4.636 ; 0.217 ; RR ; IC ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|datae ; +; 4.711 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47|combout ; +; 4.715 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X73_Y151_N48 ; High Speed ; vx_execute|[0].vx_alu|LessThan_1~47~la_lab/laboutb[12] ; +; 5.148 ; 0.433 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|dataf ; +; 5.175 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14|combout ; +; 5.181 ; 0.006 ; FF ; CELL ; 7 ; MLABCELL_X69_Y153_N54 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~14~la_mlab/laboutb[17] ; +; 5.338 ; 0.157 ; FF ; IC ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|dataf ; +; 5.366 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22|combout ; +; 5.371 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X68_Y153_N0 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~22~la_lab/laboutt[1] ; +; 6.118 ; 0.747 ; FF ; IC ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|dataf ; +; 6.146 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X46_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~23|combout ; +; 6.146 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|d ; +; 6.146 ; 0.000 ; FF ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N43 ; High Speed ; vx_e_m_reg|alu_result[2] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.501 ; 0.166 ; ; uTsu ; 1 ; FF_X46_Y153_N43 ; ; vx_e_m_reg|alu_result[2] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1898: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|wb[0] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.192 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.194 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.595 ; 81 ; 0.123 ; 0.657 ; +; Cell ; ; 14 ; 0.477 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0] ; +; 6.192 ; 3.194 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N14 ; ; vx_d_e_reg|wb[0]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N14 ; High Speed ; vx_d_e_reg|wb[0]~la_lab/laboutt[9] ; +; 3.776 ; 0.612 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2|datae ; +; 3.860 ; 0.084 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2|combout ; +; 3.865 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X80_Y153_N3 ; High Speed ; vx_forwarding|src1_exe_fwd~2~la_mlab/laboutt[2] ; +; 3.988 ; 0.123 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datad ; +; 4.067 ; 0.079 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.072 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.277 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.373 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.378 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.035 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.128 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.134 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.500 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.528 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.532 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.164 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.192 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1899: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.222 ; +; Data Required Time ; 5.577 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.053 ; ; ; ; ; ; +; Data Delay ; 3.224 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.765 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.170 ; 79 ; 0.000 ; 2.170 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.222 ; 3.224 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.405 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; +; 5.485 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; +; 5.490 ; 0.005 ; RR ; CELL ; 11 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[5] ; +; 6.195 ; 0.705 ; RR ; IC ; 1 ; LABCELL_X89_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~744|dataf ; +; 6.222 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X89_Y162_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~744|combout ; +; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8]|d ; +; 6.222 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.445 ; 2.945 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.235 ; 2.170 ; RR ; IC ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8]|clk ; +; 5.235 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y162_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; +; 5.445 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.415 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.577 ; 0.162 ; ; uTsu ; 1 ; FF_X89_Y162_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1900: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.249 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.251 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 86 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.249 ; 3.251 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.879 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.904 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.909 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.532 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.560 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.565 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.169 ; 0.604 ; RR ; IC ; 1 ; LABCELL_X104_Y147_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~978|datad ; +; 6.249 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y147_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~978|combout ; +; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18]|d ; +; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y147_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y147_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][18] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1901: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.250 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.252 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.776 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.354 ; 11 ; 0.000 ; 0.094 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.250 ; 3.252 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.487 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.516 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.521 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.156 ; 0.635 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~647|datac ; +; 6.250 ; 0.094 ; RR ; CELL ; 1 ; MLABCELL_X105_Y159_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~647|combout ; +; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7]|d ; +; 6.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N41 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.169 ; ; uTsu ; 1 ; FF_X105_Y159_N41 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1902: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.250 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.252 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.794 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.336 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.250 ; 3.252 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.524 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.552 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.557 ; 0.005 ; RR ; CELL ; 20 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[10] ; +; 6.222 ; 0.665 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|dataf ; +; 6.250 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~985|combout ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE|d ; +; 6.250 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.168 ; ; uTsu ; 1 ; FF_X107_Y150_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1903: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.227 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.048 ; ; ; ; ; ; +; Data Delay ; 3.229 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.773 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.227 ; 3.229 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.446 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.473 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.477 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.199 ; 0.722 ; RR ; IC ; 1 ; MLABCELL_X92_Y160_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~561|dataf ; +; 6.227 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y160_N48 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~561|combout ; +; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17]|d ; +; 6.227 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17]|clk ; +; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y160_N50 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; +; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.162 ; ; uTsu ; 1 ; FF_X92_Y160_N50 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1904: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.769 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.446 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.473 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.479 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.208 ; 0.729 ; RR ; IC ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|dataf ; +; 6.236 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|combout ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|d ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y161_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1905: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.772 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.344 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.450 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.477 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.482 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.209 ; 0.727 ; RR ; IC ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|dataf ; +; 6.236 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|combout ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|d ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y162_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1906: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.245 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.247 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.799 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.245 ; 3.247 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.444 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.479 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.218 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|dataf ; +; 6.245 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~910|combout ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|d ; +; 6.245 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.164 ; ; uTsu ; 1 ; FF_X102_Y161_N4 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1907: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.034 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.801 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.326 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.189 ; 79 ; 0.000 ; 2.189 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.498 ; 0.623 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|dataf ; +; 5.526 ; 0.028 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30|combout ; +; 5.532 ; 0.006 ; RR ; CELL ; 12 ; MLABCELL_X96_Y154_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~30~la_mlab/laboutt[11] ; +; 6.219 ; 0.687 ; RR ; IC ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|dataf ; +; 6.246 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X95_Y144_N30 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~986|combout ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|d ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.464 ; 2.964 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.254 ; 2.189 ; RR ; IC ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26]|clk ; +; 5.254 ; 0.000 ; RR ; CELL ; 1 ; FF_X95_Y144_N31 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; +; 5.464 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.434 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.167 ; ; uTsu ; 1 ; FF_X95_Y144_N31 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][26] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1908: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.232 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.234 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.767 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.232 ; 3.234 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.445 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.477 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.205 ; 0.728 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|dataf ; +; 6.232 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|combout ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|d ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1909: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.258 ; +; Data Required Time ; 5.613 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.260 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.728 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.411 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.258 ; 3.260 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.432 ; 0.568 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|dataf ; +; 5.464 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24|combout ; +; 5.468 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y154_N54 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~24~la_lab/laboutb[16] ; +; 6.166 ; 0.698 ; RR ; IC ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|datac ; +; 6.258 ; 0.092 ; RR ; CELL ; 1 ; MLABCELL_X109_Y152_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~772|combout ; +; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|d ; +; 6.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X109_Y152_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.613 ; 0.176 ; ; uTsu ; 1 ; FF_X109_Y152_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][4] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1910: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.752 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.372 ; 11 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.404 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.481 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.485 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.217 ; 0.732 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|dataf ; +; 6.243 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X105_Y159_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~583|combout ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|d ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][7] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1911: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.039 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.770 ; 85 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.351 ; 11 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.184 ; 79 ; 0.000 ; 2.184 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.375 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.452 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.457 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; +; 6.214 ; 0.757 ; RR ; IC ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|dataf ; +; 6.241 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y143_N51 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~607|combout ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|d ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.459 ; 2.959 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.249 ; 2.184 ; RR ; IC ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31]|clk ; +; 5.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y143_N52 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; +; 5.459 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.429 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y143_N52 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][31] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1912: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.249 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.251 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.756 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.374 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.249 ; 3.251 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.276 ; 0.448 ; FF ; IC ; 1 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|dataf ; +; 5.306 ; 0.030 ; FR ; CELL ; 2 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15|combout ; +; 5.310 ; 0.004 ; RR ; CELL ; 31 ; LABCELL_X89_Y152_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~15~la_lab/laboutb[16] ; +; 6.163 ; 0.853 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|datac ; +; 6.249 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X101_Y161_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~491|combout ; +; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|d ; +; 6.249 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N25 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y161_N25 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[15][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1913: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.731 ; 84 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.391 ; 12 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.898 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.923 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.928 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.437 ; 0.509 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|datad ; +; 5.517 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23|combout ; +; 5.521 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X99_Y153_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~23~la_lab/laboutt[4] ; +; 6.213 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~764|dataf ; +; 6.241 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~764|combout ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28]|d ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y144_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[23][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1914: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.225 ; +; Data Required Time ; 5.580 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.227 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.763 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.343 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.225 ; 3.227 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.477 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.583 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.655 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.660 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.754 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.780 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.784 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.911 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.936 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.941 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.533 ; 0.592 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|dataf ; +; 5.564 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31|combout ; +; 5.569 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X95_Y154_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~31~la_lab/laboutt[7] ; +; 6.197 ; 0.628 ; RR ; IC ; 1 ; LABCELL_X89_Y159_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1001|dataf ; +; 6.225 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X89_Y159_N27 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~1001|combout ; +; 6.225 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9]|d ; +; 6.225 ; 0.000 ; FF ; CELL ; 1 ; FF_X89_Y159_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X89_Y159_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X89_Y159_N29 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.580 ; 0.164 ; ; uTsu ; 1 ; FF_X89_Y159_N29 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[31][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1915: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.610 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.720 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.416 ; 13 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.491 ; 0.565 ; RR ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.517 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.522 ; 0.005 ; FF ; CELL ; 4 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[6] ; +; 6.169 ; 0.647 ; FF ; IC ; 1 ; MLABCELL_X96_Y161_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~742|datac ; +; 6.255 ; 0.086 ; FR ; CELL ; 1 ; MLABCELL_X96_Y161_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~742|combout ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y161_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6]|d ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y161_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X96_Y161_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X96_Y161_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.610 ; 0.182 ; ; uTsu ; 1 ; FF_X96_Y161_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][6] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1916: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.114 ; +; Data Required Time ; 5.469 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.116 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.657 ; 85 ; 0.119 ; 1.148 ; +; Cell ; ; 10 ; 0.338 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.114 ; 3.116 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.966 ; 0.004 ; FF ; CELL ; 44 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[4] ; +; 6.114 ; 1.148 ; FF ; IC ; 1 ; FF_X69_Y159_N46 ; High Speed ; vx_f_d_reg|curr_PC[9]|ena ; +; 6.114 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N46 ; High Speed ; vx_f_d_reg|curr_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N46 ; High Speed ; vx_f_d_reg|curr_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N46 ; High Speed ; vx_f_d_reg|curr_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.469 ; 0.026 ; ; uTsu ; 1 ; FF_X69_Y159_N46 ; ; vx_f_d_reg|curr_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1917: Setup slack is -0.645 (VIOLATED) +=============================================================================== ++---------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------+ +; From Node ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; +; To Node ; vx_e_m_reg|alu_result[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.147 ; +; Data Required Time ; 5.502 ; +; Slack ; -0.645 (VIOLATED) ; ++--------------------+------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.083 ; ; ; ; ; ; +; Data Delay ; 3.199 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.321 ; 79 ; 0.000 ; 2.321 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.582 ; 81 ; 0.129 ; 0.816 ; +; Cell ; ; 14 ; 0.494 ; 15 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.123 ; 4 ; 0.123 ; 0.123 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.172 ; 79 ; 0.000 ; 2.172 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.948 ; 2.948 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.948 ; 2.321 ; RR ; IC ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|clk ; +; 2.948 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE ; +; 6.147 ; 3.199 ; ; ; ; ; ; data path ; +; 3.071 ; 0.123 ; FF ; uTco ; 1 ; FF_X79_Y153_N40 ; ; vx_d_e_reg|b_reg_data[0]~DUPLICATE|q ; +; 3.115 ; 0.044 ; FF ; CELL ; 2 ; FF_X79_Y153_N40 ; High Speed ; vx_d_e_reg|b_reg_data[0]~DUPLICATE~la_lab/laboutb[6] ; +; 3.931 ; 0.816 ; FF ; IC ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|dataf ; +; 3.958 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20|combout ; +; 3.964 ; 0.006 ; FF ; CELL ; 70 ; MLABCELL_X72_Y153_N9 ; High Speed ; vx_execute|[0].vx_alu|ALU_in2[0]~20~la_mlab/laboutt[7] ; +; 4.515 ; 0.551 ; FF ; IC ; 1 ; MLABCELL_X69_Y150_N36 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~11|datad ; +; 4.607 ; 0.092 ; FR ; CELL ; 1 ; MLABCELL_X69_Y150_N36 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~11|combout ; +; 4.613 ; 0.006 ; RR ; CELL ; 3 ; MLABCELL_X69_Y150_N36 ; High Speed ; vx_execute|[0].vx_alu|shift_right_1~11~la_mlab/laboutb[5] ; +; 4.814 ; 0.201 ; RR ; IC ; 1 ; MLABCELL_X67_Y150_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~38|datae ; +; 4.887 ; 0.073 ; RR ; CELL ; 1 ; MLABCELL_X67_Y150_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~38|combout ; +; 4.893 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X67_Y150_N18 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~38~la_mlab/laboutt[12] ; +; 5.022 ; 0.129 ; RR ; IC ; 1 ; LABCELL_X68_Y150_N36 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~39|datad ; +; 5.094 ; 0.072 ; RR ; CELL ; 1 ; LABCELL_X68_Y150_N36 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~39|combout ; +; 5.098 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X68_Y150_N36 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~39~la_lab/laboutb[4] ; +; 5.392 ; 0.294 ; RR ; IC ; 1 ; MLABCELL_X69_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~40|datac ; +; 5.478 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~40|combout ; +; 5.483 ; 0.005 ; RR ; CELL ; 1 ; MLABCELL_X69_Y153_N42 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~40~la_mlab/laboutb[8] ; +; 6.074 ; 0.591 ; RR ; IC ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|datad ; +; 6.147 ; 0.073 ; RR ; CELL ; 1 ; LABCELL_X46_Y153_N30 ; High Speed ; vx_execute|[0].vx_alu|Mux_31~42|combout ; +; 6.147 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|d ; +; 6.147 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; ++---------+---------+----+------+--------+-----------------------+------------+-----------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.365 ; 2.865 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.237 ; 2.172 ; RR ; IC ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5]|clk ; +; 5.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X46_Y153_N31 ; High Speed ; vx_e_m_reg|alu_result[5] ; +; 5.365 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.335 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.502 ; 0.167 ; ; uTsu ; 1 ; FF_X46_Y153_N31 ; ; vx_e_m_reg|alu_result[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1918: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.192 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.200 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.612 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.127 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.192 ; 3.200 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[4] ; +; 4.089 ; 0.150 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datac ; +; 4.176 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.182 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.297 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.323 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.328 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.048 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.126 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.132 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.498 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.526 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.530 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.164 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.192 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1919: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.193 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.201 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.613 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.127 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.193 ; 3.201 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[4] ; +; 4.089 ; 0.150 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datac ; +; 4.176 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.182 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.297 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.323 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.328 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.048 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.126 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.132 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.498 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.526 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.530 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.165 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.193 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.193 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.193 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1920: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.192 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.200 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.625 ; 82 ; 0.127 ; 0.657 ; +; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.192 ; 3.200 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; FF ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.676 ; 0.514 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; +; 3.759 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.763 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 4.090 ; 0.327 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataf ; +; 4.118 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.123 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.250 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.371 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.376 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.033 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.126 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.132 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.498 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.526 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.530 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.164 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.192 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1921: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.193 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.201 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.626 ; 82 ; 0.127 ; 0.657 ; +; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.193 ; 3.201 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; FF ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.676 ; 0.514 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; +; 3.759 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.763 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 4.090 ; 0.327 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataf ; +; 4.118 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.123 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.250 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.371 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.376 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.033 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.126 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.132 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.498 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.526 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.530 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.165 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.193 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.193 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.193 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1922: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.105 ; +; Data Required Time ; 5.461 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.024 ; ; ; ; ; ; +; Data Delay ; 3.107 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.601 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.199 ; 80 ; 0.000 ; 2.199 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.105 ; 3.107 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.105 ; 0.256 ; FF ; IC ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11]|sload ; +; 6.105 ; 0.000 ; FF ; CELL ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.474 ; 2.974 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.264 ; 2.199 ; RR ; IC ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11]|clk ; +; 5.264 ; 0.000 ; RR ; CELL ; 1 ; FF_X72_Y161_N28 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[11] ; +; 5.474 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.444 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.461 ; 0.017 ; ; uTsu ; 1 ; FF_X72_Y161_N28 ; ; vx_fetch|VX_Warp_zero|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1923: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.099 ; +; Data Required Time ; 5.455 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.101 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.595 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.099 ; 3.101 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.099 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]|sload ; +; 6.099 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N7 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.455 ; 0.016 ; ; uTsu ; 1 ; FF_X71_Y160_N7 ; ; vx_fetch|VX_Warp_zero|real_PC[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1924: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.099 ; +; Data Required Time ; 5.455 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.101 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.595 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.099 ; 3.101 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.099 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5]|sload ; +; 6.099 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N26 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[5] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.455 ; 0.016 ; ; uTsu ; 1 ; FF_X71_Y160_N26 ; ; vx_fetch|VX_Warp_zero|real_PC[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1925: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.671 ; 82 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.452 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.370 ; 0.482 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|datad ; +; 5.450 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29|combout ; +; 5.454 ; 0.004 ; RR ; CELL ; 18 ; LABCELL_X95_Y153_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~29~la_lab/laboutt[12] ; +; 6.150 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|datad ; +; 6.243 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X103_Y161_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~942|combout ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]|d ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N50 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X103_Y161_N50 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[29][14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1926: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_d_e_reg|csr_address[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.194 ; +; Data Required Time ; 5.550 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.196 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.622 ; 82 ; 0.192 ; 0.922 ; +; Cell ; ; 12 ; 0.452 ; 14 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.194 ; 3.196 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.810 ; 0.646 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datae ; +; 3.896 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.901 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[15] ; +; 4.093 ; 0.192 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datac ; +; 4.179 ; 0.086 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.184 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.389 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.485 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.490 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.147 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.240 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.245 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.167 ; 0.922 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; +; 6.194 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; +; 6.194 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; +; 6.194 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1927: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.232 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.234 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.765 ; 85 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.232 ; 3.234 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.446 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.477 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.481 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.205 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|dataf ; +; 6.232 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|combout ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|d ; +; 6.232 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1928: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.255 ; +; Data Required Time ; 5.611 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.257 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.689 ; 83 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.446 ; 14 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.255 ; 3.257 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.406 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.483 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.487 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.175 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|datac ; +; 6.255 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|combout ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|d ; +; 6.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1929: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.778 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.345 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.865 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.445 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.472 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.477 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.216 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|dataf ; +; 6.243 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|combout ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|d ; +; 6.243 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X108_Y157_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1930: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.221 ; +; Data Required Time ; 5.577 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.058 ; ; ; ; ; ; +; Data Delay ; 3.223 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.760 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.165 ; 79 ; 0.000 ; 2.165 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.221 ; 3.223 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.318 ; 0.454 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|dataf ; +; 5.347 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29|combout ; +; 5.351 ; 0.004 ; RR ; CELL ; 21 ; LABCELL_X95_Y153_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~29~la_lab/laboutb[14] ; +; 6.195 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|dataf ; +; 6.221 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X88_Y164_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~937|combout ; +; 6.221 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|d ; +; 6.221 ; 0.000 ; FF ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.440 ; 2.940 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.230 ; 2.165 ; RR ; IC ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9]|clk ; +; 5.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X88_Y164_N23 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; +; 5.440 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.410 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.577 ; 0.167 ; ; uTsu ; 1 ; FF_X88_Y164_N23 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[29][9] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1931: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.718 ; 84 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.407 ; 13 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.155 ; 0.304 ; FF ; IC ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|dataf ; +; 5.184 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9|combout ; +; 5.188 ; 0.004 ; RR ; CELL ; 32 ; LABCELL_X91_Y153_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~9~la_lab/laboutb[16] ; +; 6.153 ; 0.965 ; RR ; IC ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|datad ; +; 6.244 ; 0.091 ; RR ; CELL ; 1 ; MLABCELL_X107_Y158_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~288|combout ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|d ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y158_N20 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y158_N20 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[9][0] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1932: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.223 ; +; Data Required Time ; 5.579 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.225 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.758 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.346 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.223 ; 3.225 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.852 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.442 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.471 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.477 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[13] ; +; 6.196 ; 0.719 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|dataf ; +; 6.223 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~648|combout ; +; 6.223 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|d ; +; 6.223 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N4 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N4 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1933: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|b_reg_data[30] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.198 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.206 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.509 ; 78 ; 0.118 ; 0.929 ; +; Cell ; ; 12 ; 0.571 ; 18 ; 0.000 ; 0.130 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.198 ; 3.206 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.091 ; 0.152 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.221 ; 0.130 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.226 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.344 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.455 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.460 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.143 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.234 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.240 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.169 ; 0.929 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|dataf ; +; 6.198 ; 0.029 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N57 ; High Speed ; vx_d_e_reg|i385~93|combout ; +; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|d ; +; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N58 ; High Speed ; vx_d_e_reg|b_reg_data[30] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N58 ; ; vx_d_e_reg|b_reg_data[30] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1934: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.823 ; 87 ; 0.104 ; 1.317 ; +; Cell ; ; 12 ; 0.301 ; 9 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.218 ; 1.317 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~363|dataf ; +; 6.244 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~363|combout ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11]|d ; +; 6.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N34 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N34 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[11][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1935: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.233 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.047 ; ; ; ; ; ; +; Data Delay ; 3.235 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.721 ; 84 ; 0.104 ; 1.228 ; +; Cell ; ; 12 ; 0.392 ; 12 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.176 ; 79 ; 0.000 ; 2.176 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.233 ; 3.235 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.116 ; 1.228 ; FF ; IC ; 1 ; MLABCELL_X92_Y163_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~47|datab ; +; 6.233 ; 0.117 ; FR ; CELL ; 1 ; MLABCELL_X92_Y163_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~47|combout ; +; 6.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15]|d ; +; 6.233 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.451 ; 2.951 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.241 ; 2.176 ; RR ; IC ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15]|clk ; +; 5.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y163_N5 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; +; 5.451 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.421 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.168 ; ; uTsu ; 1 ; FF_X92_Y163_N5 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[1][15] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1936: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.790 ; 86 ; 0.106 ; 1.300 ; +; Cell ; ; 12 ; 0.351 ; 11 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.138 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.259 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|d ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1937: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.778 ; 86 ; 0.106 ; 1.275 ; +; Cell ; ; 12 ; 0.347 ; 11 ; 0.000 ; 0.117 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.126 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|datab ; +; 6.243 ; 0.117 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~779|combout ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|d ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N10 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X105_Y159_N10 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[24][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1938: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.259 ; +; Data Required Time ; 5.615 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.261 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.790 ; 86 ; 0.106 ; 1.300 ; +; Cell ; ; 12 ; 0.351 ; 11 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.259 ; 3.261 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.138 ; 1.300 ; FF ; IC ; 1 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|datab ; +; 6.259 ; 0.121 ; FR ; CELL ; 2 ; MLABCELL_X103_Y160_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~834|combout ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|d ; +; 6.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y160_N43 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.615 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y160_N43 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][2]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1939: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.240 ; +; Data Required Time ; 5.596 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.242 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.862 ; 88 ; 0.106 ; 1.372 ; +; Cell ; ; 12 ; 0.260 ; 8 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.240 ; 3.242 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.210 ; 1.372 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|dataf ; +; 6.240 ; 0.030 ; FR ; CELL ; 1 ; MLABCELL_X101_Y162_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~395|combout ; +; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|d ; +; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.596 ; 0.166 ; ; uTsu ; 1 ; FF_X101_Y162_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[12][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1940: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.597 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.849 ; 88 ; 0.104 ; 1.378 ; +; Cell ; ; 12 ; 0.272 ; 8 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.803 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.828 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.833 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 6.211 ; 1.378 ; FF ; IC ; 1 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|dataf ; +; 6.241 ; 0.030 ; FF ; CELL ; 2 ; MLABCELL_X101_Y162_N6 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~686|combout ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|d ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y162_N7 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.597 ; 0.167 ; ; uTsu ; 1 ; FF_X101_Y162_N7 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][14]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1941: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|b_reg_data[21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.198 ; +; Data Required Time ; 5.554 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.069 ; ; ; ; ; ; +; Data Delay ; 3.206 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.678 ; 84 ; 0.115 ; 0.940 ; +; Cell ; ; 12 ; 0.403 ; 13 ; 0.000 ; 0.090 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.148 ; 79 ; 0.000 ; 2.148 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.198 ; 3.206 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.139 ; 0.138 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datad ; +; 4.229 ; 0.090 ; RF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.235 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.350 ; 0.115 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.376 ; 0.026 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.381 ; 0.005 ; FF ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.144 ; 0.763 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.222 ; 0.078 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.228 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 6.168 ; 0.940 ; FF ; IC ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|dataf ; +; 6.198 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X79_Y149_N42 ; High Speed ; vx_d_e_reg|i385~66|combout ; +; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|d ; +; 6.198 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.423 ; 2.923 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.213 ; 2.148 ; RR ; IC ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21]|clk ; +; 5.213 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y149_N43 ; High Speed ; vx_d_e_reg|b_reg_data[21] ; +; 5.423 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.393 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.554 ; 0.161 ; ; uTsu ; 1 ; FF_X79_Y149_N43 ; ; vx_d_e_reg|b_reg_data[21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1942: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.236 ; +; Data Required Time ; 5.592 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.041 ; ; ; ; ; ; +; Data Delay ; 3.238 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.759 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.358 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.236 ; 3.238 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.366 ; 0.440 ; RR ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; +; 5.394 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; +; 5.398 ; 0.004 ; FF ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; +; 6.209 ; 0.811 ; FF ; IC ; 1 ; MLABCELL_X98_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~646|dataf ; +; 6.236 ; 0.027 ; FF ; CELL ; 1 ; MLABCELL_X98_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~646|combout ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6]|d ; +; 6.236 ; 0.000 ; FF ; CELL ; 1 ; FF_X98_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X98_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6]|clk ; +; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X98_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6] ; +; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.592 ; 0.165 ; ; uTsu ; 1 ; FF_X98_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][6] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1943: Setup slack is -0.644 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.239 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.644 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.038 ; ; ; ; ; ; +; Data Delay ; 3.241 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.761 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.359 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.185 ; 79 ; 0.000 ; 2.185 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.239 ; 3.241 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.918 ; 0.006 ; RR ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.462 ; 0.544 ; RR ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.488 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.494 ; 0.006 ; FF ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.211 ; 0.717 ; FF ; IC ; 1 ; MLABCELL_X107_Y154_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~900|dataf ; +; 6.239 ; 0.028 ; FF ; CELL ; 1 ; MLABCELL_X107_Y154_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~900|combout ; +; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y154_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4]|d ; +; 6.239 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y154_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.460 ; 2.960 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.250 ; 2.185 ; RR ; IC ; 1 ; FF_X107_Y154_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4]|clk ; +; 5.250 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y154_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4] ; +; 5.460 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.430 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.165 ; ; uTsu ; 1 ; FF_X107_Y154_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][4] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1944: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.190 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.198 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.610 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.462 ; 14 ; 0.000 ; 0.127 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.190 ; 3.198 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.806 ; 0.627 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|dataa ; +; 3.933 ; 0.127 ; RR ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.939 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[4] ; +; 4.089 ; 0.150 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datac ; +; 4.176 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.182 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.297 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.323 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.328 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.048 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.126 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.132 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.498 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.526 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.530 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.162 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.190 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.190 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.190 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1945: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.192 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.200 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.640 ; 83 ; 0.135 ; 0.657 ; +; Cell ; ; 14 ; 0.434 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.192 ; 3.200 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.675 ; 0.496 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|datac ; +; 3.755 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; +; 3.760 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; +; 3.895 ; 0.135 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; +; 3.921 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.926 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.277 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.370 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.375 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.032 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.125 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.131 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.497 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.525 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.529 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.164 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.192 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1946: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.191 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.199 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.639 ; 82 ; 0.135 ; 0.657 ; +; Cell ; ; 14 ; 0.434 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.191 ; 3.199 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.675 ; 0.496 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|datac ; +; 3.755 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; +; 3.760 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; +; 3.895 ; 0.135 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; +; 3.921 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.926 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.277 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.370 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.375 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.032 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.125 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.131 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.497 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.525 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.529 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.163 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.191 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.191 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.191 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1947: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.190 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.198 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.623 ; 82 ; 0.127 ; 0.657 ; +; Cell ; ; 14 ; 0.449 ; 14 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.190 ; 3.198 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; FF ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.676 ; 0.514 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; +; 3.759 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.763 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 4.090 ; 0.327 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataf ; +; 4.118 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.123 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.250 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.371 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.376 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.033 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.126 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.132 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.498 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.526 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.530 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.162 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.190 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.190 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.190 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1948: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[1] ; +; To Node ; vx_d_e_reg|upper_immed[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.191 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.193 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.534 ; 79 ; 0.127 ; 0.657 ; +; Cell ; ; 14 ; 0.537 ; 17 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1] ; +; 6.191 ; 3.193 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N10 ; ; vx_d_e_reg|rd[1]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]~la_lab/laboutt[6] ; +; 3.760 ; 0.596 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|datad ; +; 3.850 ; 0.090 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.856 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.010 ; 0.154 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.117 ; 0.107 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.122 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.249 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.370 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.375 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.032 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.125 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.131 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.497 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.525 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.529 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.163 ; 0.634 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|dataf ; +; 6.191 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N42 ; High Speed ; vx_d_e_reg|i486~6|combout ; +; 6.191 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|d ; +; 6.191 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N43 ; High Speed ; vx_d_e_reg|upper_immed[6] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N43 ; ; vx_d_e_reg|upper_immed[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1949: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[1] ; +; To Node ; vx_d_e_reg|upper_immed[5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.192 ; +; Data Required Time ; 5.549 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.194 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.535 ; 79 ; 0.127 ; 0.657 ; +; Cell ; ; 14 ; 0.537 ; 17 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1] ; +; 6.192 ; 3.194 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N10 ; ; vx_d_e_reg|rd[1]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]~la_lab/laboutt[6] ; +; 3.760 ; 0.596 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|datad ; +; 3.850 ; 0.090 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.856 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.010 ; 0.154 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.117 ; 0.107 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.122 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.249 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.370 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.375 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.032 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.125 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.131 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.497 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.525 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.529 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.164 ; 0.635 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|dataf ; +; 6.192 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N39 ; High Speed ; vx_d_e_reg|i486~5|combout ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|d ; +; 6.192 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N40 ; High Speed ; vx_d_e_reg|upper_immed[5] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.549 ; 0.162 ; ; uTsu ; 1 ; FF_X81_Y151_N40 ; ; vx_d_e_reg|upper_immed[5] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1950: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_d_e_reg|csr_mask[10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.230 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.232 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.670 ; 83 ; 0.116 ; 0.788 ; +; Cell ; ; 14 ; 0.441 ; 14 ; 0.000 ; 0.107 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.230 ; 3.232 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.492 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.518 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.524 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.123 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|datab ; +; 6.230 ; 0.107 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N12 ; High Speed ; vx_d_e_reg|i531~10|combout ; +; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|d ; +; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N14 ; High Speed ; vx_d_e_reg|csr_mask[10] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N14 ; ; vx_d_e_reg|csr_mask[10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1951: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.099 ; +; Data Required Time ; 5.456 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+--------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.101 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.595 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.099 ; 3.101 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.099 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE|sload ; +; 6.099 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N8 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.456 ; 0.017 ; ; uTsu ; 1 ; FF_X71_Y160_N8 ; ; vx_fetch|VX_Warp_zero|real_PC[7]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1952: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.263 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.745 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.261 ; 3.263 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.244 ; 0.347 ; FF ; IC ; 1 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|datad ; +; 5.323 ; 0.079 ; FR ; CELL ; 2 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|combout ; +; 5.327 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4~la_lab/laboutb[8] ; +; 6.174 ; 0.847 ; RR ; IC ; 1 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|datac ; +; 6.261 ; 0.087 ; RR ; CELL ; 2 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|combout ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE|d ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+---------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N31 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y148_N31 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1953: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.242 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.033 ; ; ; ; ; ; +; Data Delay ; 3.244 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.788 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.334 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.190 ; 79 ; 0.000 ; 2.190 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.242 ; 3.244 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.429 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.505 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.509 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.213 ; 0.704 ; RR ; IC ; 1 ; MLABCELL_X105_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~810|dataf ; +; 6.242 ; 0.029 ; RF ; CELL ; 1 ; MLABCELL_X105_Y157_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~810|combout ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10]|d ; +; 6.242 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.465 ; 2.965 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.255 ; 2.190 ; RR ; IC ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10]|clk ; +; 5.255 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y157_N44 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; +; 5.465 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.435 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.164 ; ; uTsu ; 1 ; FF_X105_Y157_N44 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1954: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.261 ; +; Data Required Time ; 5.618 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.026 ; ; ; ; ; ; +; Data Delay ; 3.263 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.745 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.396 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.197 ; 80 ; 0.000 ; 2.197 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.261 ; 3.263 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.244 ; 0.347 ; FF ; IC ; 1 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|datad ; +; 5.323 ; 0.079 ; FR ; CELL ; 2 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4|combout ; +; 5.327 ; 0.004 ; RR ; CELL ; 23 ; LABCELL_X87_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~4~la_lab/laboutb[8] ; +; 6.174 ; 0.847 ; RR ; IC ; 1 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|datac ; +; 6.261 ; 0.087 ; RR ; CELL ; 2 ; MLABCELL_X101_Y148_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~146|combout ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]|d ; +; 6.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.472 ; 2.972 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.262 ; 2.197 ; RR ; IC ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18]|clk ; +; 5.262 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y148_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; +; 5.472 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.442 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.618 ; 0.176 ; ; uTsu ; 1 ; FF_X101_Y148_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[4][18] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1955: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.338 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.468 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.499 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.503 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.219 ; 0.716 ; RR ; IC ; 1 ; LABCELL_X99_Y145_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~692|dataf ; +; 6.247 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X99_Y145_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~692|combout ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20]|d ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y145_N46 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X99_Y145_N46 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][20] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1956: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.790 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.888 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.367 ; 0.479 ; FF ; IC ; 1 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|dataf ; +; 5.396 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21|combout ; +; 5.400 ; 0.004 ; RR ; CELL ; 20 ; LABCELL_X93_Y154_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~21~la_lab/laboutt[12] ; +; 6.218 ; 0.818 ; RR ; IC ; 1 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|dataf ; +; 6.247 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X107_Y150_N12 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~697|combout ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE|d ; +; 6.247 ; 0.000 ; FF ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; ++---------+---------+----+------+--------+------------------------+------------+----------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y150_N13 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y150_N13 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[21][25]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1957: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.234 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.236 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.788 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.234 ; 3.236 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.444 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.471 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.477 ; 0.006 ; RR ; CELL ; 14 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[17] ; +; 6.206 ; 0.729 ; RR ; IC ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|dataf ; +; 6.234 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y161_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1005|combout ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|d ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y161_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.168 ; ; uTsu ; 1 ; FF_X93_Y161_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][13] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1958: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.234 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.236 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.791 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.324 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.234 ; 3.236 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.448 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.475 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.480 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.207 ; 0.727 ; RR ; IC ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|dataf ; +; 6.234 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X97_Y162_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~837|combout ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|d ; +; 6.234 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y162_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X97_Y162_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][5] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1959: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.230 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.232 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.786 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.230 ; 3.232 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.443 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.470 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.475 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.203 ; 0.728 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|dataf ; +; 6.230 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N30 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~988|combout ; +; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|d ; +; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N32 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.163 ; ; uTsu ; 1 ; FF_X91_Y144_N32 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1960: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.244 ; +; Data Required Time ; 5.601 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.246 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.789 ; 86 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.076 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.244 ; 3.246 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.838 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.371 ; 0.533 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.447 ; 0.076 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.451 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.217 ; 0.766 ; RR ; IC ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|dataf ; +; 6.244 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X99_Y144_N33 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~821|combout ; +; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|d ; +; 6.244 ; 0.000 ; FF ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X99_Y144_N35 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.601 ; 0.164 ; ; uTsu ; 1 ; FF_X99_Y144_N35 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][21] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1961: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.603 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.048 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.825 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.301 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.175 ; 79 ; 0.000 ; 2.175 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.391 ; 0.545 ; FF ; IC ; 1 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|dataf ; +; 5.418 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17|combout ; +; 5.422 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X99_Y153_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~17~la_lab/laboutb[10] ; +; 6.218 ; 0.796 ; RR ; IC ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|dataf ; +; 6.246 ; 0.028 ; RF ; CELL ; 1 ; MLABCELL_X92_Y164_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~552|combout ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|d ; +; 6.246 ; 0.000 ; FF ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.450 ; 2.950 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.240 ; 2.175 ; RR ; IC ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8]|clk ; +; 5.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X92_Y164_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; +; 5.450 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.420 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.603 ; 0.183 ; ; uTsu ; 1 ; FF_X92_Y164_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[17][8] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1962: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.249 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.251 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.827 ; 87 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.302 ; 9 ; 0.000 ; 0.074 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.249 ; 3.251 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.416 ; 0.570 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|dataf ; +; 5.443 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23|combout ; +; 5.449 ; 0.006 ; RR ; CELL ; 28 ; MLABCELL_X98_Y153_N9 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~23~la_mlab/laboutt[7] ; +; 6.222 ; 0.773 ; RR ; IC ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|dataf ; +; 6.249 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X101_Y161_N33 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~750|combout ; +; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|d ; +; 6.249 ; 0.000 ; FF ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X101_Y161_N35 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.168 ; ; uTsu ; 1 ; FF_X101_Y161_N35 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[23][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1963: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.224 ; +; Data Required Time ; 5.581 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.050 ; ; ; ; ; ; +; Data Delay ; 3.226 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.816 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.290 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.173 ; 79 ; 0.000 ; 2.173 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.224 ; 3.226 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.391 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.418 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.423 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.197 ; 0.774 ; RR ; IC ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|dataf ; +; 6.224 ; 0.027 ; RF ; CELL ; 1 ; MLABCELL_X94_Y164_N54 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~911|combout ; +; 6.224 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|d ; +; 6.224 ; 0.000 ; FF ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.448 ; 2.948 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.238 ; 2.173 ; RR ; IC ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15]|clk ; +; 5.238 ; 0.000 ; RR ; CELL ; 1 ; FF_X94_Y164_N56 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; +; 5.448 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.418 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.581 ; 0.163 ; ; uTsu ; 1 ; FF_X94_Y164_N56 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][15] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1964: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_d_e_reg|csr_address[7] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.193 ; +; Data Required Time ; 5.550 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.119 ; ; ; ; ; ; +; Data Delay ; 3.195 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.713 ; 85 ; 0.119 ; 0.922 ; +; Cell ; ; 12 ; 0.360 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.193 ; 3.195 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.197 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.223 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.228 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.347 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.420 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.424 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.212 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.239 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.244 ; 0.005 ; RR ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.166 ; 0.922 ; RR ; IC ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|dataf ; +; 6.193 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X51_Y160_N12 ; High Speed ; vx_d_e_reg|i498~7|combout ; +; 6.193 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|d ; +; 6.193 ; 0.000 ; FF ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N14 ; High Speed ; vx_d_e_reg|csr_address[7] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N14 ; ; vx_d_e_reg|csr_address[7] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1965: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.243 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.245 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.822 ; 87 ; 0.104 ; 1.316 ; +; Cell ; ; 12 ; 0.301 ; 9 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.243 ; 3.245 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.871 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.896 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.901 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.217 ; 1.316 ; FF ; IC ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|dataf ; +; 6.243 ; 0.026 ; FR ; CELL ; 1 ; MLABCELL_X103_Y161_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~974|combout ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|d ; +; 6.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y161_N40 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.163 ; ; uTsu ; 1 ; FF_X103_Y161_N40 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[30][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1966: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[13] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.759 ; 85 ; 0.104 ; 1.275 ; +; Cell ; ; 12 ; 0.362 ; 11 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N17 ; ; vx_f_d_reg|instruction[13]|q ; +; 3.189 ; 0.069 ; FF ; CELL ; 17 ; FF_X77_Y155_N17 ; High Speed ; vx_f_d_reg|instruction[13]~la_lab/laboutt[11] ; +; 3.348 ; 0.159 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|dataf ; +; 3.377 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.382 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.486 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.560 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.565 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.659 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.685 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.689 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.816 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.841 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.846 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.121 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.241 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1967: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------+ +; From Node ; vx_csr_handler|decode_csr_address[2] ; +; To Node ; vx_e_m_reg|csr_result[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.260 ; +; Data Required Time ; 5.617 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+--------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.009 ; ; ; ; ; ; +; Data Delay ; 3.271 ; ; ; ; ; ; +; Number of Logic Levels ; ; 7 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.362 ; 79 ; 0.000 ; 2.362 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 7 ; 2.837 ; 87 ; 0.116 ; 0.924 ; +; Cell ; ; 16 ; 0.314 ; 10 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.188 ; 79 ; 0.000 ; 2.188 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.989 ; 2.989 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.989 ; 2.362 ; RR ; IC ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]|clk ; +; 2.989 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2] ; +; 6.260 ; 3.271 ; ; ; ; ; ; data path ; +; 3.109 ; 0.120 ; FF ; uTco ; 1 ; FF_X51_Y153_N52 ; ; vx_csr_handler|decode_csr_address[2]|q ; +; 3.156 ; 0.047 ; FF ; CELL ; 686 ; FF_X51_Y153_N52 ; High Speed ; vx_csr_handler|decode_csr_address[2]~la_lab/laboutb[14] ; +; 4.080 ; 0.924 ; FF ; IC ; 1 ; LABCELL_X25_Y153_N24 ; Mixed ; vx_csr_handler|Mux_3~315|dataf ; +; 4.110 ; 0.030 ; FR ; CELL ; 1 ; LABCELL_X25_Y153_N24 ; Low Power ; vx_csr_handler|Mux_3~315|combout ; +; 4.114 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X25_Y153_N24 ; Low Power ; vx_csr_handler|Mux_3~315~la_lab/laboutt[16] ; +; 4.454 ; 0.340 ; RR ; IC ; 1 ; LABCELL_X30_Y153_N48 ; Mixed ; vx_csr_handler|Mux_3~316|datad ; +; 4.534 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X30_Y153_N48 ; High Speed ; vx_csr_handler|Mux_3~316|combout ; +; 4.538 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X30_Y153_N48 ; High Speed ; vx_csr_handler|Mux_3~316~la_lab/laboutb[12] ; +; 4.671 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X31_Y153_N18 ; High Speed ; vx_csr_handler|Mux_3~317|dataf ; +; 4.697 ; 0.026 ; RR ; CELL ; 1 ; MLABCELL_X31_Y153_N18 ; High Speed ; vx_csr_handler|Mux_3~317|combout ; +; 4.703 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X31_Y153_N18 ; High Speed ; vx_csr_handler|Mux_3~317~la_mlab/laboutt[12] ; +; 5.128 ; 0.425 ; RR ; IC ; 1 ; LABCELL_X37_Y157_N45 ; High Speed ; vx_csr_handler|Mux_3~339|dataf ; +; 5.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X37_Y157_N45 ; High Speed ; vx_csr_handler|Mux_3~339|combout ; +; 5.158 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X37_Y157_N45 ; High Speed ; vx_csr_handler|Mux_3~339~la_lab/laboutb[10] ; +; 5.274 ; 0.116 ; RR ; IC ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|dataf ; +; 5.300 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340|combout ; +; 5.304 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X38_Y157_N24 ; High Speed ; vx_csr_handler|Mux_3~340~la_lab/laboutt[16] ; +; 6.081 ; 0.777 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|dataf ; +; 6.107 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341|combout ; +; 6.112 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X58_Y153_N57 ; High Speed ; vx_csr_handler|Mux_3~341~la_lab/laboutb[19] ; +; 6.234 ; 0.122 ; RR ; IC ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|dataf ; +; 6.260 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X58_Y153_N0 ; High Speed ; vx_execute|Select_31~29|combout ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|d ; +; 6.260 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.480 ; 2.980 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.253 ; 2.188 ; RR ; IC ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4]|clk ; +; 5.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X58_Y153_N2 ; High Speed ; vx_e_m_reg|csr_result[4] ; +; 5.480 ; 0.227 ; ; ; ; ; ; clock pessimism removed ; +; 5.450 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.617 ; 0.167 ; ; uTsu ; 1 ; FF_X58_Y153_N2 ; ; vx_e_m_reg|csr_result[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1968: Setup slack is -0.643 (VIOLATED) +=============================================================================== ++----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+-------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+-------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.643 (VIOLATED) ; ++--------------------+-------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.250 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.768 ; 85 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.361 ; 11 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.248 ; 3.250 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.896 ; 0.133 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.921 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.926 ; 0.005 ; RR ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.276 ; 0.350 ; RR ; IC ; 1 ; MLABCELL_X92_Y153_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~9|dataf ; +; 5.304 ; 0.028 ; RF ; CELL ; 2 ; MLABCELL_X92_Y153_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~9|combout ; +; 5.310 ; 0.006 ; FF ; CELL ; 17 ; MLABCELL_X92_Y153_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~9~la_mlab/laboutt[4] ; +; 6.220 ; 0.910 ; FF ; IC ; 1 ; LABCELL_X108_Y150_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~313|dataf ; +; 6.248 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X108_Y150_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~313|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y150_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y150_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y150_N4 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X108_Y150_N4 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[9][25] ; ++---------+---------+----+------+--------+---------------------+------------+-----------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1969: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.189 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.197 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.637 ; 82 ; 0.135 ; 0.657 ; +; Cell ; ; 14 ; 0.434 ; 14 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.189 ; 3.197 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.675 ; 0.496 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|datac ; +; 3.755 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; +; 3.760 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; +; 3.895 ; 0.135 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; +; 3.921 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.926 ; 0.005 ; RR ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.277 ; 0.351 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.370 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.375 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.032 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.125 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.131 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.497 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.525 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.529 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.161 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.189 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.189 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.189 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1970: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_d_e_reg|rd[1] ; +; To Node ; vx_d_e_reg|upper_immed[4] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.189 ; +; Data Required Time ; 5.547 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.081 ; ; ; ; ; ; +; Data Delay ; 3.191 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.532 ; 79 ; 0.127 ; 0.657 ; +; Cell ; ; 14 ; 0.537 ; 17 ; 0.000 ; 0.121 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1] ; +; 6.189 ; 3.191 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N10 ; ; vx_d_e_reg|rd[1]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N10 ; High Speed ; vx_d_e_reg|rd[1]~la_lab/laboutt[6] ; +; 3.760 ; 0.596 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|datad ; +; 3.850 ; 0.090 ; FF ; CELL ; 2 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1|combout ; +; 3.856 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X82_Y153_N6 ; High Speed ; vx_forwarding|src1_exe_fwd~1~la_mlab/laboutt[5] ; +; 4.010 ; 0.154 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataa ; +; 4.117 ; 0.107 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.122 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.249 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.370 ; 0.121 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.375 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.032 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.125 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.131 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.497 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.525 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.529 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.161 ; 0.632 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|dataf ; +; 6.189 ; 0.028 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N51 ; High Speed ; vx_d_e_reg|i486~4|combout ; +; 6.189 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|d ; +; 6.189 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N52 ; High Speed ; vx_d_e_reg|upper_immed[4] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.547 ; 0.160 ; ; uTsu ; 1 ; FF_X81_Y151_N52 ; ; vx_d_e_reg|upper_immed[4] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1971: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.628 ; 81 ; 0.118 ; 0.708 ; +; Cell ; ; 14 ; 0.495 ; 15 ; 0.000 ; 0.111 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.241 ; 3.249 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.687 ; 0.508 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; +; 3.763 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.767 ; 0.004 ; FF ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 4.098 ; 0.331 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|dataf ; +; 4.125 ; 0.027 ; FR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.130 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.248 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.359 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.364 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.047 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.138 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.144 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.852 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.880 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.886 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.166 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.241 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.241 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1972: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|csr_mask[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.228 ; +; Data Required Time ; 5.586 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.236 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.628 ; 81 ; 0.138 ; 0.712 ; +; Cell ; ; 14 ; 0.481 ; 15 ; 0.000 ; 0.096 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.228 ; 3.236 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; FF ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.795 ; 0.632 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datae ; +; 3.853 ; 0.058 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 3.859 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[13] ; +; 3.997 ; 0.138 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|datae ; +; 4.071 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2|combout ; +; 4.076 ; 0.005 ; FF ; CELL ; 33 ; LABCELL_X81_Y153_N12 ; High Speed ; vx_forwarding|src2_exe_fwd~2~la_lab/laboutt[9] ; +; 4.281 ; 0.205 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datae ; +; 4.377 ; 0.096 ; FR ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.382 ; 0.005 ; RR ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.039 ; 0.657 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.132 ; 0.093 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.138 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.422 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.448 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.454 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.166 ; 0.712 ; FF ; IC ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|datae ; +; 6.228 ; 0.062 ; FF ; CELL ; 1 ; LABCELL_X79_Y158_N12 ; High Speed ; vx_d_e_reg|i531~11|combout ; +; 6.228 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|d ; +; 6.228 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y158_N14 ; High Speed ; vx_d_e_reg|csr_mask[11] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.586 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y158_N14 ; ; vx_d_e_reg|csr_mask[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1973: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_d_e_reg|csr_mask[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.229 ; +; Data Required Time ; 5.587 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.080 ; ; ; ; ; ; +; Data Delay ; 3.231 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.670 ; 83 ; 0.116 ; 0.788 ; +; Cell ; ; 14 ; 0.440 ; 14 ; 0.000 ; 0.106 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.143 ; 79 ; 0.000 ; 2.143 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.229 ; 3.231 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.160 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.186 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.191 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.310 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.383 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.387 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.175 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.202 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.208 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.492 ; 0.284 ; RR ; IC ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|dataf ; +; 5.518 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0|combout ; +; 5.524 ; 0.006 ; FF ; CELL ; 27 ; MLABCELL_X76_Y156_N9 ; High Speed ; vx_d_e_reg|csr_mask[6]~0~la_mlab/laboutt[7] ; +; 6.123 ; 0.599 ; FF ; IC ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|datab ; +; 6.229 ; 0.106 ; FF ; CELL ; 1 ; LABCELL_X79_Y156_N15 ; High Speed ; vx_d_e_reg|i531~9|combout ; +; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|d ; +; 6.229 ; 0.000 ; FF ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.418 ; 2.918 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.208 ; 2.143 ; RR ; IC ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9]|clk ; +; 5.208 ; 0.000 ; RR ; CELL ; 1 ; FF_X79_Y156_N16 ; High Speed ; vx_d_e_reg|csr_mask[9] ; +; 5.418 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.388 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.587 ; 0.199 ; ; uTsu ; 1 ; FF_X79_Y156_N16 ; ; vx_d_e_reg|csr_mask[9] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1974: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_fetch|VX_Warp_zero|real_PC[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.099 ; +; Data Required Time ; 5.457 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.029 ; ; ; ; ; ; +; Data Delay ; 3.101 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.595 ; 84 ; 0.108 ; 0.854 ; +; Cell ; ; 12 ; 0.384 ; 12 ; 0.000 ; 0.085 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.194 ; 80 ; 0.000 ; 2.194 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.099 ; 3.101 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.353 ; 0.170 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.438 ; 0.085 ; RF ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.443 ; 0.005 ; FF ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 4.297 ; 0.854 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datac ; +; 4.381 ; 0.084 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.386 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.494 ; 0.108 ; FF ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.567 ; 0.073 ; FR ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.571 ; 0.004 ; RR ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.322 ; 0.751 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.348 ; 0.026 ; RF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.354 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.816 ; 0.462 ; FF ; IC ; 1 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|dataf ; +; 5.843 ; 0.027 ; FF ; CELL ; 2 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall|combout ; +; 5.849 ; 0.006 ; FF ; CELL ; 22 ; MLABCELL_X72_Y157_N24 ; High Speed ; vx_fetch|warp_zero_stall~la_mlab/laboutt[17] ; +; 6.099 ; 0.250 ; FF ; IC ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6]|sload ; +; 6.099 ; 0.000 ; FF ; CELL ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.469 ; 2.969 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.259 ; 2.194 ; RR ; IC ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6]|clk ; +; 5.259 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y160_N58 ; High Speed ; vx_fetch|VX_Warp_zero|real_PC[6] ; +; 5.469 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.439 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.457 ; 0.018 ; ; uTsu ; 1 ; FF_X71_Y160_N58 ; ; vx_fetch|VX_Warp_zero|real_PC[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1975: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.231 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.041 ; ; ; ; ; ; +; Data Delay ; 3.233 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.774 ; 86 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.337 ; 10 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.231 ; 3.233 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.376 ; 0.480 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|datad ; +; 5.456 ; 0.080 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26|combout ; +; 5.460 ; 0.004 ; RR ; CELL ; 29 ; LABCELL_X95_Y153_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~26~la_lab/laboutt[16] ; +; 6.203 ; 0.743 ; RR ; IC ; 1 ; LABCELL_X97_Y165_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~838|dataf ; +; 6.231 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X97_Y165_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~838|combout ; +; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6]|d ; +; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6]|clk ; +; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N40 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; +; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.162 ; ; uTsu ; 1 ; FF_X97_Y165_N40 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[26][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1976: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.230 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.041 ; ; ; ; ; ; +; Data Delay ; 3.232 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.720 ; 84 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.390 ; 12 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.182 ; 79 ; 0.000 ; 2.182 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.230 ; 3.232 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.896 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.438 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.515 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.520 ; 0.005 ; RR ; CELL ; 10 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[11] ; +; 6.147 ; 0.627 ; RR ; IC ; 1 ; LABCELL_X97_Y165_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~582|datac ; +; 6.230 ; 0.083 ; RR ; CELL ; 1 ; LABCELL_X97_Y165_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~582|combout ; +; 6.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6]|d ; +; 6.230 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.457 ; 2.957 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.247 ; 2.182 ; RR ; IC ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6]|clk ; +; 5.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y165_N49 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; +; 5.457 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.427 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.161 ; ; uTsu ; 1 ; FF_X97_Y165_N49 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][6] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1977: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+---------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[4] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.221 ; +; Data Required Time ; 5.579 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+---------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.054 ; ; ; ; ; ; +; Data Delay ; 3.223 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.815 ; 87 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.286 ; 9 ; 0.000 ; 0.084 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.169 ; 79 ; 0.000 ; 2.169 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4] ; +; 6.221 ; 3.223 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N10 ; ; vx_f_d_reg|instruction[4]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 34 ; FF_X77_Y155_N10 ; High Speed ; vx_f_d_reg|instruction[4]~la_lab/laboutt[6] ; +; 3.376 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datad ; +; 3.460 ; 0.084 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.465 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.596 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.623 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.628 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.722 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.748 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.752 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.866 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.891 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.897 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.449 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.476 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.481 ; 0.005 ; RR ; CELL ; 14 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[10] ; +; 6.193 ; 0.712 ; RR ; IC ; 1 ; LABCELL_X93_Y162_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~904|dataf ; +; 6.221 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X93_Y162_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~904|combout ; +; 6.221 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8]|d ; +; 6.221 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.444 ; 2.944 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.234 ; 2.169 ; RR ; IC ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8]|clk ; +; 5.234 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y162_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; +; 5.444 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.414 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.579 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y162_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][8] ; ++---------+---------+----+------+--------+---------------------+------------+-------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1978: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.242 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.244 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.727 ; 84 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.395 ; 12 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.242 ; 3.244 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.470 ; 0.581 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|dataf ; +; 5.497 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31|combout ; +; 5.503 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X96_Y154_N24 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~31~la_mlab/laboutt[16] ; +; 6.156 ; 0.653 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1002|datac ; +; 6.242 ; 0.086 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N0 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~1002|combout ; +; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10]|d ; +; 6.242 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N2 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.162 ; ; uTsu ; 1 ; FF_X107_Y157_N2 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[31][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1979: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.231 ; +; Data Required Time ; 5.589 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.045 ; ; ; ; ; ; +; Data Delay ; 3.233 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.772 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.339 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.178 ; 79 ; 0.000 ; 2.178 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.231 ; 3.233 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.480 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.509 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.515 ; 0.006 ; RR ; CELL ; 9 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[9] ; +; 6.203 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|dataf ; +; 6.231 ; 0.028 ; RF ; CELL ; 2 ; LABCELL_X93_Y147_N9 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~728|combout ; +; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]|d ; +; 6.231 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.453 ; 2.953 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.243 ; 2.178 ; RR ; IC ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24]|clk ; +; 5.243 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y147_N11 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; +; 5.453 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.423 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.589 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y147_N11 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][24] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1980: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++--------------------------------------------------------+ +; Path Summary ; ++--------------------+-----------------------------------+ +; Property ; Value ; ++--------------------+-----------------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_fetch|VX_Warp_three|real_PC[9] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.248 ; +; Data Required Time ; 5.606 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+-----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.019 ; ; ; ; ; ; +; Data Delay ; 3.256 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.615 ; 80 ; 0.136 ; 0.755 ; +; Cell ; ; 14 ; 0.515 ; 16 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.198 ; 80 ; 0.000 ; 2.198 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.248 ; 3.256 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; FF ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.162 ; 0.044 ; FF ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.676 ; 0.514 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|datac ; +; 3.759 ; 0.083 ; FR ; CELL ; 1 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0|combout ; +; 3.763 ; 0.004 ; RR ; CELL ; 4 ; LABCELL_X85_Y153_N33 ; High Speed ; vx_forwarding|reduce_or_0~la_lab/laboutb[2] ; +; 3.899 ; 0.136 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|datac ; +; 3.978 ; 0.079 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.983 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.339 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.429 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.434 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.117 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.208 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.213 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 5.968 ; 0.755 ; FF ; IC ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|dataf ; +; 5.995 ; 0.027 ; FR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34|combout ; +; 6.001 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y159_N39 ; High Speed ; vx_fetch|VX_Warp_three|i199~34~la_mlab/laboutb[7] ; +; 6.172 ; 0.171 ; RR ; IC ; 1 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|datae ; +; 6.248 ; 0.076 ; RF ; CELL ; 2 ; MLABCELL_X69_Y159_N48 ; High Speed ; vx_fetch|VX_Warp_three|i199~45|combout ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|d ; +; 6.248 ; 0.000 ; FF ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.473 ; 2.973 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.263 ; 2.198 ; RR ; IC ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9]|clk ; +; 5.263 ; 0.000 ; RR ; CELL ; 1 ; FF_X69_Y159_N50 ; High Speed ; vx_fetch|VX_Warp_three|real_PC[9] ; +; 5.473 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.443 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.606 ; 0.163 ; ; uTsu ; 1 ; FF_X69_Y159_N50 ; ; vx_fetch|VX_Warp_three|real_PC[9] ; ++---------+---------+----+------+--------+---------------------+------------+---------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1981: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.230 ; +; Data Required Time ; 5.588 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.232 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.784 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.327 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.230 ; 3.232 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.845 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.870 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.875 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.444 ; 0.569 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|dataf ; +; 5.475 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28|combout ; +; 5.479 ; 0.004 ; RR ; CELL ; 24 ; LABCELL_X95_Y154_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~28~la_lab/laboutb[14] ; +; 6.203 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|dataf ; +; 6.230 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y144_N0 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~924|combout ; +; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|d ; +; 6.230 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y144_N2 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.588 ; 0.164 ; ; uTsu ; 1 ; FF_X91_Y144_N2 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1982: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.253 ; +; Data Required Time ; 5.611 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.022 ; ; ; ; ; ; +; Data Delay ; 3.255 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.708 ; 83 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.426 ; 13 ; 0.000 ; 0.080 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.201 ; 80 ; 0.000 ; 2.201 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.253 ; 3.255 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.862 ; 0.005 ; FF ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.404 ; 0.542 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|datac ; +; 5.481 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18|combout ; +; 5.485 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~18~la_lab/laboutt[10] ; +; 6.173 ; 0.688 ; RR ; IC ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|datac ; +; 6.253 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X104_Y146_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~594|combout ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|d ; +; 6.253 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.476 ; 2.976 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.266 ; 2.201 ; RR ; IC ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18]|clk ; +; 5.266 ; 0.000 ; RR ; CELL ; 1 ; FF_X104_Y146_N59 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; +; 5.476 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.446 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.611 ; 0.165 ; ; uTsu ; 1 ; FF_X104_Y146_N59 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[18][18] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1983: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[5] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.240 ; +; Data Required Time ; 5.598 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.242 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.773 ; 86 ; 0.120 ; 1.094 ; +; Cell ; ; 14 ; 0.347 ; 11 ; 0.000 ; 0.125 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5] ; +; 6.240 ; 3.242 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; RR ; uTco ; 1 ; FF_X77_Y155_N8 ; ; vx_f_d_reg|instruction[5]|q ; +; 3.183 ; 0.063 ; RR ; CELL ; 18 ; FF_X77_Y155_N8 ; High Speed ; vx_f_d_reg|instruction[5]~la_lab/laboutt[5] ; +; 3.303 ; 0.120 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataa ; +; 3.428 ; 0.125 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.433 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.564 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.591 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.596 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.690 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.716 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.720 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.847 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.872 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.877 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.334 ; 0.457 ; FF ; IC ; 1 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|dataf ; +; 5.363 ; 0.029 ; FR ; CELL ; 2 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20|combout ; +; 5.367 ; 0.004 ; RR ; CELL ; 14 ; LABCELL_X95_Y153_N39 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~20~la_lab/laboutb[6] ; +; 6.211 ; 0.844 ; RR ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|dataf ; +; 6.240 ; 0.029 ; RF ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|d ; +; 6.240 ; 0.000 ; FF ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N8 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.598 ; 0.162 ; ; uTsu ; 1 ; FF_X105_Y159_N8 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1984: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[14] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.797 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.325 ; 10 ; 0.000 ; 0.077 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N20 ; ; vx_f_d_reg|instruction[14]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N20 ; High Speed ; vx_f_d_reg|instruction[14]~la_lab/laboutt[13] ; +; 3.329 ; 0.166 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datad ; +; 3.406 ; 0.077 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.411 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.515 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.589 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.594 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.688 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.714 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.718 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.832 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.857 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.863 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.443 ; 0.580 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|dataf ; +; 5.470 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30|combout ; +; 5.475 ; 0.005 ; RR ; CELL ; 10 ; MLABCELL_X96_Y154_N3 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~30~la_mlab/laboutt[2] ; +; 6.214 ; 0.739 ; RR ; IC ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|dataf ; +; 6.241 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X108_Y157_N15 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~970|combout ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|d ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X108_Y157_N16 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.161 ; ; uTsu ; 1 ; FF_X108_Y157_N16 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[30][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1985: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[1] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.780 ; 86 ; 0.110 ; 1.094 ; +; Cell ; ; 14 ; 0.342 ; 11 ; 0.000 ; 0.123 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N50 ; ; vx_f_d_reg|instruction[1]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 8 ; FF_X77_Y155_N50 ; High Speed ; vx_f_d_reg|instruction[1]~la_lab/laboutb[13] ; +; 3.292 ; 0.110 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datab ; +; 3.415 ; 0.123 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.420 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.551 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.578 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.583 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.677 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.703 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.707 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.834 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.859 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.864 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.490 ; 0.626 ; FF ; IC ; 1 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|dataf ; +; 5.517 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16|combout ; +; 5.522 ; 0.005 ; RR ; CELL ; 26 ; MLABCELL_X98_Y152_N15 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~16~la_mlab/laboutt[10] ; +; 6.214 ; 0.692 ; RR ; IC ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|dataf ; +; 6.241 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X102_Y161_N51 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~526|combout ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|d ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14]|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X102_Y161_N53 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.163 ; ; uTsu ; 1 ; FF_X102_Y161_N53 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[16][14] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1986: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[6] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.237 ; +; Data Required Time ; 5.595 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.239 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.751 ; 85 ; 0.114 ; 1.094 ; +; Cell ; ; 14 ; 0.367 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6] ; +; 6.237 ; 3.239 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N56 ; ; vx_f_d_reg|instruction[6]|q ; +; 3.182 ; 0.063 ; RR ; CELL ; 10 ; FF_X77_Y155_N56 ; High Speed ; vx_f_d_reg|instruction[6]~la_lab/laboutb[17] ; +; 3.298 ; 0.116 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|datac ; +; 3.391 ; 0.093 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.396 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.527 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.554 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.559 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.653 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.679 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.683 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.797 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.822 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.828 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.418 ; 0.590 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|dataf ; +; 5.447 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20|combout ; +; 5.452 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~20~la_mlab/laboutb[12] ; +; 6.158 ; 0.706 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|datac ; +; 6.237 ; 0.079 ; RR ; CELL ; 1 ; LABCELL_X93_Y144_N57 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~668|combout ; +; 6.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|d ; +; 6.237 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N58 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.595 ; 0.167 ; ; uTsu ; 1 ; FF_X93_Y144_N58 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[20][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1987: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.224 ; +; Data Required Time ; 5.582 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.052 ; ; ; ; ; ; +; Data Delay ; 3.226 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.812 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.294 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.171 ; 79 ; 0.000 ; 2.171 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.224 ; 3.226 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.436 ; 0.585 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|dataf ; +; 5.468 ; 0.032 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18|combout ; +; 5.473 ; 0.005 ; RR ; CELL ; 14 ; LABCELL_X95_Y154_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~18~la_lab/laboutt[17] ; +; 6.197 ; 0.724 ; RR ; IC ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|dataf ; +; 6.224 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y164_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~591|combout ; +; 6.224 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|d ; +; 6.224 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.446 ; 2.946 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.236 ; 2.171 ; RR ; IC ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15]|clk ; +; 5.236 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y164_N43 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; +; 5.446 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.416 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.582 ; 0.166 ; ; uTsu ; 1 ; FF_X93_Y164_N43 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[18][15] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1988: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.233 ; +; Data Required Time ; 5.591 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.044 ; ; ; ; ; ; +; Data Delay ; 3.235 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.826 ; 87 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.289 ; 9 ; 0.000 ; 0.072 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.179 ; 79 ; 0.000 ; 2.179 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.233 ; 3.235 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.424 ; 0.573 ; FF ; IC ; 1 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|dataf ; +; 5.451 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26|combout ; +; 5.456 ; 0.005 ; RR ; CELL ; 16 ; MLABCELL_X98_Y153_N3 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~26~la_mlab/laboutt[2] ; +; 6.206 ; 0.750 ; RR ; IC ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|dataf ; +; 6.233 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X91_Y161_N42 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~849|combout ; +; 6.233 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|d ; +; 6.233 ; 0.000 ; FF ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.454 ; 2.954 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.244 ; 2.179 ; RR ; IC ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17]|clk ; +; 5.244 ; 0.000 ; RR ; CELL ; 1 ; FF_X91_Y161_N44 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; +; 5.454 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.424 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.591 ; 0.167 ; ; uTsu ; 1 ; FF_X91_Y161_N44 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[26][17] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1989: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.247 ; +; Data Required Time ; 5.605 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.249 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.777 ; 85 ; 0.106 ; 1.094 ; +; Cell ; ; 14 ; 0.352 ; 11 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.247 ; 3.249 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.808 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.833 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.839 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.430 ; 0.591 ; FF ; IC ; 1 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|dataf ; +; 5.459 ; 0.029 ; FR ; CELL ; 2 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22|combout ; +; 5.464 ; 0.005 ; RR ; CELL ; 23 ; MLABCELL_X96_Y154_N42 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~22~la_mlab/laboutb[8] ; +; 6.160 ; 0.696 ; RR ; IC ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|datac ; +; 6.247 ; 0.087 ; RR ; CELL ; 1 ; MLABCELL_X107_Y157_N18 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~714|combout ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|d ; +; 6.247 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+------------------------+------------+--------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X107_Y157_N19 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.605 ; 0.167 ; ; uTsu ; 1 ; FF_X107_Y157_N19 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[22][10] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1990: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-----------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+--------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+--------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.235 ; +; Data Required Time ; 5.593 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+--------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.040 ; ; ; ; ; ; +; Data Delay ; 3.237 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.844 ; 88 ; 0.127 ; 1.094 ; +; Cell ; ; 14 ; 0.273 ; 8 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.183 ; 79 ; 0.000 ; 2.183 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.235 ; 3.237 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 3.495 ; 0.131 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|dataf ; +; 3.522 ; 0.027 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.527 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.621 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.647 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.651 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.778 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.803 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.808 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 5.375 ; 0.567 ; FF ; IC ; 1 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|dataf ; +; 5.406 ; 0.031 ; FR ; CELL ; 2 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21|combout ; +; 5.410 ; 0.004 ; RR ; CELL ; 22 ; LABCELL_X95_Y154_N45 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i4143~21~la_lab/laboutb[10] ; +; 6.208 ; 0.798 ; RR ; IC ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|dataf ; +; 6.235 ; 0.027 ; RF ; CELL ; 1 ; LABCELL_X93_Y144_N24 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~700|combout ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|d ; +; 6.235 ; 0.000 ; FF ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+-----------------------+------------+-------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.458 ; 2.958 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.248 ; 2.183 ; RR ; IC ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28]|clk ; +; 5.248 ; 0.000 ; RR ; CELL ; 1 ; FF_X93_Y144_N26 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; +; 5.458 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.428 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.593 ; 0.165 ; ; uTsu ; 1 ; FF_X93_Y144_N26 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[21][28] ; ++---------+---------+----+------+--------+---------------------+------------+------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1991: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[22] ; +; To Node ; vx_d_e_reg|csr_address[6] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.192 ; +; Data Required Time ; 5.550 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.113 ; ; ; ; ; ; +; Data Delay ; 3.200 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.675 ; 84 ; 0.128 ; 0.930 ; +; Cell ; ; 12 ; 0.400 ; 13 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.125 ; 4 ; 0.125 ; 0.125 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.186 ; 79 ; 0.000 ; 2.186 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22] ; +; 6.192 ; 3.200 ; ; ; ; ; ; data path ; +; 3.117 ; 0.125 ; FF ; uTco ; 1 ; FF_X97_Y153_N19 ; ; vx_f_d_reg|instruction[22]|q ; +; 3.185 ; 0.068 ; FF ; CELL ; 651 ; FF_X97_Y153_N19 ; High Speed ; vx_f_d_reg|instruction[22]~la_lab/laboutt[12] ; +; 3.907 ; 0.722 ; FF ; IC ; 1 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|datad ; +; 3.996 ; 0.089 ; FR ; CELL ; 2 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6|combout ; +; 4.001 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X82_Y153_N48 ; High Speed ; vx_forwarding|reduce_or_6~la_mlab/laboutb[12] ; +; 4.129 ; 0.128 ; RR ; IC ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|datad ; +; 4.209 ; 0.080 ; RF ; CELL ; 1 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2|combout ; +; 4.214 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X83_Y153_N39 ; High Speed ; vx_forwarding|i181~2~la_lab/laboutb[7] ; +; 4.426 ; 0.212 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|dataf ; +; 4.451 ; 0.025 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.456 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.139 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.230 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.235 ; 0.005 ; FF ; CELL ; 86 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[10] ; +; 6.165 ; 0.930 ; FF ; IC ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|dataf ; +; 6.192 ; 0.027 ; FR ; CELL ; 1 ; LABCELL_X51_Y160_N27 ; High Speed ; vx_d_e_reg|i498~6|combout ; +; 6.192 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|d ; +; 6.192 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.379 ; 2.879 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.251 ; 2.186 ; RR ; IC ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6]|clk ; +; 5.251 ; 0.000 ; RR ; CELL ; 1 ; FF_X51_Y160_N28 ; High Speed ; vx_d_e_reg|csr_address[6] ; +; 5.379 ; 0.128 ; ; ; ; ; ; clock pessimism removed ; +; 5.349 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.550 ; 0.201 ; ; uTsu ; 1 ; FF_X51_Y160_N28 ; ; vx_d_e_reg|csr_address[6] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1992: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++---------------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+------------------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+------------------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[3] ; +; To Node ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.246 ; +; Data Required Time ; 5.604 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.032 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 5 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.778 ; 86 ; 0.106 ; 1.275 ; +; Cell ; ; 12 ; 0.350 ; 11 ; 0.000 ; 0.120 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.191 ; 79 ; 0.000 ; 2.191 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3] ; +; 6.246 ; 3.248 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N26 ; ; vx_f_d_reg|instruction[3]|q ; +; 3.181 ; 0.063 ; RR ; CELL ; 17 ; FF_X77_Y155_N26 ; High Speed ; vx_f_d_reg|instruction[3]~la_lab/laboutt[17] ; +; 3.357 ; 0.176 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|dataf ; +; 3.382 ; 0.025 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.387 ; 0.005 ; RR ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.493 ; 0.106 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.565 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.570 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.664 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.690 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.694 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.821 ; 0.127 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|dataf ; +; 4.846 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0|combout ; +; 4.851 ; 0.005 ; FF ; CELL ; 677 ; MLABCELL_X86_Y153_N21 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i2094~0~la_mlab/laboutt[14] ; +; 6.126 ; 1.275 ; FF ; IC ; 1 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|datab ; +; 6.246 ; 0.120 ; FR ; CELL ; 2 ; MLABCELL_X105_Y159_N6 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|i5167~651|combout ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|d ; +; 6.246 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.466 ; 2.966 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.256 ; 2.191 ; RR ; IC ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE|clk ; +; 5.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X105_Y159_N7 ; High Speed ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; +; 5.466 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.436 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.604 ; 0.168 ; ; uTsu ; 1 ; FF_X105_Y159_N7 ; ; vx_decode|VX_Context_two|vx_register_file_master|registers[20][11]~DUPLICATE ; ++---------+---------+----+------+--------+---------------------+------------+----------------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1993: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.256 ; +; Data Required Time ; 5.614 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.030 ; ; ; ; ; ; +; Data Delay ; 3.258 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.734 ; 84 ; 0.110 ; 1.046 ; +; Cell ; ; 14 ; 0.403 ; 12 ; 0.000 ; 0.092 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.193 ; 80 ; 0.000 ; 2.193 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.256 ; 3.258 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; RR ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.179 ; 0.060 ; RR ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.398 ; 0.219 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.490 ; 0.092 ; RF ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.495 ; 0.005 ; FF ; CELL ; 3 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[2] ; +; 3.605 ; 0.110 ; FF ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datad ; +; 3.682 ; 0.077 ; FR ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.687 ; 0.005 ; RR ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.733 ; 1.046 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.759 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.763 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.888 ; 0.125 ; RR ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.912 ; 0.024 ; RR ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.917 ; 0.005 ; RR ; CELL ; 582 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[6] ; +; 5.446 ; 0.529 ; RR ; IC ; 1 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|datad ; +; 5.518 ; 0.072 ; RF ; CELL ; 2 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25|combout ; +; 5.522 ; 0.004 ; FF ; CELL ; 29 ; LABCELL_X95_Y154_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~25~la_lab/laboutb[6] ; +; 6.227 ; 0.705 ; FF ; IC ; 1 ; MLABCELL_X103_Y157_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~811|dataf ; +; 6.256 ; 0.029 ; FR ; CELL ; 1 ; MLABCELL_X103_Y157_N36 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~811|combout ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y157_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11]|d ; +; 6.256 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y157_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11] ; ++---------+---------+----+------+--------+------------------------+------------+-------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.468 ; 2.968 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.258 ; 2.193 ; RR ; IC ; 1 ; FF_X103_Y157_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11]|clk ; +; 5.258 ; 0.000 ; RR ; CELL ; 1 ; FF_X103_Y157_N37 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11] ; +; 5.468 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.438 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.614 ; 0.176 ; ; uTsu ; 1 ; FF_X103_Y157_N37 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[25][11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1994: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[14] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.110 ; +; Data Required Time ; 5.468 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.027 ; ; ; ; ; ; +; Data Delay ; 3.112 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.653 ; 85 ; 0.119 ; 1.144 ; +; Cell ; ; 10 ; 0.338 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.110 ; 3.112 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.966 ; 0.004 ; FF ; CELL ; 44 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[4] ; +; 6.110 ; 1.144 ; FF ; IC ; 1 ; FF_X74_Y160_N38 ; High Speed ; vx_f_d_reg|curr_PC[14]|ena ; +; 6.110 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N38 ; High Speed ; vx_f_d_reg|curr_PC[14] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X74_Y160_N38 ; High Speed ; vx_f_d_reg|curr_PC[14]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y160_N38 ; High Speed ; vx_f_d_reg|curr_PC[14] ; +; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.468 ; 0.027 ; ; uTsu ; 1 ; FF_X74_Y160_N38 ; ; vx_f_d_reg|curr_PC[14] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1995: Setup slack is -0.642 (VIOLATED) +=============================================================================== ++------------------------------------------------+ +; Path Summary ; ++--------------------+---------------------------+ +; Property ; Value ; ++--------------------+---------------------------+ +; From Node ; vx_f_d_reg|instruction[2] ; +; To Node ; vx_f_d_reg|curr_PC[8] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.110 ; +; Data Required Time ; 5.468 ; +; Slack ; -0.642 (VIOLATED) ; ++--------------------+---------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.027 ; ; ; ; ; ; +; Data Delay ; 3.112 ; ; ; ; ; ; +; Number of Logic Levels ; ; 4 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 5 ; 2.653 ; 85 ; 0.119 ; 1.144 ; +; Cell ; ; 10 ; 0.338 ; 11 ; 0.000 ; 0.093 ; +; uTco ; ; 1 ; 0.121 ; 4 ; 0.121 ; 0.121 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.196 ; 80 ; 0.000 ; 2.196 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2] ; +; 6.110 ; 3.112 ; ; ; ; ; ; data path ; +; 3.119 ; 0.121 ; FF ; uTco ; 1 ; FF_X77_Y155_N52 ; ; vx_f_d_reg|instruction[2]|q ; +; 3.163 ; 0.044 ; FF ; CELL ; 20 ; FF_X77_Y155_N52 ; High Speed ; vx_f_d_reg|instruction[2]~la_lab/laboutb[14] ; +; 3.379 ; 0.216 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|datac ; +; 3.472 ; 0.093 ; FR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0|combout ; +; 3.478 ; 0.006 ; RR ; CELL ; 2 ; MLABCELL_X76_Y155_N33 ; High Speed ; vx_decode|Decoder_0~0~la_mlab/laboutb[3] ; +; 4.318 ; 0.840 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|datad ; +; 4.398 ; 0.080 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.403 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.522 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.595 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.600 ; 0.005 ; FF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[17] ; +; 4.934 ; 0.334 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|dataf ; +; 4.962 ; 0.028 ; FF ; CELL ; 2 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0|combout ; +; 4.966 ; 0.004 ; FF ; CELL ; 44 ; LABCELL_X81_Y153_N36 ; High Speed ; vx_f_d_reg|i8~0~la_lab/laboutb[4] ; +; 6.110 ; 1.144 ; FF ; IC ; 1 ; FF_X74_Y160_N19 ; High Speed ; vx_f_d_reg|curr_PC[8]|ena ; +; 6.110 ; 0.000 ; FF ; CELL ; 1 ; FF_X74_Y160_N19 ; High Speed ; vx_f_d_reg|curr_PC[8] ; ++---------+---------+----+------+--------+-----------------------+------------+------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.471 ; 2.971 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.261 ; 2.196 ; RR ; IC ; 1 ; FF_X74_Y160_N19 ; High Speed ; vx_f_d_reg|curr_PC[8]|clk ; +; 5.261 ; 0.000 ; RR ; CELL ; 1 ; FF_X74_Y160_N19 ; High Speed ; vx_f_d_reg|curr_PC[8] ; +; 5.471 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.441 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.468 ; 0.027 ; ; uTsu ; 1 ; FF_X74_Y160_N19 ; ; vx_f_d_reg|curr_PC[8] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1996: Setup slack is -0.641 (VIOLATED) +=============================================================================== ++-------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------+ +; Property ; Value ; ++--------------------+----------------------------+ +; From Node ; vx_f_d_reg|instruction[23] ; +; To Node ; vx_d_e_reg|upper_immed[3] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.189 ; +; Data Required Time ; 5.548 ; +; Slack ; -0.641 (VIOLATED) ; ++--------------------+----------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.075 ; ; ; ; ; ; +; Data Delay ; 3.197 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.619 ; 82 ; 0.115 ; 0.720 ; +; Cell ; ; 14 ; 0.451 ; 14 ; 0.000 ; 0.126 ; +; uTco ; ; 1 ; 0.127 ; 4 ; 0.127 ; 0.127 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.142 ; 79 ; 0.000 ; 2.142 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23] ; +; 6.189 ; 3.197 ; ; ; ; ; ; data path ; +; 3.119 ; 0.127 ; RR ; uTco ; 1 ; FF_X97_Y153_N10 ; ; vx_f_d_reg|instruction[23]|q ; +; 3.180 ; 0.061 ; RR ; CELL ; 651 ; FF_X97_Y153_N10 ; High Speed ; vx_f_d_reg|instruction[23]~la_lab/laboutt[6] ; +; 3.862 ; 0.682 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|datac ; +; 3.942 ; 0.080 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0|combout ; +; 3.946 ; 0.004 ; RR ; CELL ; 1 ; LABCELL_X81_Y153_N21 ; High Speed ; vx_forwarding|src2_exe_fwd~0~la_lab/laboutt[14] ; +; 4.070 ; 0.124 ; RR ; IC ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|datab ; +; 4.196 ; 0.126 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0|combout ; +; 4.202 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X82_Y153_N54 ; High Speed ; vx_forwarding|out_fwd_stall~0~la_mlab/laboutb[17] ; +; 4.317 ; 0.115 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|dataf ; +; 4.343 ; 0.026 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1|combout ; +; 4.348 ; 0.005 ; RR ; CELL ; 3 ; LABCELL_X81_Y153_N42 ; High Speed ; vx_forwarding|out_fwd_stall~1~la_lab/laboutb[9] ; +; 5.068 ; 0.720 ; RR ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datad ; +; 5.146 ; 0.078 ; RR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.152 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.518 ; 0.366 ; RR ; IC ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|dataf ; +; 5.546 ; 0.028 ; RF ; CELL ; 1 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0|combout ; +; 5.550 ; 0.004 ; FF ; CELL ; 20 ; LABCELL_X77_Y151_N15 ; High Speed ; vx_d_e_reg|upper_immed[12]~0~la_lab/laboutt[10] ; +; 6.162 ; 0.612 ; FF ; IC ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|dataf ; +; 6.189 ; 0.027 ; FF ; CELL ; 1 ; LABCELL_X81_Y151_N15 ; High Speed ; vx_d_e_reg|i486~3|combout ; +; 6.189 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|d ; +; 6.189 ; 0.000 ; FF ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.417 ; 2.917 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.207 ; 2.142 ; RR ; IC ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3]|clk ; +; 5.207 ; 0.000 ; RR ; CELL ; 1 ; FF_X81_Y151_N16 ; High Speed ; vx_d_e_reg|upper_immed[3] ; +; 5.417 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.387 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.548 ; 0.161 ; ; uTsu ; 1 ; FF_X81_Y151_N16 ; ; vx_d_e_reg|upper_immed[3] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1997: Setup slack is -0.641 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[17] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.240 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.641 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.025 ; ; ; ; ; ; +; Data Delay ; 3.248 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.365 ; 79 ; 0.000 ; 2.365 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.648 ; 82 ; 0.125 ; 0.708 ; +; Cell ; ; 14 ; 0.474 ; 15 ; 0.000 ; 0.091 ; +; uTco ; ; 1 ; 0.126 ; 4 ; 0.126 ; 0.126 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.992 ; 2.992 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.992 ; 2.365 ; RR ; IC ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]|clk ; +; 2.992 ; 0.000 ; RR ; CELL ; 1 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17] ; +; 6.240 ; 3.248 ; ; ; ; ; ; data path ; +; 3.118 ; 0.126 ; RR ; uTco ; 1 ; FF_X97_Y153_N28 ; ; vx_f_d_reg|instruction[17]|q ; +; 3.179 ; 0.061 ; RR ; CELL ; 649 ; FF_X97_Y153_N28 ; High Speed ; vx_f_d_reg|instruction[17]~la_lab/laboutt[18] ; +; 3.675 ; 0.496 ; RR ; IC ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|datac ; +; 3.751 ; 0.076 ; RF ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1|combout ; +; 3.756 ; 0.005 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N57 ; High Speed ; vx_forwarding|i134~1~la_lab/laboutb[19] ; +; 3.881 ; 0.125 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|dataf ; +; 3.907 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2|combout ; +; 3.912 ; 0.005 ; FF ; CELL ; 5 ; LABCELL_X85_Y153_N36 ; High Speed ; vx_forwarding|i134~2~la_lab/laboutb[5] ; +; 4.268 ; 0.356 ; FF ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datac ; +; 4.358 ; 0.090 ; FF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.363 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.046 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.137 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.143 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.851 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.879 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.885 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.165 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.240 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1998: Setup slack is -0.641 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_d_e_reg|rd[3] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.240 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.641 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.242 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.582 ; 80 ; 0.118 ; 0.708 ; +; Cell ; ; 14 ; 0.538 ; 17 ; 0.000 ; 0.111 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3] ; +; 6.240 ; 3.242 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y153_N46 ; ; vx_d_e_reg|rd[3]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 3 ; FF_X77_Y153_N46 ; High Speed ; vx_d_e_reg|rd[3]~la_lab/laboutb[10] ; +; 3.818 ; 0.654 ; FF ; IC ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|datac ; +; 3.902 ; 0.084 ; FR ; CELL ; 1 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0|combout ; +; 3.906 ; 0.004 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N0 ; High Speed ; vx_forwarding|src1_exe_fwd~0~la_lab/laboutt[0] ; +; 4.045 ; 0.139 ; RR ; IC ; 1 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|datac ; +; 4.124 ; 0.079 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4|combout ; +; 4.129 ; 0.005 ; RR ; CELL ; 2 ; LABCELL_X81_Y153_N39 ; High Speed ; vx_forwarding|src1_exe_fwd~4~la_lab/laboutb[7] ; +; 4.247 ; 0.118 ; RR ; IC ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|datab ; +; 4.358 ; 0.111 ; RF ; CELL ; 1 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3|combout ; +; 4.363 ; 0.005 ; FF ; CELL ; 35 ; MLABCELL_X80_Y153_N33 ; High Speed ; vx_forwarding|out_fwd_stall~3~la_mlab/laboutb[2] ; +; 5.046 ; 0.683 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|datac ; +; 5.137 ; 0.091 ; FF ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.143 ; 0.006 ; FF ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.851 ; 0.708 ; FF ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.879 ; 0.028 ; FR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.885 ; 0.006 ; RR ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.165 ; 0.280 ; RR ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.240 ; 0.075 ; RR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #1999: Setup slack is -0.641 (VIOLATED) +=============================================================================== ++-------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------+ +; From Node ; vx_f_d_reg|instruction[0] ; +; To Node ; vx_fetch|VX_Warp_one|real_PC[11] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.240 ; +; Data Required Time ; 5.599 ; +; Slack ; -0.641 (VIOLATED) ; ++--------------------+----------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.031 ; ; ; ; ; ; +; Data Delay ; 3.242 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.757 ; 85 ; 0.119 ; 0.788 ; +; Cell ; ; 14 ; 0.365 ; 11 ; 0.000 ; 0.089 ; +; uTco ; ; 1 ; 0.120 ; 4 ; 0.120 ; 0.120 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.192 ; 80 ; 0.000 ; 2.192 ; +; Cell ; ; 4 ; 0.565 ; 20 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0] ; +; 6.240 ; 3.242 ; ; ; ; ; ; data path ; +; 3.118 ; 0.120 ; RR ; uTco ; 1 ; FF_X77_Y155_N59 ; ; vx_f_d_reg|instruction[0]|q ; +; 3.207 ; 0.089 ; RR ; CELL ; 8 ; FF_X77_Y155_N59 ; High Speed ; vx_f_d_reg|instruction[0]~la_lab/laboutb[19] ; +; 3.334 ; 0.127 ; RR ; IC ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|dataf ; +; 3.359 ; 0.025 ; RR ; CELL ; 1 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0|combout ; +; 3.364 ; 0.005 ; RR ; CELL ; 7 ; MLABCELL_X76_Y155_N51 ; High Speed ; vx_decode|Select_35~0~la_mlab/laboutb[14] ; +; 4.128 ; 0.764 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|dataf ; +; 4.154 ; 0.026 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2|combout ; +; 4.159 ; 0.005 ; RR ; CELL ; 1 ; LABCELL_X79_Y152_N24 ; High Speed ; vx_decode|out_clone_stall~2~la_lab/laboutt[17] ; +; 4.278 ; 0.119 ; RR ; IC ; 1 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|datae ; +; 4.351 ; 0.073 ; RF ; CELL ; 2 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3|combout ; +; 4.355 ; 0.004 ; FF ; CELL ; 40 ; LABCELL_X79_Y152_N54 ; High Speed ; vx_decode|out_clone_stall~3~la_lab/laboutb[16] ; +; 5.143 ; 0.788 ; FF ; IC ; 1 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|dataf ; +; 5.170 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1|combout ; +; 5.176 ; 0.006 ; RR ; CELL ; 172 ; MLABCELL_X76_Y153_N45 ; High Speed ; vx_fetch|i131~1~la_mlab/laboutb[11] ; +; 5.857 ; 0.681 ; RR ; IC ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|dataf ; +; 5.883 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34|combout ; +; 5.889 ; 0.006 ; FF ; CELL ; 1 ; MLABCELL_X69_Y158_N21 ; High Speed ; vx_fetch|VX_Warp_one|i199~34~la_mlab/laboutt[15] ; +; 6.167 ; 0.278 ; FF ; IC ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|datae ; +; 6.240 ; 0.073 ; FR ; CELL ; 1 ; LABCELL_X71_Y158_N48 ; High Speed ; vx_fetch|VX_Warp_one|i199~35|combout ; +; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|d ; +; 6.240 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+-----------------------+------------+--------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.467 ; 2.967 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.257 ; 2.192 ; RR ; IC ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11]|clk ; +; 5.257 ; 0.000 ; RR ; CELL ; 1 ; FF_X71_Y158_N49 ; High Speed ; vx_fetch|VX_Warp_one|real_PC[11] ; +; 5.467 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.437 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.599 ; 0.162 ; ; uTsu ; 1 ; FF_X71_Y158_N49 ; ; vx_fetch|VX_Warp_one|real_PC[11] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + + +Path #2000: Setup slack is -0.641 (VIOLATED) +=============================================================================== ++-------------------------------------------------------------------------------------------+ +; Path Summary ; ++--------------------+----------------------------------------------------------------------+ +; Property ; Value ; ++--------------------+----------------------------------------------------------------------+ +; From Node ; vx_f_d_reg|instruction[12] ; +; To Node ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; +; Launch Clock ; clk ; +; Latch Clock ; clk ; +; Data Arrival Time ; 6.241 ; +; Data Required Time ; 5.600 ; +; Slack ; -0.641 (VIOLATED) ; ++--------------------+----------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +; Setup Relationship ; 2.500 ; ; ; ; ; ; +; Clock Skew ; -0.049 ; ; ; ; ; ; +; Data Delay ; 3.243 ; ; ; ; ; ; +; Number of Logic Levels ; ; 6 ; ; ; ; ; +; Physical Delays ; ; ; ; ; ; ; +; Arrival Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.371 ; 79 ; 0.000 ; 2.371 ; +; Cell ; ; 4 ; 0.627 ; 21 ; 0.000 ; 0.277 ; +; Data ; ; ; ; ; ; ; +; IC ; ; 6 ; 2.786 ; 86 ; 0.104 ; 1.094 ; +; Cell ; ; 14 ; 0.335 ; 10 ; 0.000 ; 0.087 ; +; uTco ; ; 1 ; 0.122 ; 4 ; 0.122 ; 0.122 ; +; Required Path ; ; ; ; ; ; ; +; Clock ; ; ; ; ; ; ; +; IC ; ; 3 ; 2.174 ; 79 ; 0.000 ; 2.174 ; +; Cell ; ; 4 ; 0.565 ; 21 ; 0.000 ; 0.277 ; ++------------------------+--------+-------+-------------+------------+-------+-------+ +Note: Negative delays are omitted from totals when calculating percentages + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Arrival Path ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ +; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ; +; 2.998 ; 2.998 ; ; ; ; ; ; clock path ; +; 0.000 ; 0.000 ; ; ; ; ; ; source latency ; +; 0.000 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 0.277 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 0.356 ; 0.079 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 0.356 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 0.627 ; 0.271 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 2.998 ; 2.371 ; RR ; IC ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]|clk ; +; 2.998 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12] ; +; 6.241 ; 3.243 ; ; ; ; ; ; data path ; +; 3.120 ; 0.122 ; FF ; uTco ; 1 ; FF_X77_Y155_N2 ; ; vx_f_d_reg|instruction[12]|q ; +; 3.164 ; 0.044 ; FF ; CELL ; 18 ; FF_X77_Y155_N2 ; High Speed ; vx_f_d_reg|instruction[12]~la_lab/laboutt[1] ; +; 3.345 ; 0.181 ; FF ; IC ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|datac ; +; 3.432 ; 0.087 ; FR ; CELL ; 1 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0|combout ; +; 3.437 ; 0.005 ; RR ; CELL ; 6 ; MLABCELL_X76_Y155_N42 ; High Speed ; vx_decode|reduce_or_1~0~la_mlab/laboutb[8] ; +; 3.541 ; 0.104 ; RR ; IC ; 1 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|datac ; +; 3.615 ; 0.074 ; RF ; CELL ; 2 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn|combout ; +; 3.620 ; 0.005 ; FF ; CELL ; 49 ; LABCELL_X77_Y155_N33 ; High Speed ; vx_decode|is_wspawn~la_lab/laboutb[3] ; +; 4.714 ; 1.094 ; FF ; IC ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|dataf ; +; 4.740 ; 0.026 ; FF ; CELL ; 1 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2|combout ; +; 4.744 ; 0.004 ; FF ; CELL ; 2 ; LABCELL_X85_Y153_N48 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~2~la_lab/laboutb[12] ; +; 4.858 ; 0.114 ; FF ; IC ; 1 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|dataf ; +; 4.883 ; 0.025 ; FF ; CELL ; 2 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3|combout ; +; 4.889 ; 0.006 ; FF ; CELL ; 473 ; MLABCELL_X86_Y153_N39 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i2094~3~la_mlab/laboutb[7] ; +; 5.441 ; 0.552 ; FF ; IC ; 1 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|dataf ; +; 5.468 ; 0.027 ; FR ; CELL ; 2 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28|combout ; +; 5.474 ; 0.006 ; RR ; CELL ; 18 ; MLABCELL_X94_Y154_N45 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i4143~28~la_mlab/laboutb[11] ; +; 6.215 ; 0.741 ; RR ; IC ; 1 ; MLABCELL_X90_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~924|dataf ; +; 6.241 ; 0.026 ; RF ; CELL ; 1 ; MLABCELL_X90_Y144_N21 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|i5167~924|combout ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28]|d ; +; 6.241 ; 0.000 ; FF ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+-----------------------+------------+---------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Data Required Path ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ +; 2.500 ; 2.500 ; ; ; ; ; ; latch edge time ; +; 5.449 ; 2.949 ; ; ; ; ; ; clock path ; +; 2.500 ; 0.000 ; ; ; ; ; ; source latency ; +; 2.500 ; 0.000 ; ; ; 1 ; PIN_M23 ; ; clk ; +; 2.500 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|i ; +; 2.777 ; 0.277 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input|o ; +; 2.840 ; 0.063 ; RR ; CELL ; 1 ; IOIBUF_X78_Y196_N47 ; ; clk~input~io_48_lvds_tile/ioclkin[2] ; +; 2.840 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|inclk ; +; 3.065 ; 0.225 ; RR ; CELL ; 14237 ; CLKCTRL_2L_G_I6 ; ; clk~inputCLKENA0|outclk ; +; 5.239 ; 2.174 ; RR ; IC ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28]|clk ; +; 5.239 ; 0.000 ; RR ; CELL ; 1 ; FF_X90_Y144_N23 ; High Speed ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; +; 5.449 ; 0.210 ; ; ; ; ; ; clock pessimism removed ; +; 5.419 ; -0.030 ; ; ; ; ; ; clock uncertainty ; +; 5.600 ; 0.181 ; ; uTsu ; 1 ; FF_X90_Y144_N23 ; ; vx_decode|VX_Context_three|vx_register_file_master|registers[28][28] ; ++---------+---------+----+------+--------+---------------------+------------+--------------------------------------------------------------------------+ + +---------------------------- +; Extra Fitter Information ; +---------------------------- +HTML report is unavailable in plain text report export. + +